Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1998
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CDB5180
Evaluation Board for the CS5180
Features
l
Buffered Serial Data Output
l
Input Signal Conditioning Amplifiers
l
On-board 3 Volt regulator
l
Analog/Digital Patch Areas
l
Analog BNC Input Connector
l
Provision for optional precision voltage
reference
l
Compatible with CDBCapture+ board
l
Provision for evaluation of CS5180 with
internal digital filter enabled or disabled (one-
bit mode)
Description
The CDB5180 is an evaluation board that expedites the
laboratory characterization of the CS5180 A/D convert-
er. The CS5180 is a 16-bit high speed delta-sigma
converter with a serial output having an output word rate
of up to 400 kHz. The board accepts single-ended or dif-
ferential input signals and buffers the serial output of the
CS5180 before sending it to a header for off-board use.
The output header signals on the evaluation board are
designed to be compatible with the CDBCapture+
board. An on-board 3 Volt regulator allows the CS5180
to be evaluated with either 3 or 5 Volt digital supplies.
The converter can be operated with it's internal voltage
reference although the layout makes provision for add-
ing an external precision reference as a user-supplied
option.
ORDERING INFORMATION
CDB5180
Evaluation Board
I
CS5180
MCLK
AIN+
AIN-
VREFOUT
VREFIN
SCLK
SDATA
SDATA
FSO
CLOCK
GENERATOR
25.6 MHz
ANALOG
SIGNAL
CONDITIONING
EXTERNAL
PRECISION
REFERENCE
OPTION
AIN
10 POS.
SERIAL
OUTPUT
HEADER
BUFFERS
+3 V
REGULATOR
+5 VD
+3 VD
+5 VA
5 V DIGITAL
5 V ANALOG
+15 V
-15 V
AGND
DGND
RESET and
SYNC
CONDITIONING
RESET
SYNC
RESET
SYNC
DEC `98
DS259DB1
CDB5180
2
DS259DB1
POWER SUPPLIES AND VOLTAGE
REFERENCE
Figure 1 illustrates the power supply and precision
voltage reference circuits. The CDB5180 evalua-
tion board has inputs for 4 regulated voltages,
+5 Volts Digital, +5 Volts Analog, +15 Volts, and
-15 Volts. As an option, one 5 Volt power supply
may be used to power both the analog and digital
portions of the converter. This is done by installing
HDR17 and connecting the 5 Volt supply to post
J7. An on-board 3 Volt regulator allows for the
converter's digital circuitry to be powered from ei-
ther 5 Volts or 3 Volts. This selection is achieved
by setting header HDR13 to either the +5VD or
+3VD position. The plus and minus 15 Volts are
used to power the analog signal conditioning cir-
cuits external to the converter. The analog 5 Volt
supply can be used to power a precision 2.5 Volt
reference, an LT1019-2.5 or equivalent, which can
be substituted for the converter's on-board refer-
ence to achieve lower drift. The board is supplied
with the external reference and it's passive compo-
nents depopulated. If it is desired to use an exter-
nal reference, then the following steps must be
completed.
1) Remove zero-ohm resistor R32 and install a
zero-ohm resistor in the R33 position.
2) Install the following components: U10, C38,
C56, R22, C59, and R25.
3) Set the reference voltage to the desired value by
adjusting potentiometer R22.
The output of the internal reference is connected to
the operational amplifiers through zero-ohm resis-
tor R54. If it is desired to use the external reference
to drive the signal conditioning circuits, then R54
must be removed and a zero-ohm resistor installed
in position R55.
Z3
1N6276A
Z2
1N6276A
.1 F
X7R
.1 F
X7R
C57
C58
C46
68 F
C52
68 F
AGND
+
+
+15 V
-15 V
+5 VA
C38
10 F
+
.1 F
X7R
C56
AGND
U10
4
3
7
5
6
GND TEMP
HIR
TRIM
OUT
IN
LT1019CN8_2P5
2
TP12
VREF_AMP
FIGURE 4
R22
20 K
CW
PRECISION VOLTAGE REFERENCE OPTION
GND
C53
.1 F
X7R
C26
68 F
AGND
+5 VA
+
L1
FERRITE
BEAD
GND
GND
GND
AGND
Z1
1N6276A
.1 F
X7R
C22
C3
68 F
+
2
1
HDR17
3
VIN
VOUT
ADJ
LT317AT
1
R11
249
R12
392
2
.1 F
X7R
C21
C2
68 F
+
+3 VD
HDR13
+5 VD
L2
FERRITE
BEAD
1
2
HDR14
VCCIO
C59
10 F
+
VDDD
U7
Z4
P6KE6V8P
AGND
J8
J7
J3
J4
J5
GND
AGND
JP1
JP2
JP3
R25
2.1
R55
0
R33
0
VREFIN
FIGURE 5
NOT POPULATED
Figure 1. Power Supplies and Voltage Reference
CDB5180
DS259DB1
3
CLOCK OSCILLATOR AND BUFFER
Figure 2 illustrates the circuitry used to generate
the clock signal MCLK that drives the CS5180.
The board contains a 25.6 MHz nominal oscillator
as well as a BNC connector for use with an external
clock source. The on-board oscillator is buffered
and inverted to form a complementary clock signal,
MCLKB, that is used in the SYNC and RESET cir-
cuits. Selection of internal clock or external clock
is done by setting header HDR3 to either the OSC
or BNC position. Using the on-board oscillator
will result in an output word rate of 400.0 kHz.
RESET AND SYNC CIRCUITS
Figure 3 illustrates the circuits used for generating
the chip RESET and SYNC signals. Two manual
pushbuttons are provided for generating the RE-
SET and SYNC signals, which are synchronized to
the falling edge of the master clock by means of a
flip-flop before being sent to the CS5180. Header
HDR2, not populated, is provided for connecting to
external SYNC and RESET signals. To use the ex-
ternal signals, set headers HDR6 and HDR7 to the
EXT position and apply the external signals at the
HDR2 thru-holes.
INPUT SIGNAL CONDITIONING
Figure 4 illustrates the circuitry used to condition
the analog input signal. A single-ended input is fed
in via the BNC connector to a pair of operational
amplifiers. The signal is buffered and also inverted
to form differential signals. These signals are then
fed to two more op-amps where the voltage refer-
ence is added to each of them to bring the common
mode voltage up to the range required by the con-
verter. Potentiometer R41 is available to adjust the
offsets on the two op-amp outputs to be equal, so
that with zero volts in at J2, the converter reads ze-
ro. The two signals are then passed through an at-
tenuating resistor network before being input to the
converter. A 1.0 Volt peak-peak signal input at the
BNC connector will result in nominal 0.2849 Volt
peak-peak fully differential signals being applied
between the AIN+ and AIN- pins of the converter.
If the external signal is not single ended but is al-
ready differential, it can be input through connector
J6 where it is capacitively coupled in and offset to
the proper common mode value before being ap-
plied to the converter. The settings of HDR8 and
HDR9 select whether the input signal will be input
through the BNC connector as a single-ended sig-
nal or through J6 as a differential signal. To use the
J1
BNC
GND
GND
49.9
R36*
VCCIO
R35
10
C9
0.1 F
X7R
GND
14
4
2
VCC
EN
GND
HDR3
8
25.6 MHz Nominal
U1
MCLK
Figures 5 and 6
GND
1
2
3
GND
U3
NC7SZ04M5
VCC
4
5
C16
0.1 F
X7R
VCCIO
MCLKB
Figure 3
R56
0
11
1
R57
0
EXTCLK
BNC
OSC
CLKOSC
*Not Populated
Figure 2. Clock Oscillator and Buffer
CDB5180
4
DS259DB1
DC-coupled signal from the BNC connector J2, set
headers HDR8 and HDR9 to the BNC position. To
feed a capacitively coupled signal from J6 to the
CS5180, set HDR8 and HDR9 to the XLR position.
Alternatively, the differential signals can be ap-
plied by feeding them into test points BAL+ and
BAL-. Note that connector J6, R20, R21, C40, and
C41 do not come installed on the board and must be
obtained and soldered in by the user before a bal-
anced signal can be applied to the board input. J6,
R20, R21, C40, and C41 are not required when a
single-ended signal is being applied to connector
J2, since the op-amps will convert and apply a bal-
anced signal to the CS5180.
CS5180 CONVERTER CIRCUITS
The connections to the CS5180 chip are illustrated
in Figure 5. The analog and digital supply voltages
are all decoupled with X7R ceramic capacitors
close to the device. In addition to the 0.1 F ceram-
ic capacitors, there are 1 and 10 F electrolytic caps
on the voltage reference input and output lines to
minimize noise on the references. An LED is con-
nected to the MFLAG signal and when on, indi-
cates that data from the converter may be invalid
due to an input overload. Header plugs are provid-
ed to change the MODE pin, allowing for raw 1-bit
modulator data to be output, and for placing the
chip in the power-down mode. For normal opera-
tion, header HDR15 should not be installed. To use
the CS5180 internal digital filter, the mode pin
should be set high by removing header HDR16. If
HDR16 is installed, the internal digital filter is dis-
abled and the direct unfiltered modulator output
will be presented on the serial data pin SDO. For
this condition, header HDR12 should be set to the
MCLK position.
OUTPUT BUFFERS AND HEADER
CONNECTIONS
Figure 6 illustrates the circuitry for sending the out-
put data off-board and the associated header con-
nections. The CS5180 outputs data in a serial
format only, along with the serial clock and the
frame sync signal, FSO. These signals are buffered
externally to the CS5180 and then made available
on the 10-pin header HDR1. Header HDR12 can
be used to select between sending the serial clock
SCLK or the master clock, MCLK, to pin 8 of
HDR1. If the evaluation board is being used with
the CDBCapture+ board then the CS5180 should
be operated in Mode 1 (internal digital filter en-
abled), and HDR12 should be set to the SCLK po-
sition, where SCLK is connected to HDR1. If the
GND
GND
GND
GND
GND
GND
GND
RESET
S2
R4
2 K
SNYC
S1
R13
2 K
VCCIO
VCCIO
C36
.1 F
X7R
C36
.1 F
X7R
R28
49.9 K
R29
49.9 K
C8
0.1 F
X7R
VCCIO
MCLKB
Figure 2
4
3
2
1
10
11
12
13
1/PRE
1CLK
1D
1/CLR
2/PRE
2CLK
2D
2/CLR
U11
MC74HC74AD
14
5
6
9
8
7
VCC
1Q
1/Q
2Q
2/Q
GND
VCCIO
SNYC
Figure 5
RESETB
Figure 5
SW
HDR7
EXT
SW
HDR6
EXT
2 EXT_SYNC
4 EXT_RESETB
1
3
HDR2
Figure 3. Reset and Sync Circuits
CDB5180
DS259DB1
5
evaluation board is being used without the CDB-
Capture+ board and the CS5180 is operating in
Mode 0 (raw modulator output), then HDR12
should be set to the MCLK position, feeding the
master clock signal to connector HDR1. Nor-gates
U13 and U14 will automatically reconstruct the
RTZ data from the modulator bitstream so that it
can be sampled on the rising or falling edge of
MCLK.
USING THE EVALUATION BOARD
Although the evaluation board can be connected di-
rectly to a microprocessor that has a serial port and
is fast enough to process up to 400K words/second,
it can be more convenient to use the evaluation
board in conjunction with the Crystal CDBCap-
ture+ Board, which has been designed specifically
to interface with high speed converters and has a
10-pin header that is compatible with the signals on
header HDR1 of the evalboard. Connect the appro-
priate power supply voltages to the binding posts of
the board. Use high quality linear power supplies
that are low in noise, ripple, and line frequency
(50/60 Hz) interference. If both 5 V digital and 5 V
analog supplies are to be used, make sure that
HDR17 is removed to prevent contention between
the supplies. Total 5 Volt current requirements are
approximately 0.2 Amps. The load on the plus and
minus 15 Volt supplies will be under 0.1 Ampere
each. The Capture Plus board is then connected to
a PC and Crystal's software is used to configure the
board and to capture data.
10 K
R15
-
+
-
+
-
+
-
+
J2
BNC
AGND
2 K
R5
AGND
AGND
-15 V
.1 F
V-
4
3
2
V+
8
U6
1
LM6172IM
R7
+15 V
C17 .1 F
X7R
AGND
2 K
C18
X7R
5
6
R6
2 K
U6
7
LM6172IM
R8
2 K
R38
1 K
AGND
VREF_AMP
Figure 1
AGND AGND
R39
10 F
R18
10 K
+
R19
10 K
5
6
R9
2 K
U9
7
LM6172IM
AGND
-15 V
.1 F
V-
4
3
2
LM6172IM
C19
X7R
BNC
HDR9
XLR
BNC
HDR8
XLR
AGND
U9
1
8
V+
R10
2 K
AGND
AGND
+
C42
10 F
R40
10 K
+15 V
C20 .1 F
X7R
1 K
CW
R39
9.53 K
VREF_AMP
Figure 1
R41
R21
10 K
AGND
BAL-
10 F
C40
+
R16
1.0 K
R17
1.0 K
C41
10 F
R20
10 K
R30
100
R1
301
R2
301
BAL+
AGND
AGND
+
J6
2
3
1
XLR_F
AIN+
AIN-
VREF_AMP
Figure 1
(Not Populated)
TP14
Figure 5
TP13
Figure 5
*
*
*
*
*
* NOT POPULATED
Figure 4. Input Signal Conditioning Circuitry
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