1
Copyright
Cirrus Logic, Inc. 2002
(All Rights Reserved)
http://www.cirrus.com
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CS5351
108 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-Bit Conversion
108 dB Dynamic Range
-98 dB THD+N
System Sampling Rates up to 192 kHz
Single-Ended Analog Inputs
Less than 150 mW Power Consumption
High Pass Filter or DC Offset Calibration
Supports Logic Levels Between 5 and 2.5V
Linear Phase Digital Anti-Alias Filtering
Overflow Detection
Functionally Compatible with the CS5361
General Description
The CS5351 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion and anti-alias filtering, generating 24-
bit values for both left and right inputs in serial form at
sample rates up to 192 kHz per channel.
The CS5351 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5351 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
A/V receivers, DVD-R, CD-R, digital mixing consoles,
and effects processors.
ORDERING INFORMATION
CS5351-KS
-10 to 70 C
24-pin SOIC
CS5351-BS
-40 to 85 C
24-pin SOIC
CS5351-KZ
-10 to 70 C
24-pin TSSOP
CS5351-BZ
-40 to 85 C
24-pin TSSOP
CDB5351
Evaluation Board
Voltage Reference
Serial Audio Interface
Digital
Filter
High
Pass
Filter
High
Pass
Filter
Decimation
Digital
Filter
Decimation
DAC
-
+
S/H
DAC
-
+
S/H
AINR
SCLK
SDOUT
MCLK
RST
VQ
LRCK
AINL
FILT+
M/S
HPF
MODE0
MODE1
REFGND
V
L
LP Filter
LP Filter
I2S/LJ
MDIV
SEPT `02
DS565PP2
CS5351
2
DS565PP2
TABLE OF CONTENTS
1 PIN DESCRIPTIONS ................................................................................................................. 4
2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 5
3 APPLICATIONS ......................................................................................................................... 6
3.1 Operational Mode/Sample Rate Range Select .................................................................. 6
3.2 System Clocking ................................................................................................................ 6
3.2.1 Master Mode ......................................................................................................... 7
3.2.2 Slave Mode ........................................................................................................... 8
3.3 Power-up Sequence .......................................................................................................... 8
3.4 Analog Connections ........................................................................................................... 8
3.5 High Pass Filter and DC Offset Calibration ....................................................................... 9
3.6 Overflow Detection ............................................................................................................. 9
3.6.1 OVFL Output Timing ........................................................................................... 10
3.7 Grounding and Power Supply Decoupling ....................................................................... 10
3.8 Synchronization of Multiple Devices ................................................................................ 10
4 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 11
ANALOG CHARACTERISTICS (CS5351-KS/KZ) .................................................................. 11
ANALOG CHARACTERISTICS (CS5351-BS/BZ) .................................................................. 12
DIGITAL DECIMATION FILTER CHARACTERISTICS .......................................................... 13
DC ELECTRICAL CHARACTERISTICS................................................................................. 16
DIGITAL CHARACTERISTICS ............................................................................................... 16
THERMAL CHARACTERISTICS............................................................................................ 16
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 17
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 18
5 PARAMETER DEFINITIONS ................................................................................................... 21
6 PACKAGE DIMENSIONS
..................................................................................................... 22
7 ADDENDUM ............................................................................................................................ 24
LIST OF FIGURES
Figure 1. Typical Connection Diagram ............................................................................................ 5
Figure 2. CS5351 Master Mode Clocking ....................................................................................... 7
Figure 3. CS5351 Recommended Analog Input Buffer ................................................................... 9
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-
ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
CS5351
DS565PP2
3
Figure 4. Single Speed Mode Stopband Rejection ....................................................................... 14
Figure 5. Single Speed Mode Transition Band ............................................................................. 14
Figure 6. Single Speed Mode Transition Band (Detail)................................................................. 14
Figure 7. Single Speed Mode Passband Ripple ........................................................................... 14
Figure 8. Double Speed Mode Stopband Rejection...................................................................... 14
Figure 9. Double Speed Mode Transition Band ............................................................................ 14
Figure 10. Double Speed Mode Transition Band (Detail) ............................................................. 15
Figure 11. Double Speed Mode Passband Ripple ........................................................................ 15
Figure 12. Quad Speed Mode Stopband Rejection ...................................................................... 15
Figure 13. Quad Speed Mode Transition Band............................................................................. 15
Figure 14. Quad Speed Mode Transition Band (Detail) ................................................................ 15
Figure 15. Quad Speed Mode Passband Ripple........................................................................... 15
Figure 16. Master Mode, Left Justified SAI ................................................................................... 19
Figure 17. Slave Mode, Left Justified SAI ..................................................................................... 19
Figure 18. Master Mode, I
2
S SAI .................................................................................................. 19
Figure 19. Slave Mode, I
2
S SAI .................................................................................................... 19
Figure 20. OVFL Output Timing .................................................................................................... 19
Figure 21. Left-Justified Serial Audio Interface ............................................................................. 20
Figure 22. I
2
S Serial Audio Interface............................................................................................. 20
Figure 23. OVFL Output Timing, I2S Format ................................................................................ 20
Figure 24. OVFL Output Timing, Left-Justified Format ................................................................. 20
Figure 25. CS5351/CS5361 Analog Input Buffer .......................................................................... 24
LIST OF TABLES
Table 1. CS5351 Mode Control ............................................................................................................. 6
Table 2. CS5351 Common Master Clock Frequencies ........................................................................ 7
Table 3. CS5351 Slave Mode Clock Ratios .......................................................................................... 8
CS5351
4
DS565PP2
1
PIN DESCRIPTIONS
RST
1
24
FILT+
M/S
2
23
REFGND
LRCK
3
22
VQ3
SCLK
4
21
AINR
MCLK
5
20
VQ2
VD
6
19
VA
GND
7
18
GND
VL
8
17
VQ1
SDOUT
9
16
AINL
MDIV
10
15
OVFL
HPF
11
14
M1
I
2
S/LJ
12
13
M0
Pin Name
#
Pin Description
RST
1
Reset (Input) - The device enters a low power mode when low.
M/S
2
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
LRCK
3
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
4
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
GND
7,18
Ground (Input) - Ground reference. Must be connected to analog ground.
VL
8
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
9
Serial Audio Data Output (Output) - Output for two's complement serial audio data.
MDIV
10
MCLK Divider (Input) - Enables a master clock divide by two function.
HPF
11
High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
I
2
S/LJ
12
Serial Audio Interface Format Select (Input) -Selects either the left-justified or I
2
S format for the SAI.
M0
M1
13,
14
Mode Selection (Input) - Determines the operational mode of the device.
OVFL
15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
AINR
AINL
16,
21
Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specifi-
cation table.
VQ1
VQ2
VQ3
17,
20,
22
Quiescent Voltage (Input/Output) - Filter connection for the internal quiescent reference voltage.
VA
19
Analog Power (Input) - Positive power supply for the analog section.
REF_GND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
CS5351
DS565PP2
5
2
TYPICAL CONNECTION DIAGRAM
F ILT +
V
D
0 .1
F
A /D C O N V E R T E R
S C L K
C S 5 3 51
M / S
M C L K
A IN L
A IN R
V Q
47
F
+
R S T
V A
V
L
+ 5 V
1
F
+ 5 V to 2.5V
5 .1
1
F
+
+
+
S D O U T
G N D
I
2
S /LJ
L R C K
G N D
P o w er D o w n
a nd M od e
S e tting s
A u d io D a ta
P ro c e s s o r
Tim ing L o g ic
a n d C lo ck
0 .1
F
0 .1
F
0.1
F
0 .1
F
H P F
M 0
M1
R E F G N D
M DIV
+5 V to 3 .3 V
1
F
0 .1
F
1
F
+
Analog
Input
Buffer
(Figure 3)
O V FL
V L
10 k
3
V Q 2
V Q 1
Figure 1. Typical Connection Diagram
CS5351
6
DS565PP2
3 APPLICATIONS
3.1
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5351 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 1.
3.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchro-
nously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial
clocks. The device also includes a master clock divider in Master Mode where the master clock will be
internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode
the MDIV pin needs to be disabled, set to logic 0.
M1 (Pin 14) M0 (Pin 13)
MODE
Output Sample Rate (Fs)
0
0
Single Speed Mode
2kHz - 50kHz
0
1
Double Speed Mode
50kHz - 100kHz
1
0
Quad Speed Mode
100kHz - 192kHz
1
1
Reserved
Table 1. CS5351 Mode Control
CS5351
DS565PP2
7
3.2.1
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 2. Refer to Table 2 for common master clock frequencies
128
256
64
M0
M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
2
4
1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
2
1
0
1
MCLK
MDIV
Figure 2. CS5351 Master Mode Clocking
SAMPLE RATE (kHz)
MDIV = 0
MCLK (MHz)
MDIV = 1
MCLK (MHz)
32
8.192
16.384
44.1
11.2896
22.5792
48
12.288
24.576
64
8.192
16.384
88.2
11.2896
22.5792
96
12.288
24.576
176.4
11.2896
22.5792
192
12.288
24.576
Table 2. CS5351 Common Master Clock Frequencies
CS5351
8
DS565PP2
3.2.2
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived
from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously
derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3
for required clock ratios.
*Available when MDIV = 1 (for Master Mode)
Table 3. CS5351 Slave Mode Clock Ratios
3.3
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
3.4
Analog Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject
signals within the stopband of the filter. However, there is no rejection for input signals which are
(n
6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3 which shows the sug-
gested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum
source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such
as general purpose ceramics) must be avoided since these can degrade signal linearity.
Please see the Addendum at the end of the datasheet for an analog input buffer that can be used with both
the CS5351 as well as the CS5361 with a simple change in the bill of materials.
Single Speed Mode
Fs = 2kHz to 50kHz
Double Speed Mode
Fs = 50kHz to 100kHz
Quad Speed Mode
Fs = 100kHz to 192kHz
MCLK/LRCK Ratio
256x (512x)*
128x (256x)*
128x (256x)*
SCLK/LRCK Ratio
32x, 64x, 128x
32x, 64x
64x
CS5351
DS565PP2
9
3.5
High Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into
the A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding "clicks" when switching between devices in
a multichannel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is
frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it
possible to perform a system DC offset calibration by:
1) Running the CS5351 with the high pass filter enabled until the filter settles.See the Digital Filter Char-
acteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5351.
3.6
Overflow Detection
The CS5361 includes overflow detection on both the left and right channels. This time multiplexed infor-
mation is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go
to a logical low as soon as an overrange condition in either channel is detected. The data will remain low
V Q
10k
+
6 3 4
6 3 4
9 1
9 1
+
-
-
2 7 0 0 p F
4 7 0 p F
4 7 0 p F
C O G
C O G
1 0 0 u F
1 0 0 u F
C S 5 3 5 1 A I N L
C S 5 3 5 1 A I N R
A I N L
A I N R
C O G
10k
2 7 0 0 p F
C O G
Figure 3. CS5351 Recommended Analog Input Buffer
CS5351
10
DS565PP2
as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to
detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R
data will return to a logical high if there has not been any other overrange condition detected. Please note
that an overrange condition on either channel will restart the timeout period for both channels.
3.6.1
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I
2
S format,
the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both
cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified
format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of
LRCK would latch the left channel overflow status. In I
2
S format, the falling edge of LRCK would latch
the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
3.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5351 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The
FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electri-
cal path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and
power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS
inputs.
3.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351's in the sys-
tem. If only one master clock source is needed, one solution is to place one CS5351 in Master mode, and
slave all of the other CS5351's to the one master. If multiple master clock sources are needed, a possible
solution would be to supply all clocks from the same external source and time the CS5351 reset with the
inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
CS5351
DS565PP2
11
4
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (CS5351-KS/KZ)
(Test conditions (unless otherwise speci-
fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance char-
acteristics are derived from measurements taken at T
A
= 25
C, VL = VD = 3.3V and VA = 5.0V. Min/Max
performance characteristics are guaranteed over the specified operating temperature and voltages.)
Note:
1. Referred to the typical full-scale input voltage
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode
Fs = 48kHz
Dynamic Range
A-weighted
unweighted
102
99
108
105
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-98
-85
-45
-92
-
-
dB
dB
dB
Double Speed Mode
Fs = 96kHz
Dynamic Range
A-weighted
unweighted
40kHz bandwidth unweighted
102
99
-
108
105
102
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
40kHz bandwidth
-1dB
THD+N
-
-
-
-
-98
-85
-45
-95
-92
-
-
-
dB
dB
dB
dB
Quad Speed Mode
Fs = 192kHz
Dynamic Range
A-weighted
unweighted
40kHz bandwidth unweighted
102
99
-
108
105
102
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
40kHz bandwidth
-1dB
THD+N
-
-
-
-
-98
-85
-45
-95
-92
-
-
-
dB
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation
-
95
-
dB
Interchannel Phase Deviation
-
0.0001
-
Degree
DC Accuracy
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-
5
%
Gain Drift
-
100
-
ppm/C
Offset Error
HPF enabled
HPF disabled
-
-
0
100
-
-
LSB
LSB
Analog Input Characteristics
Full-scale Input Voltage
0.95
1.0
1.05
Vrms
Input Impedance
18
-
-
k
CS5351
12
DS565PP2
ANALOG CHARACTERISTICS (CS5351-BS/BZ)
(Test conditions (unless otherwise speci-
fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance char-
acteristics are derived from measurements taken at T
A
= 25
C, VL = VD = 3.3V and VA = 5.0V. Min/Max
performance characteristics are guaranteed over the specified operating temperature and voltages.)
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode
Fs = 48kHz
Dynamic Range
A-weighted
unweighted
101
98
108
105
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-98
-85
-45
-91
-
-
dB
dB
dB
Double Speed Mode
Fs = 96kHz
Dynamic Range
A-weighted
unweighted
40kHz bandwidth unweighted
101
98
-
108
105
102
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
40kHz bandwidth
-1dB
THD+N
-
-
-
-
-98
-85
-45
-95
-91
-
-
-
dB
dB
dB
dB
Quad Speed Mode
Fs = 192kHz
Dynamic Range
A-weighted
unweighted
40kHz bandwidth unweighted
101
98
-
108
105
102
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
-1 dB
-20 dB
-60 dB
40kHz bandwidth
-1dB
THD+N
-
-
-
-
-98
-85
-45
-95
-91
-
-
-
dB
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation
-
95
-
dB
Interchannel Phase Deviation
-
0.0001
-
Degree
DC Accuracy
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-
5
%
Gain Drift
-
100
-
ppm/C
Offset Error
HPF enabled
HPF disabled
-
-
0
100
-
-
LSB
LSB
Analog Input Characteristics
Full-scale Input Voltage
0.9
1.0
1.1
Vrms
Input Impedance
18
-
-
k
CS5351
DS565PP2
13
DIGITAL DECIMATION FILTER CHARACTERISTICS
Notes: 2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
3. The filter frequency response scales precisely with Fs.
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode (2kHz to 50kHz sample rates)
Passband
(-0.1 dB)
(Note 3)
0
-
0.47
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 3)
0.58
-
-
Fs
Stopband Attenuation
-95
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
12/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
Double Speed Mode (50kHz to 100kHz sample rates)
Passband
(-0.1 dB)
(Note 3)
0
-
0.45
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 3)
0.68
-
-
Fs
Stopband Attenuation
-92
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
9/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
Quad Speed Mode (100kHz to 192kHz sample rates)
Passband
(-0.1 dB)
(Note 3)
0
-
0.24
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 3)
0.78
-
-
Fs
Stopband Attenuation
-97
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
5/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
High Pass Filter Characteristics
Frequency Response
-3.0 dB
-0.13 dB
(Note 2)
-
1
20
-
-
Hz
Hz
Phase Deviation
@ 20Hz
(Note 2)
-
10
-
Deg
Passband Ripple
-
-
0
dB
Filter Settling Time
10
5
/Fs
s
CS5351
14
DS565PP2
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
plit
ude
(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
A
m
pl
i
t
ud
e
(
dB
)
Figure 4. Single Speed Mode Stopband Rejection
Figure 5. Single Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
Frequency (normalized to Fs)
A
m
plit
ude
(
d
B
)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
A
m
p
l
i
t
ud
e
(
dB
)
Figure 6. Single Speed Mode Transition Band (Detail)
Figure 7. Single Speed Mode Passband Ripple
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
plit
u
d
e
(
dB
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
A
m
pl
it
ud
e
(
d
B
)
Figure 8. Double Speed Mode Stopband Rejection
Figure 9. Double Speed Mode Transition Band
CS5351
DS565PP2
15
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.40
0.43
0.45
0.48
0.50
0.53
0.55
Frequency (normalized to Fs)
A
m
p
lit
u
d
e
(
d
B
)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
A
m
p
lit
u
d
e
(
d
B
)
Figure 10. Double Speed Mode Transition Band (Detail)
Figure 11. Double Speed Mode Passband Ripple
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
plit
ude
(
d
B
)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
Frequency (normalized to Fs)
A
m
pli
t
ude
(
d
B
)
Figure 12. Quad Speed Mode Stopband Rejection
Figure 13. Quad Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
Frequency (normalized to Fs)
A
m
plit
u
d
e
(
dB
)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
A
m
p
lit
u
d
e
(
d
B
)
Figure 14. Quad Speed Mode Transition Band (Detail)
Figure 15. Quad Speed Mode Passband Ripple
CS5351
16
DS565PP2
DC ELECTRICAL CHARACTERISTICS
(GND = 0V, all voltages with respect to ground.
MCLK=12.288 MHz; Master Mode)
Notes: 4. Power Down Mode is defined as RST = Low with all clocks and data lines held static.
5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
THERMAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies:
Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
4.75
3.1
2.37
5.0
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current
VA
(Normal Operation)
VL,VD = 5 V
VL,VD = 3.3V
I
A
I
D
I
D
-
-
-
17.5
22
14.5
21
26
17
mA
mA
mA
Power Supply Current
VA
(Power-Down Mode)(Note 4)
VL,VD=5V
I
A
I
D
-
-
2
2
-
-
mA
mA
Power Consumption
(Normal Operation)
VL, VD=5V
VL, VD = 3.3V
(Power-Down Mode)
-
-
-
-
-
-
198
135
20
235
161
-
mW
mW
mW
Power Supply Rejection Ratio
(1 kHz)
(Note 5)
PSRR
-
65
-
dB
V
Q
Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
2.5
25
0.01
-
-
-
V
k
mA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
5
35
0.01
-
-
-
V
k
mA
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
(% of VL)
V
IH
70%
-
-
V
Low-Level Input Voltage
(% of VL)
V
IL
-
-
30%
V
High-Level Output Voltage at I
o
= 100 uA
(% of VL)
V
OH
70%
-
-
V
Low-Level Output Voltage at I
o
=100 uA
(% of VL)
V
OL
-
-
15%
V
OVFL Current Sink
I
ovfl
-
-
4.0
mA
Input Leakage Current
I
in
-
-
10
A
Parameter
Symbol
Min
Typ
Max
Unit
Allowable Junction Temperature
-
-
135
C
Junction to Ambient Thermal Impedance
JA
-
70
-
C/W
Ambient Operating Temperature (Power Applied)
-KS/KZ
-BS/BZ
T
A
T
A
-10
-40
-
-
+70
+85
C
C
CS5351
DS565PP2
17
ABSOLUTE MAXIMUM RATINGS
(GND = 0V, All voltages with respect to ground.) (Note 8)
Notes: 6. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC
latch-up.
7. The maximum over/under voltage is limited by the input current.
8. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
-
-
-
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 6)
I
in
-
-
10
mA
Analog Input Voltage
(Note 7)
V
IN
GND-0.7
-
VA+0.7
V
Digital Input Voltage
(Note 7)
V
IND
-0.7
-
VL+0.7
V
Ambient Operating Temperature (Power Applied)
T
A
-50
-
+95
C
Storage Temperature
T
stg
-65
-
+150
C
CS5351
18
DS565PP2
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V;
Logic "1" = VL = 2.37V to 5.25V, VA = 5V
5%, VD = 3.1V to 5.25V, C
L
= 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Input Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
50
100
192
kHz
kHz
kHz
OVFL to LRCK edge setup time
t
setup
16/f
sclk
-
-
s
OVFL to LRCK edge hold time
t
hold
1/f
sclk
-
-
s
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4kHz
Fs = 48, 96, 192kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period
t
clkw
40
-
1953
ns
MCLK Pulse Width High
t
clkh
15
-
-
ns
MCLK Pulse Width Low
t
clkl
15
-
-
ns
Master Mode
SCLK falling to LRCK
t
mslr
-20
-
20
ns
SCLK falling to SDOUT valid
t
sdo
0
-
40
ns
SCLK Duty Cycle
-
50
-
%
SCLK Output Frequency
-
50
-
%
Slave Mode
Single Speed
Output Sample Rate
Fs
2
-
50
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
163
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
40
ns
SCLK falling to LRCK edge
t
slrd
-20
-
20
ns
Double Speed
Output Sample Rate
Fs
50
-
100
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
163
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
40
ns
SCLK falling to LRCK edge
t
slrd
-20
-
20
ns
Quad Speed
Output Sample Rate
Fs
100
-
192
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
81
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
20
ns
SCLK falling to LRCK edge
t
slrd
-10
-
10
ns
CS5351
DS565PP2
19
SCLK output
t msl
r
SDOUT
t sd
o
LRCK
output
MSB
MSB-1
SCLK input
LRCK input
sclkl
t
dss
t
MSB
MSB-1
MSB-2
lrdss
t
sclkh
t
t
sclkw
SDOUT
s rd
l
t
Figure 16. Master Mode, Left Justified SAI
Figure 17. Slave Mode, Left Justified SAI
SCLK
output
t mslr
SDOUT
t
sdo
LRCK output
MSB
SCLK input
LRCK input
sclkl
t
dss
t
MSB
MSB-1
sclkh
t
t
sclkw
SDOUT
Figure 18. Master Mode, I
2
S SAI
Figure 19. Slave Mode, I
2
S SAI
OVFL
t setup
LRCK
t hold
Figure 20. OVFL Output Timing
CS5351
20
DS565PP2
S D A T A
2 3 2 2
7
6
2 3 2 2
SC L K
L R C K
2 3 2 2
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
9
9
L e ft C h a n n e l
R ig h t C h a n n e l
Figure 21. Left-Justified Serial Audio Interface
SD A T A
2 3 2 2
8
7
2 3 2 2
S C L K
L R C K
2 3 2 2
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
9
9
L e ft C h a n n e l
R ig h t C h a n n e l
Figure 22. I
2
S Serial Audio Interface
LRCK
OVFL
SCLK
OVFL_R
OVFL_L
OVFL_R
Figure 23. OVFL Output Timing, I
2
S Format
LRCK
OVFL
SCLK
OVFL_R
OVFL_L
OVFL_R
Figure 24. OVFL Output Timing, Left-Justified Format
CS5351
DS565PP2
21
5
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
CS5351
22
DS565PP2
6 PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.598
0.614
15.20
15.60
E
0.291
0.299
7.40
7.60
e
0.040
0.060
1.02
1.52
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
0
8
0
8
24L SOIC (300 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
1
e
CS5351
DS565PP2
23
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.043
--
--
1.10
A1
0.002
0.004
0.006
0.05
--
0.15
A2
0.03346
0.0354
0.037
0.85
0.90
0.95
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.303
0.307
0.311
7.70
7.80
7.90
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
0.026 BSC
--
--
0.65 BSC
--
L
0.020
0.024
0.028
0.50
0.60
0.70
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters.
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
CS5351
24
DS565PP2
7 ADDENDUM
The CS5351 and CS5361 family of analog-to-digi-
tal converters are functionally compatible and can
easily be interchanged with minimal modifications
to the input buffer circuitry.
Figure 25 shows an analog input buffer that pro-
vides anti-alias filtering, proper dc biasing, and op-
timum source impedance for the modulators. The
input buffer shown will work well with both the
CS5351 and the CS5361, merely by changing the
bill of materials.
In order to use this buffer design with the CS5351,
one would stuff the 0ohm resistors R19 and R22
and not populate R3 and R20. This will create a sin-
gle-ended input buffer (as shown in Figure 3) with
the unused differential input pin connected to the
quiescent voltage of the converter (VQ). Note that
in this configuration, it is unnecessary to have the
second op-amp and related components.
In order to use this buffer design with the CS5361,
one would stuff the 0ohm resistors R3 and R20 and
not populate R19 and R22. This will create a fully
differential analog input buffer.
Figure 25. CS5351/CS5361 Analog Input Buffer
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