Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CDB61318
E1 Long Haul Line Interface Unit
Features
l
Socketed CS61318 Line Interface
l
All Required Components for CS61318
Evaluation
l
LED Status Indications for Alarm
Conditions and Operating Status
l
Support for Hardware and Host Modes
Description
The evaluation board includes a socketed CS61318 line
interface device and all support components necessary
for evaluation. The board is powered by an external
+5 Volt supply.
The board may be configured for 75
coax E1 or 120
twisted-pair E1 operations. Binding posts and bantam
jacks are provided for the line interface connections.
Several BNC connectors provide clock and data I/O at
the system interface. Reference timing may be derived
from a quartz crystal or an external reference clock. Four
LED indicators monitor device alarm conditions and op-
erating status.
ORDERING INFORMATION
CDB61318
I
TTIP
RTIP
5V+
0V
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
Hardware Control
and Mode Circuit
LED Status
Indicators
Serial Interface
Control Circuit
CS61318
XTL
MCLK
XTALOUT
XTALIN
+5V
4.7 k
TRING
RRING
(optional)
OCT `99
DS441DB1
CDB61318
2 DS441DB1
TABLE OF CONTENTS
1. POWER SUPPLY ..................................................................................................................... 3
2. BOARD CONFIGURATION ...................................................................................................... 3
2.1 Hardware Mode ................................................................................................................. 3
2.1.1 Network Loopback ................................................................................................ 3
2.2 Hardware-Coder Mode ...................................................................................................... 3
2.3 Host Mode ......................................................................................................................... 3
3. TRANSMIT CIRCUIT ................................................................................................................ 3
4. RECEIVE CIRCUIT ................................................................................................................... 4
5. REFERENCE CLOCK .............................................................................................................. 4
5.1 Quartz Crystal .................................................................................................................... 4
5.2 External Reference ............................................................................................................ 4
5.3 LED Indicators ................................................................................................................... 4
6. BUFFERING ............................................................................................................................. 4
7. TRANSFORMER SELECTION ................................................................................................. 4
8. PROTOTYPING AREA ............................................................................................................. 5
9. EVALUATION HINTS ............................................................................................................... 5
10. CDB61318 SOFTWARE ......................................................................................................... 6
10.1 Configure PC ................................................................................................................... 6
10.2 Configure Part .................................................................................................................. 6
10.3 Control Register Configuration ......................................................................................... 6
10.4 Transmitter Ram Configuration ........................................................................................ 6
10.5 Modify Unit Interval .......................................................................................................... 7
LIST OF FIGURES
Figure 1. Register Configuration Window........................................................................................ 7
Figure 2. Transmitter RAM Configuration Window.......................................................................... 8
Figure 3. Modify Unit Interval Window............................................................................................. 9
Figure 4. CDB61318Evaluation Board Schematic ........................................................................ 10
Figure 5. Board Layout - Top Layer .............................................................................................. 11
Figure 6. Board Layout - Bottom Layer ......................................................................................... 12
Figure 7. Evaluation Board Silkscreen .......................................................................................... 13
LIST OF TABLES
Table 1. LATN Settings ................................................................................................................... 4
Table 2. Transformer and Resistor Options .................................................................................... 5
Table 3. Jumper Selections............................................................................................................. 5
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
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marks and service marks can be found at http://www.cirrus.com.
CDB61318
DS441DB1
3
1. POWER SUPPLY
As shown on the evaluation board schematic in
Figure 1, power is supplied to the board from an ex-
ternal +5 Volt supply connected to the two binding
posts labeled V+ and GND. Zener diode Z1 pro-
tects the components on the board from reversed
supply connections and over-voltage damage. Ca-
pacitor C1 provides power supply decoupling and
ferrite bead L1 helps isolate the CS61318 and buff-
er supplies. The 0.1
F capacitors decouple their
respective ICs. Ferrite bead L7 helps isolates the
devices U2, U3 and U4.
2. BOARD CONFIGURATION
Slide switch S1 selects hardware, host or hardware-
coder mode operation by sliding it into HW, SW or
HWCDR positions, respectively.
2.1
Hardware Mode
In Hardware mode operation, the evaluation board
is configured using the DIP switch SW1. In this
mode, the switch establishes the digital control in-
puts for both line interface channels. Closing a DIP
switch away from the label sets the CS61318 con-
trol pin of the same name to a logic 1. The host pro-
cessor interface J1 should not be used in the
Hardware mode.
The CDB61318 switches and functions are listed
below:
TAOS: transmit all ones;
LLOOP: local loopback;
RLOOP: remote loopback;
JASEL: jitter attenuator path selection;
All switch inputs are pulled-high using resistor R13
when the switch is closed.
2.1.1
Network Loopback
NLOOP is enabled in the hardware mode by short-
ing HDR11 (HW_NLOOP) and then pressing S2. It
can also be done by closing the switches RLOOP,
LLOOP and TAOS on SW1, pulling them high,
and then pulling them back to low by opening the
RLOOP, LLOOP and TAOS switches. NLOOP
can then be turned on by sending the 1:4 pattern to
the receive input RTIP and RRING for five sec-
onds. The NLOOP LED will light up at this point if
HDR6 is jumped to NLOOP_LED position.
NLOOP can be turned off by sending a 1:2 pattern
to RTIP and RRING for five seconds.
2.2
Hardware-Coder Mode
This mode is essentially the same as the Hardware
mode with the HDB3 encoder/decoder enabled.
2.3
Host Mode
In Host mode operation, the evaluation board sup-
ports serial-port operation over interface port J1 us-
ing the printer port of a host PC running the enclosed
software. The evaluation board is connected to the
host PC using a standard DB-25 male-to-female ca-
ble (included). Ferrite beads L2-L6 help reduce in-
coming noise from the host interface. The SW1
switch must be open to enable serial port operation.
An external microprocessor may also interface to
the serial port of the CS61318 through HDR12.
HDR6 must be jumpered so the interrupt pin, INT,
Comes out to HDR12.
3. TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on
BNC inputs labeled TCLK, TPOS, and TNEG. In
Hardware and Host mode (with coder mode dis-
abled), data is supplied on the TPOS and TNEG
BNC inputs. In Host mode with coder mode en-
abled, data is supplied on the TDATA BNC input.
The transmitter output is transformer coupled to the
line through the step-up transformer T2. The signal
is available at either the Transmit binding posts
(J11, J13) or the Transmit bantam jack. Capacitor
C12 prevents output stage imbalances from pro-
ducing a DC current that may saturate the trans-
former, thus degrading its performance.
CDB61318
4
DS441DB1
4. RECEIVE CIRCUIT
The receive signal is input at either the Receive
binding posts (J4, J10) or the Receive bantam jack.
The receive signal is transformer coupled to the
CS61318 through the transformer T1.
The receive line is terminated by resistors R1-R2 to
provide impedance matching and receiver return
loss. They are socketed so the values may be
changed according to the application. The evalua-
tion board is supplied from the factory with 60
resistors for terminating 120
twisted-pair lines,
and 37.5
resistors
for terminating 75
coaxial
cables. Capacitor C3 provides an AC ground refer-
ence for the differential input.
The recovered clock and data signals are available
on BNC outputs labeled RCLK, RPOS, and RNEG.
In Hardware and Host mode (with coder mode dis-
abled), data is available on the RPOS and RNEG
BNC. With coder mode enabled, data is available
on the RDATA BNC output in unipolar format and
bipolar violations are reported on the RNEG BNC
connector.
5. REFERENCE CLOCK
The CDB61318 requires an E1 reference clock for
operation. This clock can be supplied by either a
quartz crystal or an external reference. The evalua-
tion board is supplied from the factory with a
quartz crystal. In the case that both the external ref-
erence and the quartz crystal are applied, the exter-
nal reference takes precedence.
5.1
Quartz Crystal
A quartz crystal may be inserted at socket Y1. The
quartz crystals operate at 4X the frequency of oper-
ation: 8.192 MHz.
5.2
External Reference
An external reference of 2.048 MHz may be provid-
ed at the REFCLK BNC input. Header HDR7 must
be jumpered in the "MCLK" position to provide con-
nectivity to the MCLK pin of the CS61318.
5.3
LED Indicators
The four-LED pack D1 indicates signal states on
LATN1, LATN2, LOS and NLOOP. The LOS
LED indicator illuminates when the line interface
receiver has detected a loss of signal. The NLOOP
LED indicates if Network Loopback is in opera-
tion. The LATN1/LATN2 LED's indicate the at-
tenuation level of the received signal; reading how
much the incoming signal is below the nominal ex-
pected signal level. See Table 1 for details.
6. BUFFERING
Buffer U2 provides additional drive capability for
the SW1 and Host mode connections. The buffer
outputs are filtered with an (optional) RC network
(not initially populated) to reduce the transients
caused by buffer switching.
7. TRANSFORMER SELECTION
The evaluation board is supplied from the factory
with PE-64936 (1:1), PE-65351 (1:2) and T-1229
(1:1.58) transformers by Pulse Engineering. The
socket T1 on the board is for receive side trans-
former and T2 is for the transmit side. Please see
Table 2 for details on transformers selection.
LATN1
LATN2
Attenuation Level (dB)
ON
ON
0
OFF
OFF
9.5
ON
OFF
19.5
OFF
ON
28.5
Table 1. LATN Settings
CDB61318
DS441DB1
5
8. PROTOTYPING AREA
An ample prototyping area with power supply and
ground connections is provided on the evaluation
board. This area can be used to develop and test a
variety of additional circuits such as framer devic-
es, system synchronizer PLLs, or specialized inter-
face logic.
9. EVALUATION HINTS
1) The orientation of pin 1 for the CS61318 is
marked by a small circle on the top-left side of
the socket U1.
2) Component locations R1-R2, R3-R4, Y1, T1
and T2 must have the correct values installed
according to the application. All the necessary
components are included with the evaluation
board.
3) Closing a DIP switch on SW1 away from the
label sets the CS61318 control pin of the same
name to logic 1.
4) When performing a manual loopback of the re-
covered signal to the transmit signal at the BNC
connectors, the recovered data must be valid on
the falling edge of RCLK to properly latch the
data in the transmit direction.
5) Jumpers can be placed on header HDR4 to pro-
vide a ground reference on TRING for 75
coax E1 applications.
Properly terminate TTIP/TRING when evaluating
the transmit output pulse shape. For more informa-
tion concerning pulse shape evaluation, refer to the
Crystal application note entitled "Measurement and
Evaluation of Pulse Shapes in T1/E1 Transmission
Systems."
Mode
TX Transformer
RX Transformer
R1-R2
R3-R4
E1 (120
)/LH
1:2
1:1
60
15
E1 (75
)/SH
1:1.58
1:1
37.5
15
Table 2. Transformer and Resistor Options
SH=Short Haul; LH = Long Haul;
* Default setting from the factory
Jumper
Position
Junction Selected
HDR4
IN
Grounds TRING on the line side of the transmit transformer
HDR5
IN
Grounds the line side of RRING through C2
HDR6
INT
Host Mode operation, connects INT pin to the serial interface
NLOOP_LED Hardware Mode operation, connects NLOOP pin to the LED
HDR7
GND
Grounds the MCLK pin
MCLK
Connects the MCLK pin to the BNC
HDR8
IN
Pulls the TNEG pin high, for selecting the coder mode (TCLK has to be present for
selecting the coder mode)
HDR9
XTAL-HI
Pulls the pin XTALIN high
XTAL-GND
Pulls the pin XTALIN to ground
HDR10
X
Don't care (shorted)
HDR11
OUT
Allows S2 to pull RLOOP and LLOOP high for RESET in hardware mode
IN
Allows S2 to pull RLOOP, LLOOP, and TAOS high for enabling NLOOP in hardware mode
HDR12
X
Provides access to the serial port signals
Table 3. Jumper Selections
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