CL-PS6700

Preliminary Data Book

November 1997

Version 1.0

I R R U S

O G I C

O N F I D E N T I A L

, N D A R

E Q U I R E D

Low-Power PC Card

Controller for the CL-PS7111

OVERVIEW

FEATURES

Direct interface to CL-PS7111 low-power
microcontroller

-- Custom multiplexed address/data bus for low pin count
-- Supports 13- and 18-MHz operating frequencies

Fully compatible with PC Card (PCMCIA) Release
2.01 specification

One or two CL-PS6700s per system

Low power states

-- Operating (25 mW, typical)
-- Idle
-- Standby (virtually zero power drain)

Support for PC Card hot insertion and removal

Read and write buffers

Support for 3.3- and 5-V PC Cards

Endian conversion

Supports the following PC Cards:

-- Memory-only card; flash, EPROM, or SRAM
-- I/O card; modem and communications
-- Cards configured as both I/O and memory
-- DMA-capable cards (through software emulation)

100-pin VQFP package

The CL-PS6700 connects directly to a PC Card
(PCMCIA) Release 2.01 socket and has a custom
interface to the CL-PS7111 microcontroller. The
CL-PS7111 can support up to two CL-PS6700
devices, which allows up to two PC Card sockets per
system. Addresses and data are passed to the
CL-PS6700 through 16 bits of the 32-bit Data bus
(D[15:0]).

The PC Card socket is effectively isolated by the
CL-PS6700. Except for power and ground pins, the
pins on the socket only connect to the rest of the
system through the CL-PS6700.

CL-PS7111-to-CL-PS6700 Interface

PCM_WP

PCM_CE[2:1]

PCM_OE_L

PCM_WE_L

PCM_REG_L

PCTL[2:0]

PCM_RESET

PCM_D[15:0]

PCM_A[25:0]

PCM_IOWR_L

PC CARD

PCM_BVD[2:1]

PCM_RDY

PCM_WAIT

PCM_CD[2:1]

PCM_VS[2:1]

5 V

PCM_IORD_L

SOCKET

SYS_RES_L

PCLK

PCE_L

PRDY

MD[15:0]

PIRQ_L[1:0]

I/O PO

WER =

V5V_O

I/O PO

WER =

V3V_O

PTYPE

POWER

PSLEEP_L

CL-PS7111

3 V

EXPCLK

NCS[4]

PB[0]

NEINTN

D[15:0]

WRITE

GPIO

RESET_L

CL-

PS6700

MODULE

(cont.)

PRELIMINARY DATA BOOK v1.0

November 1997

OVERVIEW

I R R U S

O G I C

O N F I D E N T I A L

, N D A R

E Q U I R E D

CL-PS6700

Low-Power PC Card Controller

CL-PS7111-to-CL-PS6700 Interface

The PC Card interface requires a 26-bit address bus
and a 16-bit data bus. The interface between the
CL-PS6700 and CL-PS7111 consists of a 16-bit bus
that carries the address and data information, and
several control signals. This bus defines a two-clock
address phase during which the 26-bit PC Card
address and 6 control bits are transferred, and a
one- or two-clock data phase during which one or
four bytes of data are transferred. The data phase
for reads can be deferred (for example, for a DMA
access to the frame buffer of the CL-PS7111).

If a write transfer is indicated, write data appears in
the third clock phase. If a word write is indicated,
write data also appears in the fourth clock phase.
For read transfers, the CL-PS6700 drives the bus
with read data during the first one or two clocks of
the data phase. This interface bus is also shared by
other memory devices and up to one additional
CL-PS6700 device.

The CL-PS7111 accesses the CL-PS6700 as a
memory-mapped peripheral on the 16-bit memory
bus. A Chip Enable signal (NCS[4]) from the
CL-PS7111 selects one CL-PS6700 device for
access to a particular PC Card socket. Another Chip
Enable signal (NCS[5]) connects a second PC Card
socket.

The CL-PS6700 implements the low-level interface
to the PC Card socket and provides voltage transla-
tion for mixed-voltage systems. The CL-PS6700
also provides the data buffer and interrupt controls
for the PC Card. Transfers between the two devices
can be either one or four bytes.

The CL-PS6700 can be programmed to assem-
ble/disassemble CL-PS7111 transfers to the width
of the PC Card. The CL-PS6700 has read and write
buffers that allow posting of both reads and writes.
The read queue is single entry; the write FIFO can
queue up to four CL-PS7111 transactions (up to
16 bytes).

Hot Insertion Support

The CL-PS6700 PC Card controller allows PC
Cards to be inserted or removed while system
power is on. The CL-PS7111 controller typically
applies power to a PC Card socket after it has
detected a properly inserted card. The device
removes the power before the card is removed
(that is, when the CPU detects that the card lock is
deasserted). Since each card is isolated from the
system by the associated CL-PS6700, insertion
and removal of cards do not cause interference on
the system buses.

Card Configuration and Access

After power-on or reset, a PC Card defaults to a
memory-only card. The CL-PS7111 then reads the
CIS of the card to determine the card type, access
time, and so on, and configures the CL-PS6700 to
access the card.

Each PC Card's V

and V

pins are individually

controlled by its associated CL-PS6700. The
CL-PS7111 controls the power to a card by writing
to the CL-PS6700 registers. The CL-PS6700
ensures that its signals to the sockets are in the
proper state before applying or removing power.

The CL-PS6700 device is available in an 100-pin
VQFP package. The device can be used with both
operating frequencies of the CL-PS7111 (13 and
18 MHz at 2.7 and 3.3 V).

OVERVIEW

(cont.)

November 1997

PRELIMINARY DATA BOOK v1.0

TABLE OF CONTENTS

I R R U S

O G I C

O N F I D E N T I A L

, N D A R

E Q U I R E D

CL-PS6700

Low-Power PC Card Controller

CONVENTIONS ......................................................................................... 5

1. PIN INFORMATION.................................................................................... 7

1.1 100-Pin VQFP Pin Diagram ....................................................................................... 7
1.2 Pin Listings................................................................................................................. 8

2. PIN DESCRIPTIONS................................................................................ 10

2.1 CL-PS7111-to-CL-PS6700 Interface Signals........................................................... 10

2.1.1

Address/Data Bus Signals ............................................................................ 10

2.1.2

Access Control Signals................................................................................. 12

2.1.3

Interrupt and Abort Signals........................................................................... 13

2.1.4

Clock, Reset, and Sleep Signals .................................................................. 13

2.2 PC Card Interface Signals........................................................................................ 14

2.2.1

Address and Data Signals ............................................................................ 14

2.2.2

Access Control Signals................................................................................. 14

2.2.3

Additional Control for I/O Signals.................................................................. 16

2.2.4

Card Detect and Battery Status Signals ....................................................... 16

2.2.5

Card Voltages and Reset Signals ................................................................. 17

2.3 Power and Ground Pins ........................................................................................... 17

3. FUNCTIONAL DESCRIPTION................................................................. 18

3.1 PC Card (PCMCIA) Interface ................................................................................... 18

3.1.1

PC Card Types.............................................................................................. 18

3.1.2

PC Card Address/Data Bus .......................................................................... 18

3.1.3

PC Card Address Spaces and DMA............................................................. 18

3.1.4

Byte Assembly/Disassembly and Queueing ................................................. 19

3.1.5

Card Configuration........................................................................................ 19

3.1.6

Hot Insertion Support ................................................................................... 19

3.2 Power States ............................................................................................................ 20

3.2.1

Active State................................................................................................... 20

3.2.2

Idle State....................................................................................................... 20

3.2.3

Standby State ............................................................................................... 20

4. REGISTERS ............................................................................................. 21

4.1 Register Addresses.................................................................................................. 21
4.2 Interrupt Structure .................................................................................................... 23
4.3 Power Management Registers ................................................................................. 24

4.3.1

Power Management Register (0X0C002800) ............................................... 24

4.3.2

Card Power Control Register (0X0C002C00) ............................................... 25

4.4 System Interface Registers ...................................................................................... 26

4.4.1

System Interface Configuration Register (0X0C002000).............................. 26

4.4.2

DMA Control Register (0X0C004000) .......................................................... 27

4.4.3

Device Information Register (0X0C004400) ................................................. 27

4.5 Card Interface Registers .......................................................................................... 28

4.5.1

Card Interface Configuration Register (0X0C002400) .................................. 28

4.5.2

Card Interface Timing Register 0A (0X0C003000) ....................................... 29

4.5.3

Card Interface Timing Register 0B (0X0C003400) ....................................... 29

4.5.4

Card Interface Timing Register 1A (0X0C003800) ....................................... 30

4.5.5

Card Interface Timing Register 1B (0X0C003C00)....................................... 30

TABLE OF CONTENTS

PRELIMINARY DATA BOOK v1.0

November 1997

TABLE OF CONTENTS

I R R U S

O G I C

O N F I D E N T I A L

, N D A R

E Q U I R E D

CL-PS6700

Low-Power PC Card Controller

4.6 I/O Properties........................................................................................................... 31

5. ELECTRICAL SPECIFICATIONS ............................................................ 33

5.1 Bus Timing -- System Bus ...................................................................................... 35
5.2 Bus Operations ........................................................................................................ 38

6. PACKAGE SPECIFICATIONS ................................................................. 43

7. ORDERING INFORMATION .................................................................... 44

BIT INDEX................................................................................................ 45

INDEX....................................................................................................... 46

Электронный компонент: CL-PS6700

Document Outline