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Электронный компонент: CS3310

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Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
Products from
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS3310
Stereo Digital Volume Control
Features
l
Complete Digital Volume Control
-- 2 Independent Channels
-- Serial Control
-- 0.5 dB Step Size
l
Wide Adjustable Range
-- -95.5 dB Attenuation
-- +31.5 dB Gain
l
Low Distortion & Noise
-- 0.001% THD+N
-- 116 dB Dynamic Range
l
Noise Free Level Transitions
l
Channel-to-Channel Crosstalk Better Than
110 dB
Description
The CS3310 is a complete stereo digital volume control
designed specifically for audio systems. It features a 16-
bit serial interface that controls two independent, low dis-
tortion audio channels.
The CS3310 includes an array of well-matched resistors
and a low noise active output stage that is capable of
driving a 600
load. A total adjustable range of 127 dB,
in 0.5 dB steps, is achieved through 95.5 dB of attenua-
tion and 31.5 dB of gain.
The simple 3-wire interface provides daisy-chaining of
multiple CS3310's for multi-channel audio systems.
The device operates from 5 V supplies and has an in-
put/output voltage range of 3.75 V.
ORDERING INFORMATION
CS3310-KP
0 to 70 C
16-pin Plastic DIP
CS3310-KS
0 to 70 C
16-pin Plastic SOIC
I
AINL
AGNDL
MUX
AINR
AGNDR
MUX
16
15
10
9
8
8
+
-
+
-
Control
Register
Serial to
Parallel
Register
16
8
8
AOUTL
14
MUTE
8
1
2
ZCEN
CS
3
SDATAI
7
SDATAO
6
SCLK
AOUTR
11
DGND
5
VD+
4
VA-
13
VA+
12
FEB `99
DS82PP3
CS3310
2
DS82PP3
ANALOG CHARACTERISTICS
(T
A
= 25 C, VA+, VD+ = 5 V 5%; VA- = -5V 5%; Rs = 0; R
L
=
2 k
; C
L
= 20 pF; 10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified)
Notes: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings >1.
2. This parameter is guaranteed by design and/or characterization.
Parameter
Symbol Min
Typ
Max
Unit
DC Characteristics
Step Size
-
0.5
-
dB
Gain Error (31.5 dB Gain)
-
0.05
-
dB
Gain Matching Between Channels
-
0.05
-
dB
Input Resistance
R
IN
8
10
-
k
Input Capacitance
C
IN
-
10
-
pF
AC Characteristics
Total Harmonic Distortion plus Noise (V in = 2V rms, 1 kHz)
THD+N
-
0.001
.0025
%
Dynamic Range
110
116
-
dB
Input/Output Voltage Range
(VA-)+1.25
-
(VA+)-1.25
V
Output Noise
(Note 1)
-
4.2
8.4
Vrms
Digital Feedthrough (Peak Component)
(Note 2)
-80
-
-
dB
Interchannel Isolation (1 kHz)
(Note 2)
-100
-110
-
dB
Output Buffer
Offset Voltage
(Note 1)
V
OS
-
0.25
0.75
mV
Load Capacitance
-
-
100
pF
Short Circuit Current
-
20
-
mA
Unity Gain Bandwidth, Small Signal
(Note 2)
2
-
-
MHz
Power Supplies
Supply Current (No Load, AIN = 0 V)
IA+
IA-
ID+
-
-
-
5.0
5.0
350
8.0
8.0
800
mA
mA
A
Power Consumption
P
D
-
52.0
84.0
mW
Power Supply Rejection Ratio (250 Hz)
PSRR
-
80
-
dB
CS3310
DS82PP3
3
DIGITAL CHARACTERISTICS
(T
A
= 25 C, VA+ , VD+ = 5V 5%, VA- = -5V 5% )
SWITCHING CHARACTERISTICS
(T
A
= 25 C; VA+, VD+ = +5V 5%; VA- = -5V 5%; C
L
= 20 pF)
Parameter
Symbol Min
Typ
Max
Unit
High-Level Input Voltage
V
IH
2.0
-
VD+0.3
V
Low-Level Input Voltage
V
IL
-0.3
-
+0.8
V
High-Level Output Voltage
(I
O
= 200
A)
V
OH
VD-1.0
-
-
V
Low-Level Output Voltage
(I
O
= 3.2mA)
V
OL
-
-
0.4
V
Input Leakage Current
I
in
-
1.0
10
A
Parameter
Symbol Min
Typ
Max
Unit
Serial Clock
SCLK
0
-
-
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t
ph
t
pl
80
80
-
-
-
-
ns
ns
MUTE Pulse
Width
Low
-
2.0
-
-
ms
Input Timing
SDATAI Set Up Time
t
SDVS
20
-
-
ns
SDATAI Hold Time
t
SDH
20
-
-
ns
CS Valid to SCLK Rising
t
CSVS
30
-
-
ns
SCLK Falling to CS High
t
LTH
35
-
-
ns
Output Timing
CS Low to Output Active
t
CSH
-
-
35
ns
SCLK Falling to Data Valid
t
SSD
-
-
60
ns
CS High to SDATAO Inactive
t
CSDH
-
-
100
ns
t CSVS
t SDVS
tSDH
SCLK
SDATAI
CS
SDATAO
t CSH
tCSDH
t SSD
MSB
tLTH
Figure 1. Serial Port Timing Diagram
CS3310
4
DS82PP3
RECOMMENDED OPERATING CONDITIONS
(DGND = 0V; all voltages with respect to ground)
Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the
recommended power connections.
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
Symbol Min
Typ
Max
Unit
DC Power Supplies:
Positive Digital
Positive Analog
Negative Analog
(VD+) - (VA+) (Note 3)
VD+
VA+
VA
-
4.75
4.75
-4.75
-0.3
5.0
5.0
-5.0
-
VA+
5.25
-5.25
0.0
V
V
V
V
Ambient Operating Temperature
T
A
0
25
70
C
Parameter
Symbol Min
Max
Unit
DC Power Supplies:
Positive Digital
Positive Analog
Negative Analog
VD+
VA+
VA-
-0.3
-0.3
0.3
(VA+)+ 0.3
6.0
-6.0
V
V
V
Input Current, Any Pin Except Supply
I
in
-
10
mA
Digital Input Voltage
V
IND
-0.3
(VA+) + 0.3
V
Ambient Operating Temperature (power applied)
T
A
-55
+125
C
Storage Temperature
T
STG
-65
+150
C
CS3310
DS82PP3
5
CS3310
AINL
AINR
AGNDL
AGNDR
VD+
VA+
VA-
SDATAO
CS
SDATAI
TO ANOTHER
CS3310 OR
CONTROLLER
CONTROLLER
SCLK
AUDIO
SOURCE
AOUTL
AOUTR
7
10
11
12
13
14
15
+
+
+5V ANALOG
-5V ANALOG
2
3
6
16
9
DGND
5
AUDIO
OUTPUTS
4
ZCEN
0.1
F
10
F
+
10
1
MUTE
8
0.1
F
10
F
0.1
F
0.1
F
10
F
47 k
Figure 2. Recommended Connection Diagram
*Required to terminate SDATAI due to high impedance
state of SDATAO when CS is high.
**Refer to Note 3.
*
**
CS3310
6
DS82PP3
GENERAL DESCRIPTION
The CS3310 is a stereo, digital volume control de-
signed for audio systems. The levels of the left and
right analog input channels are set by a 16-bit serial
data word; the first 8 bits address the right channel
and the remaining 8 bits address the left channel, as
detailed in Table 1. Resistor values are decoded to
0.5 dB resolution by an internal multiplexer for a
total attenuation range of -95.5 dB. An output am-
plifier stage provides a programmable gain of up to
31.5 dB in 0.5 dB steps. This results in an overall 8-
bit adjustable range of 127 dB.
The CS3310 operates from
5 V supplies and ac-
cepts inputs up to
3.75 V. Once in operation, the
CS3310 can be brought to a muted state with the
mute pin, MUTE, or by writing all zeros to the vol-
ume control registers. The device contains a simple
three wire serial interface which accepts 16-bit da-
ta. This interface also supports daisy-chaining ca-
pability.
SYSTEM DESIGN
Very few external components are required to sup-
port the CS3310. Normal power supply decoupling
components are all that is required, as shown in
Figure 2.
Serial Data Interface
The CS3310 has a simple, three wire interface that
consists of three input pins: SDATAI, serial data
input; SCLK, serial data clock and CS, the chip se-
lect input. SDATAO, serial data output, enables the
user to read the current volume setting or provide
daisy-chaining of multiple CS3310's.
The 16-bit serial data is formatted MSB first and
clocked into SDATAI by the rising edge of SCLK
with CS low as shown in Figure 3. The data is
latched by the rising edge of CS and the analog out-
put levels of both left and right channels are set.
The existing data in the volume control data regis-
ter is clocked out SDATAO on the falling edge of
SCLK. This data can be used to read current
gain/attenuation levels or to daisy chain multiple
CS3310's. See Figure 1 for proper setup and hold
times for CS, SDATAI, SCLK, and SDATAO.
SCLK and SDATAI should be active only during
volume setting operations to achieve optimum dy-
namic range.
Daisy Chaining
Digitally controlled, multi-channel audio systems
often result in complex address decoding which
complicates PCB layout. This is greatly simplified
with the daisy-chaining capability of the CS3310.
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
CS
SCLK
SDATAI
SDATAO
L0 = Left Channel Least Significant Bit R0 = Right Channel Least Significant Bit
L7 = Left Channel Most Significant Bit R7 = Right Channel Most Significant Bit
SDATAI is latched internally on the rising edge of SCLK
SDATAO transitions after the falling edge of SCLK
SDATAO bits reflect the data previously loaded into the CS3310
Figure 3. Serial Port Timing
CS3310
DS82PP3
7
In single device operation, volume control data is
loaded into the 16-bit shift register by holding the
CS pin low for sixteen SCLK pulses and then
latched on the rising edge of CS. The previous con-
tents of the shift-register are shifted through the
register and out SDATAO during the process.
Multi-channel operation can be implemented as
shown in Figure 4 by connecting the SDATAO of
device #1 to the SDATAI pin of device #2. In this
manner multiple CS3310s can be loaded from a
single serial data line without complex addressing
schemes. Volume control data is loaded by holding
CS low for 16 x N SCLK pulses, where N is the
number of devices in the chain. The 16 bits clocked
into device #1 on SCLK pulses 1-16 are clocked
into device #2 on SCLK pulses 17-32. The
CS3310s are simultaneously updated on the rising
edge of CS following 16 x N SCLK pulses. Notice
that a 47 kohm resistor is required to terminate
SDATAI, as shown in Figure 4, due to the high im-
pedance state of SDATAO when CS is high.
Changing the Analog Output Level
Care has been taken to ensure that there are no au-
dible artifacts in the analog output signal during
volume control changes. The gain/attenuation
changes of the CS3310 occur at zero crossings to
eliminate glitches during level transitions. The zero
crossing for the left channel is the voltage potential
at the AGNDL pin; the voltage potential at the
AGNDR pin defines the right channel zero cross-
ing.
A volume control change occurs after chip select
latches the data in the volume control data register
and two zero crossings are detected. If two zero
crossings are not detected within 18 ms of the
change in CS, the new volume setting is imple-
mented. The zero crossing enable pin, ZCEN, en-
ables or disables the zero crossing detection
function as well as the 18 ms time-out circuit.
Analog Inputs and Outputs
The maximum input level is limited by the com-
mon-mode voltage capabilities of the internal op-
amp. Signals approaching the analog supply volt-
ages may be applied to the AIN pins if the internal
attenuator limits the output signal to within 1.25
volts of the analog supply rails.
The outputs are capable of driving 600
loads to
within 1.25 volts of the analog supply rails and are
short circuit protected to 20 mA.
As with any adjustable gain stage the affects of a
DC offset at the input must be considered. Capaci-
tively coupling the analog inputs may be required
AUDIO
SIGNAL
16
9
AINL
AINR
SDATAI
SDATAO
AOUTL
AOUTR
CS
SCLK
CS3310
CONTROLLER
14
11
2
6
3
7
AUDIO
SIGNAL
16
9
AINL
AINR
SDATAI
SDATAO
AOUTL
AOUTR
CS
SCLK
CS3310
14
11
2
6
3
7
47 k
#1
#2
Figure 4. Daisy Chaining Diagram
Input Code
(Left or Right Channel)
Gain or Attenuation (dB)
11111111
11111110

11000000
00000010
00000001
00000000
+31.5
+31.0

0
-95.0
-95.5
Software Mute
Table 1. Input Code Definition
CS3310
8
DS82PP3
to prevent "clicks and pops" which occur with gain
changes if an appreciable offset is present.
Source Impedance Requirements
The CS3310 requires a low source impedance to
achieve maximum performance. The ESD protec-
tion diodes on the analog input pins are reversed bi-
ased during normal operation. A characteristic of a
reversed biased diode is a non-linear voltage de-
pendent capacitance which can be a source of dis-
tortion if the source impedance becomes
appreciable relative to the reversed biased diode
capacitance. Source impedances equal to or less
than 600 ohms will avoid this distortion mecha-
nism for the CS3310.
Mute
Muting can be achieved by either hardware or soft-
ware control. Hardware muting is accomplished
via the MUTE input and software muting by load-
ing all zeroes into the volume control register.
MUTE disconnects the internal buffer amplifiers
from the output pins and terminates AOUTL and
AOUTR with 10 k
resistors to ground. The mute
is activated with a zero crossing detection (inde-
pendent of the zero cross enable status) or an 18 ms
timeout to eliminate any audible "clicks" or
"pops". MUTE also initiates an internal offset cal-
ibration.
A software mute is implemented by loading all ze-
roes into the volume control register. The internal
amplifier is set to unity gain with the amplifier in-
put connected to the maximum attenuation point of
the resistive divider, AGND.
A "soft mute" can be accomplished by sequentially
ramping down from the current volume control set-
ting to the maximum attenuation code of all zeroes.
Power-Up Considerations
Upon initial application of power, the MUTE pin of
the CS3310 should be set low to initiate a power-up
sequence. This sequence sets the serial shift regis-
ter and the volume control register to zero and per-
forms an offset calibration. The device should
remain muted until the supply voltages have settled
to ensure an accurate calibration. The device also
includes an internal power-on reset circuit that re-
quires approximately 100 s to settle and will ig-
nore any attempts to address the internal registers
during this period.
The offset calibration minimizes internally gener-
ated offsets and ignores offsets applied to the AIN
pins. External clocks are not required for calibra-
tion.
Although the device is tolerant to power supply
variation, the device will enter a hardware mute
state if the power supply voltage drops below ap-
proximately
3.5 volts. A power-up sequence will
be initiated if the power supply voltage returns to
greater than
3.5 volts.
Applying power to VD+ prior to VA+ creates a
SCR latch-up condition. Refer to Figure 2 for the
recommended power connections.
PCB Layout, Grounding and Power Supply
Decoupling
As with any high performance device which con-
tains both analog and digital circuitry, careful at-
tention to power supply and grounding
arrangements must be observed to optimize perfor-
mance. Figure 2 shows the recommended power
arrangements with VA+ connected to a clean +5
volt supply and VA- connected to a clean -5 volt
supply. VD+ powers the digital interface circuitry
and should be powered from VA+, as shown in Fig-
ure 2, to avoid potentially destructive SCR latch-
up. Decoupling capacitors should be located as
near to the CS3310 as possible, see Figure 5.
The printed circuit board layout should have sepa-
rate analog and digital regions with individual
ground planes. The CS3310 should reside in the an-
alog region as shown in Figure 5. Care should be
taken to ensure that there is minimal resistance in
CS3310
DS82PP3
9
the analog ground leads to the device to prevent
any change in the defined attenuation settings. Ex-
tensive use of ground plane fill on both the analog
and digital sections of the circuit board will yield
large reductions in radiated noise effects.
Performance Plots
Figure 8 displays the CS3310 frequency response
with a 3.75 Vp output.
Figure 9 shows the frequency response with
a.375 Vp output.
Figure 6 is the Total Harmonic Distortion + Noise
vs. amplitude at 1 kHz. The upper trace is the
THD+N vs. amplitude of the CS3310 The lower
trace is the THD+N of the Audio Precision System
One generator output connected directly to the an-
alyzer input. The System One panel settings are
identical to the previous test. This indicates that the
THD+N contribution of the Audio Precision actu-
ally degrades the measured performance of the
CS3310 below 2.7 Vrms signal levels.
Figure 7 is a 16k FFT plot demonstrating the
crosstalk performance of the CS3310 at 20 kHz.
Both channels were set to unity gain. The right
channel input is grounded with the left channel
driven to 2.65 Vrms output at 20 kHz. The FFT plot
is of the right channel output. This indicates chan-
nel to channel crosstalk of -130 dB at 20 kHz.
Figure 10 is a series of plots which display the uni-
ty-gain THD+N vs. Frequency for 600
, 2 k
and
infinite load conditions. The output was set to
2 Vrms. The Audio Precision System One was
bandlimited to 22 kHz
Figure 11 is a series of plots which display the uni-
ty-gain THD+N vs. Frequency for 1, 2 and 2.8
Vrms output levels. The output load was open cir-
cuit. The Audio Precision System One was band-
limited to 22 kHz.
Digital Ground Plane
CPU & Digital
Logic
> 1/8"
Analog Signals
and Circuits
Analog Ground Plane
10
10
F
VA+
+
VA-
10
F
+
0.1
F
0.1
F
0.1
F
10
F
+
Figure 5. Recommended 2-Layer PCB Layout
CS3310
10
DS82PP3
.
0.1
1
3
1
.1
.01
.001
.0001
THD+N% vs AMPL (Vrms)
Figure 6. THD+N vs. AMP
Figure 7. 20 kHz Crosstalk
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
20.00 2.06k 4.11k 6.15k 8.19k 10.2k 12.3k 14.3k 16.4k 18.4k 20.5k 22.5k
AMPL (dBr) vs FREQ (Hz)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
10
100
1k
10k
100k 200k
AMPL (dBr) vs FREQ (Hz)
Figure 8. Frequency Response Full Scale Input
Figure 9. Frequency Response -20 dB Input
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
10
100
1k
10k
100k 200k
AMPL (dBr) vs FREQ (Hz)
0.1000
0.0100
0.0010
0.0001
20
100
1k
10k
20k
OPEN
600
2k
0.1000
0.0100
0.0010
0.0001
20
100
1k
10k
20k
2.8 VRMS
1 VRMS
2 VRMS
Figure 10. THD+N vs. Frequency LOAD = 600
, 2 k
,
open ckt
Figure 11. THD+N vs. Frequency Output levels of 1, 2,
and 2.8 Vrms
CS3310
DS82PP3
11
PIN DESCRIPTION
Power Supply Connections
VA+ - Positive Analog Power, Pin 12.
Positive analog supply. Nominally +5 volts.
VA- - Negative Analog Power, Pin 13.
Negative analog supply. Nominally -5 volts.
AGNDL - Left Channel Analog Ground, Pin 15.
Analog ground reference for the left channel.
AGNDR - Right Channel Analog Ground, Pin 10.
Analog ground reference for the right channel.
VD+ - Positive Digital Power, Pin 4.
Positive supply for the digital section. Nominally +5 volts. Applying power to VD+ prior to
VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power
connections.
DGND - Digital Ground, Pin 5.
Digital ground for the digital section.
Zero Crossing Enable
ZCEN
AINL
Left Channel Input
Chip Select
CS
AGNDL
Left Analog Ground
Serial Data Input
SDATAI
AOUTL
Left Channel Output
Positive Digital Power
VD+
VA-
Negative Analog Power
Digital Ground
DGND
VA+
Positive Analog Power
Serial Clock Input
SCLK
AOUTR
Right Channel Output
Serial Data Output
SDATAO
AGNDR
Right Analog Ground
Mute
MUTE
AINR
Right Channel Input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS3310
12
DS82PP3
Analog Inputs and Outputs
AINL, AINR - Left and Right Channel Analog Inputs, Pins 16, 9.
Analog input connections for the left and right channels. Nominally 3.75 volts for a full scale
input.
AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11.
Analog outputs for the left and right channels. Nominally 3.75 volts for a full scale output.
Digital Pins
SDATAI - Serial Data Input, Pin 3.
Serial input data that sets the analog output level of the left and right channels. The data is
formatted in a 16-bit word. The first eight bits clocked into this pin control the analog output
level for the right channel, and the second eight bits clocked into the device control the analog
output level for the left channel. The data is clocked into the CS3310 by the rising edge of
SCLK.
SDATAO - Serial Data Output, Pin 7.
Serial output data that provides daisy-chaining of multiple CS3310's. This serial output will
output the previous sixteen bits of volume control data that were clocked into the SDATAI pin.
SDATAO will enter a High Impedance State when CS is High.
SCLK - Serial Input Clock, Pin 6.
Serial clock that clocks in the individual bits of serial data from the SDATAI pin. This clock is
also used to clock out the individual bits from the SDATAO pin. The SDATAI data is latched
on the rising edge, and SDATAO data is clocked out on the falling edge.
CS - Chip Select, Pin 2.
When high, the SDATAO output is held in a high impedance state. A falling transition defines
the start of the 16-bit volume control word into the device. The 16-bit input data is latched into
the control register on the rising edge of CS.
MUTE - Mute, Pin 8.
Forces both the left and right analog output channels to ground. An offset calibration is
initiated following the low transition of MUTE. Calibration requires a minimum mute period of
2 ms.
ZCEN - Zero Crossing Enable, Pin 1.
This pin enables or disables the zero crossing detection and time-out function used during
analog output level transitions. A high level on this pin enables the zero crossing detection
function. A low level on this pin disables the zero crossing detection.
CS3310
DS82PP3
13
PARAMETER DEFINITIONS
Dynamic Range
Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the
specified bandwidth with the input grounded. Units in decibels.
Total Harmonic Distortion plus Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components.
Expressed in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the
converter's output with the input under test grounded and a full-scale signal applied to the other
channel. Units in decibels.
CS3310
14
DS82PP3
PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A 0.000
0.210
0.00
5.33
A1
0.015
0.025
0.38
0.64
A2
0.115
0.195
2.92
4.95
b
0.014
0.022
0.36
0.56
b1
0.045
0.070
1.14
1.78
c
0.008
0.014
0.20
0.36
D
0.780
0.800
19.81
20.32
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.090
0.110
2.29
2.79
eA
0.280
0.320
7.11
8.13
eB
0.300
0.430
7.62
10.92
eC
0.000
0.060
0.00
1.52
L
0.115
0.150
2.92
3.81
0
15
0
15
16 PIN PLASTIC (PDIP) PACKAGE DRAWING
E1
D
SEATING
PLANE
b1
e
b
A
L
A1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
1
eA
c
A2
E
eC
eB
CS3310
DS82PP3
15
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A 0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.398
0.413
10.10
10.50
E
0.291
0.299
7.40
7.60
e
0.040
0.060
1.02
1.52
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
0
8
0
8
JEDEC #: MS-013
e
16L SOIC (300 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
1
Features

Demonstrates recommended layout
and grounding arrangements

On-board or externally supplied system
control

Buffered PC Control Interface

Digital and Analog Patch Areas
General Description
The CDB3310 evaluation board allows fast evaluation
of the CS3310 stereo digital volume control. The board
generates all control signals. Evaluation requires a low-
distortion signal source and a power supply.
The evaluation board may be configured to accept ex-
ternal timing signals for operation in a user application
during system development. The CDB3310 also pro-
vides a PC compatible control port for user software
development.
Analog inputs and outputs are standard RCA phono
plugs.
ORDERING INFORMATION:
CDB3310
SEPT '93
DS82DB1
15
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
Evaluation Board for CS3310
Semiconductor Corporation
CDB3310
+5V
GND
-5V
AINR
AINL
Microcontroller
PC
Control
Port
Power Supply
Conditioning
Analog
Patch
Area
Digital
Patch
Area
CS3310
AOUTR
AOUTL
CS
SDATAI
SCLK
SDATAO
Copyright
Crystal Semiconductor Corporation 1993
(All Rights Reserved)
Notes
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Cirrus
Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information
is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by
Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of
Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied,
reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Fur-
thermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic,
Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks
of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found
at http://www.cirrus.com.