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Электронный компонент: CS42426

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Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2004
(All Rights Reserved)
Cirrus Logic, Inc.
www.cirrus.com
CS42426
114 dB, 192 kHz 6-Ch Codec with PLL
Features
Six 24-bit D/A, two 24-bit A/D converters
114 dB DAC / 114 dB ADC dynamic range
-100 dB THD+N
System sampling rates up to 192 kHz
Integrated low-jitter PLL for increased system
jitter tolerance
PLL clock or OMCK system clock selection
7 configurable general purpose outputs
ADC high pass filter for DC offset calibration
Expandable ADC channels and one-line
mode support
Digital output volume control with soft ramp
Digital +/-15 dB input gain adjust for ADC
Differential analog architecture
Supports logic levels between 5 V and 1.8 V
General Description
The CS42426 CODEC provides two analog-to-digital and six
digital-to-analog Delta-Sigma converters, as well as an inte-
grated PLL, in a 64-pin LQFP package.
The CS42426 integrated PLL provides a low-jitter system
clock. The internal stereo ADC is capable of independent chan-
nel gain control for single-ended or differential analog inputs.
All six channels of DAC provide digital volume control and dif-
ferential analog outputs. The general purpose outputs may be
driven high or low, or mapped to a variety of DAC mute controls
or ADC overflow indicators.
The CS42426 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42426-CQZ
-10 to 70 C
64-pin LQFP
CS42426-DQZ
-40 to 85 C
64-pin LQFP
CDB42428
Evaluation Board
PLL
Internal Voltage
Reference
RST
GPO1
AD0/CS
SCL/CCLK
SDA/CDOUT
AD1/CDIN
VLC
AOUTA1+
AOUTA1-
AOUTB1+
AOUTA3+
AOUTA3-
AOUTA2-
AOUTB2-
AOUTA2+
AOUTB2+
AOUTB1-
AOUTB3+
AOUTB3-
AINL+
AINL-
AINR+
AINR-
FILT+
REFGND VQ
ADC#1
ADC#2
Digital Filter
Digital Filter
Gain & Clip
Gain & Clip
ADC_SDOUT
ADCIN1
ADCIN2
DAC_SCLK
DAC_LRCK
DAC_SDIN3
DAC_SDIN2
DAC_SDIN1
VLS
ADC_LRCK
DGND VD
OMCK
RMCK
LPFLT
INT
Control
Port
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
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GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
MUTEC
Mute
A
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VA AGND
ADC
Serial
Audio
Port
Mult/Div
GPO
ADC_SCLK
Lev
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JUL `04
DS604A2
CS42426
2
TABLE OF CONTENTS
1 PIN DESCRIPTIONS ................................................................................................................. 6
2 TYPICAL CONNECTION DIAGRAMS ..................................................................................... 8
3 APPLICATIONS ....................................................................................................................... 10
3.1 Overview .......................................................................................................................... 10
3.2 Analog Inputs ................................................................................................................... 10
3.2.1 Line Level Inputs ................................................................................................. 10
3.2.2 External Input Filter ............................................................................................. 11
3.2.3 High Pass Filter and DC Offset Calibration ......................................................... 11
3.3 Analog Outputs ................................................................................................................ 11
3.3.1 Line Level Outputs and Filtering ......................................................................... 11
3.3.2 Interpolation Filter ............................................................................................... 12
3.3.3 Digital Volume and Mute Control ........................................................................ 12
3.3.4 ATAPI Specification ............................................................................................ 13
3.4 Clock Generation ............................................................................................................. 14
3.4.1 PLL and Jitter Attenuation ................................................................................... 14
3.4.2 OMCK System Clock Mode ................................................................................ 15
3.4.3 Master Mode ....................................................................................................... 15
3.4.4 Slave Mode ......................................................................................................... 15
3.5 Digital Interfaces .............................................................................................................. 16
3.5.1 Serial Audio Interface Signals ............................................................................. 16
3.5.2 Serial Audio Interface Formats ............................................................................ 18
3.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................. 21
3.5.4 One Line Mode(OLM) Configurations ................................................................. 22
3.6 Control Port Description and Timing ................................................................................ 26
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiar-
ies ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor-
mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and condi-
tions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No
responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items,
or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants
no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus
owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within
your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described
in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or
quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material
is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHO-
RIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COM-
PONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICA-
TIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,
STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES
OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY
CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING
ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Purchase of I
2
C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I
2
C Patent Rights to use
those components in a standard I
2
C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to
www.cirrus.com/
3
CS42426
3.6.1 SPI Mode ............................................................................................................ 26
3.6.2 I2C Mode ............................................................................................................ 27
3.7 Interrupts ......................................................................................................................... 28
3.8 Reset and Power-up ....................................................................................................... 29
3.9 Power Supply, Grounding, and PCB layout ..................................................................... 29
4 REGISTER QUICK REFERENCE ........................................................................................... 30
5 REGISTER DESCRIPTION ..................................................................................................... 32
5.1 Memory Address Pointer (MAP) ....................................................................................... 32
5.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 32
5.3 Power Control (address 02h)............................................................................................ 33
5.4 Functional Mode (address 03h) ........................................................................................ 33
5.5 Interface Formats (address 04h) ...................................................................................... 34
5.6 Misc Control (address 05h) .............................................................................................. 36
5.7 Clock Control (address 06h) ............................................................................................. 37
5.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 39
5.9 Clock Status (address 08h) (Read Only) .......................................................................... 39
5.10 Volume Control (address 0Dh) ....................................................................................... 40
5.11 Channel Mute (address 0Eh).......................................................................................... 41
5.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ........................................ 42
5.13 Channel Invert (address 17h) ......................................................................................... 42
5.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) ............................................. 42
5.15 ADC Left Channel Gain (address 1Ch) .......................................................................... 45
5.16 ADC Right Channel Gain (address 1Dh) ........................................................................ 45
5.17 Interrupt Control (address 1Eh) ...................................................................................... 45
5.18 Interrupt Status (address 20h) (Read Only) ................................................................... 46
5.19 Interrupt Mask (address 21h) ......................................................................................... 47
5.20 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)................................................................................ 47
5.21 MuteC Pin Control (address 28h) ................................................................................... 47
5.22 General Purpose Pin Control (addresses 29h to 2Fh) ................................................... 48
6 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 50
SPECIFIED OPERATING CONDITIONS ............................................................................... 50
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 50
ANALOG INPUT CHARACTERISTICS .................................................................................. 51
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................... 52
ANALOG OUTPUT CHARACTERISTICS .............................................................................. 55
D/A DIGITAL FILTER CHARACTERISTICS .......................................................................... 56
SWITCHING CHARACTERISTICS ........................................................................................ 61
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ............................... 62
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 63
DC ELECTRICAL CHARACTERISTICS ................................................................................ 64
DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 64
7 PARAMETER DEFINITIONS ................................................................................................... 65
8 REFERENCES ......................................................................................................................... 66
9 PACKAGE DIMENSIONS .................................................................................................... 67
THERMAL CHARACTERISTICS ........................................................................................... 67
CS42426
4
LIST OF FIGURES
Figure 1. Typical Connection Diagram ............................................................................................ 8
Figure 2. Typical Connection Diagram using the PLL ..................................................................... 9
Figure 3. Full-Scale Analog Input .................................................................................................. 10
Figure 4. Full-Scale Output ........................................................................................................... 12
Figure 5. ATAPI Block Diagram (x = channel pair 1, 2, 3)............................................................. 13
Figure 6. Clock Generation ........................................................................................................... 14
Figure 7. Right Justified Serial Audio Formats .............................................................................. 18
Figure 8. I
2
S Serial Audio Formats................................................................................................ 19
Figure 9. Left Justified Serial Audio Formats ................................................................................ 19
Figure 10. One Line Mode #1 Serial Audio Format ....................................................................... 20
Figure 11. One Line Mode #2 Serial Audio Format ....................................................................... 20
Figure 12. ADCIN1/ADCIN2 Serial Audio Format ......................................................................... 21
Figure 13. OLM Configuration #1 .................................................................................................. 22
Figure 14. OLM Configuration #2 .................................................................................................. 23
Figure 15. OLM Configuration #3 .................................................................................................. 24
Figure 16. OLM Configuration #4 .................................................................................................. 25
Figure 17. Control Port Timing in SPI Mode.................................................................................. 26
Figure 18. Control Port Timing, I2C Slave Mode Write ................................................................. 27
Figure 19. Control Port Timing, I2C Slave Mode Read ................................................................. 27
Figure 20. Single Speed Mode Stopband Rejection ..................................................................... 53
Figure 21. Single Speed Mode Transition Band............................................................................ 53
Figure 22. Single Speed Mode Transition Band (Detail) ............................................................... 53
Figure 23. Single Speed Mode Passband Ripple.......................................................................... 53
Figure 24. Double Speed Mode Stopband Rejection .................................................................... 53
Figure 25. Double Speed Mode Transition Band .......................................................................... 53
Figure 26. Double Speed Mode Transition Band (Detail).............................................................. 54
Figure 27. Double Speed Mode Passband Ripple ........................................................................ 54
Figure 28. Quad Speed Mode Stopband Rejection....................................................................... 54
Figure 29. Quad Speed Mode Transition Band ............................................................................. 54
Figure 30. Quad Speed Mode Transition Band (Detail) ................................................................ 54
Figure 31. Quad Speed Mode Passband Ripple........................................................................... 54
Figure 32. Single Speed (fast) Stopband Rejection ...................................................................... 57
Figure 33. Single Speed (fast) Transition Band ............................................................................ 57
Figure 34. Single Speed (fast) Transition Band (detail) ................................................................ 57
Figure 35. Single Speed (fast) Passband Ripple .......................................................................... 57
Figure 36. Single Speed (slow) Stopband Rejection ..................................................................... 57
Figure 37. Single Speed (slow) Transition Band ........................................................................... 57
Figure 38. Single Speed (slow) Transition Band (detail) ............................................................... 58
Figure 39. Single Speed (slow) Passband Ripple ......................................................................... 58
Figure 40. Double Speed (fast) Stopband Rejection ..................................................................... 58
Figure 41. Double Speed (fast) Transition Band ........................................................................... 58
Figure 42. Double Speed (fast) Transition Band (detail) ............................................................... 58
Figure 43. Double Speed (fast) Passband Ripple ......................................................................... 58
Figure 44. Double Speed (slow) Stopband Rejection ................................................................... 59
Figure 45. Double Speed (slow) Transition Band.......................................................................... 59
Figure 46. Double Speed (slow) Transition Band (detail).............................................................. 59
Figure 47. Double Speed (slow) Passband Ripple........................................................................ 59
Figure 48. Quad Speed (fast) Stopband Rejection ....................................................................... 59
Figure 49. Quad Speed (fast) Transition Band.............................................................................. 59
Figure 50. Quad Speed (fast) Transition Band (detail).................................................................. 60
Figure 51. Quad Speed (fast) Passband Ripple............................................................................ 60
5
CS42426
Figure 52. Quad Speed (slow) Stopband Rejection...................................................................... 60
Figure 53. Quad Speed (slow) Transition Band ............................................................................ 60
Figure 54. Quad Speed (slow) Transition Band (detail) ................................................................ 60
Figure 55. Quad Speed (slow) Passband Ripple .......................................................................... 60
Figure 56. Serial Audio Port Master Mode Timing ........................................................................ 61
Figure 57. Serial Audio Port Slave Mode Timing .......................................................................... 61
Figure 58. Control Port Timing - I2C Format................................................................................. 62
Figure 59. Control Port Timing - SPI Format................................................................................. 63
LIST OF TABLES
Table 1. PLL External Component Values .................................................................................... 15
Table 2. Common OMCK Clock Frequencies .............................................................................. 15
Table 3. Common PLL Output Clock Frequencies....................................................................... 16
Table 4. Slave Mode Clock Ratios ............................................................................................... 16
Table 5. Serial Audio Port Channel Allocations ............................................................................ 17
Table 6. DAC De-Emphasis .......................................................................................................... 34
Table 7. Digital Interface Formats ................................................................................................. 35
Table 8. ADC One_Line Mode ...................................................................................................... 35
Table 9. DAC One_Line Mode ...................................................................................................... 35
Table 10. RMCK Divider Settings ................................................................................................. 37
Table 11. OMCK Frequency Settings ........................................................................................... 38
Table 12. Master Clock Source Select.......................................................................................... 38
Table 13. PLL Clock Frequency Detection.................................................................................... 39
Table 14. Example Digital Volume Settings .................................................................................. 42
Table 15. ATAPI Decode .............................................................................................................. 44
Table 16. Example ADC Input Gain Settings ................................................................................ 45