Advance Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 2004

Cirrus Logic, Inc.
www.cirrus.com

CS42428

114 dB, 192 kHz 8-Ch Codec with PLL

Features

Eight 24-bit D/A, two 24-bit A/D converters
114 dB DAC / 114 dB ADC dynamic range
-100 dB THD+N
System sampling rates up to 192 kHz
Integrated low-jitter PLL for increased system
jitter tolerance
PLL clock or OMCK system clock selection
7 configurable general purpose outputs
ADC high pass filter for DC offset calibration
Expandable ADC channels and one-line
mode support
Digital output volume control with soft ramp
Digital +/-15 dB input gain adjust for ADC
Differential analog architecture
Supports logic levels between 5 V and 1.8 V

General Description

The CS42428 CODEC provides two analog-to-digital and eight
digital-to-analog Delta-Sigma converters, as well as an inte-
grated PLL, in a 64-pin LQFP package.

The CS42428 integrated PLL provides a low-jitter system
clock. The internal stereo ADC is capable of independent chan-
nel gain control for single-ended or differential analog inputs.
All eight channels of DAC provide digital volume control and
differential analog outputs. The general purpose outputs may
be driven high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.

The CS42428 is ideal for audio systems requiring wide dynam-
ic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.

ORDERING INFORMATION

CS42428-CQZ

-10° to 70° C

64-pin LQFP

CS42428-DQZ

-40° to 85° C

64-pin LQFP

CDB42428

Evaluation Board

PLL

Internal Voltage

R eference

RST

G PO 1

A D0/C S

S CL/C C LK

S DA/CD O UT

AD 1/CD IN

V LC

AO U TA1+
AO U TA1-

A O UTB 1+

A O UTA 3+
AO U TA3-

AO U TA2-

AO U TB2-

A O UTA 2+

AO U TB2+

AO U TB1-

A O UTB 3+

AO UT B3-

AO U TA4+
AO UTA 4-

AO U TB4+
AO U TB4-

A INL+

A IN L-

AIN R+
AINR -

F ILT+

R EFG N D

A DC #1

AD C#2

D igital F ilter

G ain & C lip

D AC_S CLK

D AC_LR CK

DAC _SDIN4

DAC _SD IN 3

DA C_SD IN 2

D AC_SD IN 1

VLS

D G ND

O MC K

RM CK

LPFLT

INT

Control

Port

D AC#1

D AC#2

D AC #3

D AC#4

D AC#5

D AC #6

D AC#7

DAC #8

i
g

i
t
a

l F

ilt

l
u

t
r
o

G PO 2
G PO 3
G PO 4
G PO 5
G PO 6
G PO 7

MU TEC

M ute

nal

i
l
t
er

AG N D

Mult/Div

G PO

l T

r
a

t
o

r
i
al

udi

r
t

ADC _SDO U T

ADC IN 1
A DC IN 2

AD C_LRC K

ADC

Serial
Audio

Port

ADC _SCLK

Lev

r
an

l
at

JUL `04

DS605A2

CS42428

TABLE OF CONTENTS

1 PIN DESCRIPTIONS ................................................................................................................. 6
2 TYPICAL CONNECTION DIAGRAMS ..................................................................................... 8
3 APPLICATIONS ....................................................................................................................... 10

3.1 Overview .......................................................................................................................... 10
3.2 Analog Inputs ................................................................................................................... 10

3.2.1 Line Level Inputs ................................................................................................. 10
3.2.2 External Input Filter ............................................................................................. 11
3.2.3 High Pass Filter and DC Offset Calibration ......................................................... 11

3.3 Analog Outputs ................................................................................................................ 11

3.3.1 Line Level Outputs and Filtering ......................................................................... 11
3.3.2 Interpolation Filter ............................................................................................... 12
3.3.3 Digital Volume and Mute Control ........................................................................ 12
3.3.4 ATAPI Specification ............................................................................................ 13

3.4 Clock Generation ............................................................................................................. 14

3.4.1 PLL and Jitter Attenuation ................................................................................... 14
3.4.2 OMCK System Clock Mode ................................................................................ 15
3.4.3 Master Mode ....................................................................................................... 15
3.4.4 Slave Mode ......................................................................................................... 15

3.5 Digital Interfaces .............................................................................................................. 16

3.5.1 Serial Audio Interface Signals ............................................................................. 16
3.5.2 Serial Audio Interface Formats ............................................................................ 18
3.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................. 21
3.5.4 One Line Mode(OLM) Configurations ................................................................. 22

3.6 Control Port Description and Timing ................................................................................ 26

IMPORTANT NOTICE

"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiar-
ies ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor-
mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and condi-
tions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No
responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items,
or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants
no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus
owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within
your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described
in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or
quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material
is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHO-
RIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COM-
PONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICA-
TIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,
STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES
OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY
CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING
ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Purchase of I

C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I

C Patent Rights to use

those components in a standard I

C system.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to

www.cirrus.com/

CS42428

3.6.1 SPI Mode ............................................................................................................ 26
3.6.2 I2C Mode ............................................................................................................ 27

3.7 Interrupts ......................................................................................................................... 28
3.8 Reset and Power-up ....................................................................................................... 29
3.9 Power Supply, Grounding, and PCB layout ..................................................................... 29

4 REGISTER QUICK REFERENCE ........................................................................................... 30
5 REGISTER DESCRIPTION ..................................................................................................... 32

5.1 Memory Address Pointer (MAP) ....................................................................................... 32
5.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 32
5.3 Power Control (address 02h)............................................................................................ 33
5.4 Functional Mode (address 03h) ........................................................................................ 33
5.5 Interface Formats (address 04h) ...................................................................................... 34
5.6 Misc Control (address 05h) .............................................................................................. 36
5.7 Clock Control (address 06h) ............................................................................................. 37
5.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 39
5.9 Clock Status (address 08h) (Read Only) .......................................................................... 39
5.10 Volume Control (address 0Dh) ....................................................................................... 40
5.11 Channel Mute (address 0Eh).......................................................................................... 41
5.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ........................ 42
5.13 Channel Invert (address 17h) ......................................................................................... 42
5.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)

Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................ 42

5.15 ADC Left Channel Gain (address 1Ch) .......................................................................... 45
5.16 ADC Right Channel Gain (address 1Dh) ........................................................................ 45
5.17 Interrupt Control (address 1Eh) ...................................................................................... 45
5.18 Interrupt Status (address 20h) (Read Only) ................................................................... 46
5.19 Interrupt Mask (address 21h) ......................................................................................... 47
5.20 Interrupt Mode MSB (address 22h)

Interrupt Mode LSB (address 23h)................................................................................ 47

5.21 MuteC Pin Control (address 28h) ................................................................................... 47
5.22 General Purpose Pin Control (addresses 29h to 2Fh) ................................................... 48

6 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 50

SPECIFIED OPERATING CONDITIONS ............................................................................... 50
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 50
ANALOG INPUT CHARACTERISTICS .................................................................................. 51
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................... 52
ANALOG OUTPUT CHARACTERISTICS .............................................................................. 55
D/A DIGITAL FILTER CHARACTERISTICS .......................................................................... 56
SWITCHING CHARACTERISTICS ........................................................................................ 61
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ............................... 62
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 63
DC ELECTRICAL CHARACTERISTICS ................................................................................ 64
DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 64

7 PARAMETER DEFINITIONS ................................................................................................... 65
8 REFERENCES ......................................................................................................................... 66
9 PACKAGE DIMENSIONS .................................................................................................... 67

THERMAL CHARACTERISTICS ........................................................................................... 67

CS42428

LIST OF FIGURES

Figure 1. Typical Connection Diagram ............................................................................................ 8
Figure 2. Typical Connection Diagram using the PLL ..................................................................... 9
Figure 3. Full-Scale Analog Input .................................................................................................. 10
Figure 4. Full-Scale Output ........................................................................................................... 12
Figure 5. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)......................................................... 13
Figure 6. Clock Generation ........................................................................................................... 14
Figure 7. Right Justified Serial Audio Formats .............................................................................. 18
Figure 8. I

S Serial Audio Formats................................................................................................ 19

Figure 9. Left Justified Serial Audio Formats ................................................................................ 19
Figure 10. One Line Mode #1 Serial Audio Format ....................................................................... 20
Figure 11. One Line Mode #2 Serial Audio Format ....................................................................... 20
Figure 12. ADCIN1/ADCIN2 Serial Audio Format ......................................................................... 21
Figure 13. OLM Configuration #1 .................................................................................................. 22
Figure 14. OLM Configuration #2 .................................................................................................. 23
Figure 15. OLM Configuration #3 .................................................................................................. 24
Figure 16. OLM Configuration #4 .................................................................................................. 25
Figure 17. Control Port Timing in SPI Mode.................................................................................. 26
Figure 18. Control Port Timing, I2C Slave Mode Write ................................................................. 27
Figure 19. Control Port Timing, I2C Slave Mode Read ................................................................. 27
Figure 20. Single Speed Mode Stopband Rejection ..................................................................... 53
Figure 21. Single Speed Mode Transition Band............................................................................ 53
Figure 22. Single Speed Mode Transition Band (Detail) ............................................................... 53
Figure 23. Single Speed Mode Passband Ripple.......................................................................... 53
Figure 24. Double Speed Mode Stopband Rejection .................................................................... 53
Figure 25. Double Speed Mode Transition Band .......................................................................... 53
Figure 26. Double Speed Mode Transition Band (Detail).............................................................. 54
Figure 27. Double Speed Mode Passband Ripple ........................................................................ 54
Figure 28. Quad Speed Mode Stopband Rejection....................................................................... 54
Figure 29. Quad Speed Mode Transition Band ............................................................................. 54
Figure 30. Quad Speed Mode Transition Band (Detail) ................................................................ 54
Figure 31. Quad Speed Mode Passband Ripple........................................................................... 54
Figure 32. Single Speed (fast) Stopband Rejection ...................................................................... 57
Figure 33. Single Speed (fast) Transition Band ............................................................................ 57
Figure 34. Single Speed (fast) Transition Band (detail) ................................................................ 57
Figure 35. Single Speed (fast) Passband Ripple .......................................................................... 57
Figure 36. Single Speed (slow) Stopband Rejection ..................................................................... 57
Figure 37. Single Speed (slow) Transition Band ........................................................................... 57
Figure 38. Single Speed (slow) Transition Band (detail) ............................................................... 58
Figure 39. Single Speed (slow) Passband Ripple ......................................................................... 58
Figure 40. Double Speed (fast) Stopband Rejection ..................................................................... 58
Figure 41. Double Speed (fast) Transition Band ........................................................................... 58
Figure 42. Double Speed (fast) Transition Band (detail) ............................................................... 58
Figure 43. Double Speed (fast) Passband Ripple ......................................................................... 58
Figure 44. Double Speed (slow) Stopband Rejection ................................................................... 59
Figure 45. Double Speed (slow) Transition Band.......................................................................... 59
Figure 46. Double Speed (slow) Transition Band (detail).............................................................. 59
Figure 47. Double Speed (slow) Passband Ripple........................................................................ 59
Figure 48. Quad Speed (fast) Stopband Rejection ....................................................................... 59
Figure 49. Quad Speed (fast) Transition Band.............................................................................. 59
Figure 50. Quad Speed (fast) Transition Band (detail).................................................................. 60
Figure 51. Quad Speed (fast) Passband Ripple............................................................................ 60

CS42428

Figure 52. Quad Speed (slow) Stopband Rejection...................................................................... 60
Figure 53. Quad Speed (slow) Transition Band ............................................................................ 60
Figure 54. Quad Speed (slow) Transition Band (detail) ................................................................ 60
Figure 55. Quad Speed (slow) Passband Ripple .......................................................................... 60
Figure 56. Serial Audio Port Master Mode Timing ........................................................................ 61
Figure 57. Serial Audio Port Slave Mode Timing .......................................................................... 61
Figure 58. Control Port Timing - I2C Format................................................................................. 62
Figure 59. Control Port Timing - SPI Format................................................................................. 63

LIST OF TABLES

Table 1. PLL External Component Values .................................................................................... 15
Table 2. Common OMCK Clock Frequencies .............................................................................. 15
Table 3. Common PLL Output Clock Frequencies....................................................................... 16
Table 4. Slave Mode Clock Ratios ............................................................................................... 16
Table 5. Serial Audio Port Channel Allocations ............................................................................ 17
Table 6. DAC De-Emphasis .......................................................................................................... 34
Table 7. Digital Interface Formats ................................................................................................. 35
Table 8. ADC One_Line Mode ...................................................................................................... 35
Table 9. DAC One_Line Mode ...................................................................................................... 35
Table 10. RMCK Divider Settings ................................................................................................. 37
Table 11. OMCK Frequency Settings ........................................................................................... 38
Table 12. Master Clock Source Select.......................................................................................... 38
Table 13. PLL Clock Frequency Detection.................................................................................... 39
Table 14. Example Digital Volume Settings .................................................................................. 42
Table 15. ATAPI Decode .............................................................................................................. 44
Table 16. Example ADC Input Gain Settings ................................................................................ 45

CS42428

1 PIN DESCRIPTIONS

Pin Name

Pin Description

DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4

64
63
62

DAC Serial Audio Data Input (

Input) - Input for two's complement serial audio data.

DAC_SCLK

DAC Serial Clock

(Input/Output) - Serial clock for the DAC serial audio interface.

DAC_LRCK

DAC Left Right Clock (

Input/Output) - Determines which channel, Left or Right, is currently active on

the DAC serial audio data line.

Digital Power (

Input) - Positive power supply for the digital section.

DGND

Digital Ground (

Input) - Ground reference. Should be connected to digital ground.

VLC

Control Port Power (

Input) - Determines the required signal level for the control port.

SCL/CCLK

Serial Control Port Clock (

Input) - Serial clock for the serial control port. Requires an external pull-up

resistor to the logic interface voltage in I

C mode as shown in the Typical Connection Diagram.

SDA/CDOUT

Serial Control Data (

Input/Output) - SDA is a data I/O line in I

C mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.

AD1/CDIN

Address Bit 1 (I

C)/Serial Control Data (SPI) (

Input) - AD1 is a chip address pin in I

C mode; CDIN is

the input data line for the control port interface in SPI mode.

AD0/CS

Address Bit 0 (I

C)/Control Port Chip Select (SPI)

(Input) - AD0 is a chip address pin in I

C mode; CS

is the chip select signal in SPI mode.

INT

Interrupt

(Output) - The CS42428 will generate an interrupt condition as per the Interrupt Mask register.

See "Interrupts" on page 28 for more details.

1 7 18 19

20 21

22 23 24 25 2 6 27

28 29 3 0 31 32

6 3 6 2 6 1 60

59 58 57 56 5 5 54

53 52 5 1 50 49

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

DAC _SDIN1

D G ND

VLC

SC L/CC LK

SDA/CD O UT

AD 1/CDIN

AD0/CS

INT

R ST

AINR -

AIN R+

AIN L+

AINL -

AO UTA2-

AOU TB1-

AO UTB1+

AO UTA1+

AO UTA1-

M U TEC

AG N D

G PO 7

G PO 6

G PO 5

G PO 4

G PO 3

G PO 2

G PO 1

L PFL T

D AC_ LRC K

DAC _SCL K

I
N

CS42428

CS42428

RST

Reset (

Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low.

AINR-
AINR+

13
14

Differential Right Channel Analog Input (

Input) - Signals are presented differentially to the delta-sigma

modulators via the AINR+/- pins.

AINL+
AINL-

15
16

Differential Left Channel Analog Input (

Input) - Signals are presented differentially to the delta-sigma

modulators via the AINL+/- pins.

Quiescent Voltage (

Output) - Filter connection for internal quiescent reference voltage.

FILT+

Positive Voltage Reference (

Output) - Positive reference voltage for the internal sampling circuits.

REFGND

Reference Ground (

Input) - Ground reference for the internal sampling circuits.

AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-

36,37
35,34
32,33
31,30
28,29
27,26
22,23
21,20

Differential Analog Output (

Output) - The full-scale differential analog output level is specified in the

Analog Characteristics specification table.

24
41

Analog Power (

Input) - Positive power supply for the analog section.

AGND

25
40

Analog Ground (

Input) - Ground reference. Should be connected to analog ground.

MUTEC

Mute Control (

Output) - The Mute Control pin outputs high impedance following an initial power-on con-

dition or whenever the PDN bit is set to a `1', forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

LPFLT

PLL Loop Filter (

Output) - An RC network should be connected between this pin and ground.

GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1

42
43
44
45
46
47
48

General Purpose Output (

Output) - These pins can be configured as general purpose output pins, an

ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers.

VLS

Serial Port Interface Power (

Input) - Determines the required signal level for the serial port interfaces.

RMCK

Recovered Master Clock (

Output) - Recovered master clock output from the External Clock Reference

(OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK.

ADC_SDOUT

ADC Serial Data Output (

Output) - Output for two's complement serial audio PCM data from the output

of the internal and external ADCs.

ADCIN1
ADCIN2

58
57

External ADC Serial Input (

Input) - The CS42428 provides for up to two external stereo analog to digital

converter inputs to provide a maximum of six channels on one serial data output line when the CS42428
is placed in One Line mode.

OMCK

External Reference Clock (

Input) - External clock reference that must be within the ranges specified in

the register "OMCK Frequency (OMCK Freqx)" on page 38.

ADC_LRCK

ADC Left/Right Clock (

Input/Output) - Determines which channel, Left or Right, is currently active on

the ADC serial audio data line.

ADC_SCLK

ADC Serial Clock

(Input/Output) - Serial clock for the ADC serial audio interface.

CS42428

2 TYPICAL CONNECTION DIAGRAMS

AOUTA1+

0.1 µF

10 µF

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

10 µF

Analog Conditioning

and Muting

AOUTA1-

AOUTB1+

Analog Conditioning

and Muting

AOUTB1-

AOUTA2+

Analog Conditioning

and Muting

AOUTA2-

AOUTB2+

Analog Conditioning

and Muting

AOUTB2-

AOUTA3+

Analog Conditioning

and Muting

AOUTA3-

AOUTB3+

Analog Conditioning

and Muting

AOUTB3-

AOUTA4+

Analog Conditioning

and Muting

AOUTA4-

AOUTB4+

Analog Conditioning

and Muting

AOUTB4-

MUTEC

Mute
Drive

DGND DGND

VLC

0.1 µF

+1.8 V

to +5 V

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

2 k

Note: Resistors are required for

C control port operation

See
Note

ADC_LRCK

REFGND

AD0/CS

INT

Digital Audio

Processor

Micro-

Controller

RMCK

ADCIN1

ADCIN2

CS5361

A/D Converter

CS5361

A/D Converter

ADC_SDOUT

0.1 µF

AGND

CFILT**

RFILT**

LPFLT

CRIP**

2700 pF*

AINL+

AINL-

AINR+

AINR-

Left Analog Input

Right Analog Input

* See CDB42428 for a recommended filter.

** Refer to Table 1

for proper values

Connect DGND and AGND at single point near Codec

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_SDIN4

DAC_LRCK

DAC_SCLK

Analog

Input

Buffer *

Analog

Input

Buffer *

+VA

***

*** Pull up or down as required on startup

***

0.01 µF

0.1 µF

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF

0.01 µF

VLS

0.1 µF

+2.5 V

to +5 V

OMCK

OSC

Figure 1. Typical Connection Diagram

CS42428

CS42428

VLS

AOUTA1+

0.1 µF +

10 µF

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

10 µF

0.1 µF

+1.8 V

to +5.0 V

Analog Conditioning

and Muting

AOUTA1-

AOUTB1+

Analog Conditioning

and Muting

AOUTB1-

AOUTA2+

Analog Conditioning

and Muting

AOUTA2-

AOUTB2+

Analog Conditioning

and Muting

AOUTB2-

AOUTA3+

Analog Conditioning

and Muting

AOUTA3-

AOUTB3+

Analog Conditioning

and Muting

AOUTB3-

AOUTA4+

Analog Conditioning

and Muting

AOUTA4-

AOUTB4+

Analog Conditioning

and Muting

AOUTB4-

MUTEC

Mute
Drive

DGND DGND

VLC

0.1 µF

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

2 k

Note: Resistors are required for

C control port operation

See
Note

OMCK

ADC_LRCK

REFGND

AD0/CS

INT

DVD

Processor

RMCK

ADCIN1

ADCIN2

ADC_SDOUT

0.1 µF

AGND

CFILT**

RFILT**

LPFLT

CRIP**

2700 pF*

AINL+

AINL-

AINR+

AINR-

Left Analog Input

Right Analog Input

* See CDB42428 for a recommended filter.

** Refer to Table 1

for proper values

Connect DGND and AGND at single point near Codec

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_SDIN4

DAC_LRCK

DAC_SCLK

Analog

Input

Buffer *

Analog

Input

Buffer *

+VA

***

*** Pull up or down as required on startup

***

0.01 µF

0.1 µF +

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF

0.01 µF

27 MHz

Figure 2. Typical Connection Diagram using the PLL

CS42428

CS42428

3 APPLICATIONS

3.1

Overview

The CS42428 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital con-
verters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters
(DAC). Other functions integrated within the codec include independent digital volume controls for each
DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters,
and an on-chip voltage reference. All serial data is transmitted through one configurable serial audio inter-
face for the ADC with enhanced one line modes of operation allowing up to 6 channels of serial audio data
on one data line. All functions are configured through a serial control port operable in SPI mode or in I

mode. Figure 1 shows the recommended connections for the CS42428.

The CS42428 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register "Functional Mode (address 03h)" on page 33. Single-Speed mode
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.

Using the integrated PLL, a low jitter clock is recovered from the ADC LRCK input signal. The recovered
clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.

3.2

Analog Inputs

3.2.1

Line Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line level differential analog inputs. These pins are internally
biased to the DC quiescent reference voltage, VQ, of approximately 2.7 V. The level of the signal can be
adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain Control
Registers on page 45. The ADC output data is in 2's complement binary format. For inputs above positive
full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause
the ADC Overflow bit in the register "Interrupt Status (address 20h) (Read Only)" on page 46 to be set to
a `1'. The GPO pins may also be configured to indicate an overflow condition has occurred in the ADC.
See "General Purpose Pin Control (addresses 29h to 2Fh)" on page 48 for proper configuration. Figure 3
shows the full-scale analog input levels.

AIN+

AIN-

Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp

4.1 V

2.7 V

1.3 V

4.1 V

2.7 V

1.3 V

Figure 3. Full-Scale Analog Input

CS42428

3.2.2

External Input Filter

The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter
will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are (n

6.144 MHz) the digital passband frequency, where n=0,1,2,...

Refer to the CDB42418 for a rec-

ommended analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing
the optimum source impedance for the modulators. The use of capacitors which have a large voltage coef-
ficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.

3.2.3

High Pass Filter and DC Offset Calibration

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during
normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC
offset will continue to be subtracted from the conversion result. This feature makes it possible to perform
a system DC offset calibration by:

1) Running the CS42428 with the high pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

The high pass filters are controlled using the HPF_FREEZE bit in the register "Misc Control (address
05h)" on page 36.

3.3

Analog Outputs

3.3.1

Line Level Outputs and Filtering

The CS42428 contains on-chip buffer amplifiers capable of producing line level differential outputs. These
amplifiers are biased to a quiescent DC level of approximately VQ.

The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low pass filter. The recommended output filter configuration is shown in the CDB42418. This
filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential
output pins. It also shows an AC coupling configuration which minimizes the number of required AC cou-
pling capacitors.

CS42428

The CS42428 is a linear phase design and does not include phase or amplitude compensation for an exter-
nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an-
alog circuitry. Figure 4 shows the full-scale analog output levels.

3.3.2

Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS42428 incorpo-
rates selectable interpolation filters for each mode of operation. A "fast" and a "slow" roll-off filter is avail-
able in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate
a variety of musical tastes and styles. The FILT_SEL bit found in the register "Misc Control (address 05h)"
on page 36 is used to select which filter is used. Filter response plots can be found in Figures 32 to

55.

3.3.3

Digital Volume and Mute Control

Each DAC's output level is controlled via the Volume Control registers operating over the range of 0 to
-127 dB attenuation with 0.5 dB resolution. See "Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h,
15h, 16h)" on page 42. Volume control changes are programmable to ramp in increments of 0.125 dB at
the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See "Volume Control (ad-
dress 0Dh)" on page 40.

Each output can be independently muted via mute control bits in the register "Channel Mute (address
0Eh)" on page 41. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum
value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation
level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by
the SZC[1:0] bits.

The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Con-
trol pin is tri-stated during power up or in power down mode by setting the PDN bit in the register "Power
Control (address 02h)" on page 33 to a `1'. Once out of power-down mode the pin can be controlled by the
user via the control port, or automatically asserted high when zero data is present on all DAC inputs, or
when serial port clock errors are present. To prevent large transients on the output, it is desirable to mute
the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descrip-
tions section for more information.

AO UT+

AO UT-

Full-Scale O utput Level= (AIN +) - (AIN -)= 5 Vpp

3.95 V

2.7 V

1.45 V

3.95 V

2.7 V

1.45 V

Figure 4. Full-Scale Output

CS42428

3.4

Clock Generation

The clock generation for the CS42428

is shown in the figure below. The internal MCLK is derived from

the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of
PLL lock to the other source input.

3.4.1

PLL and Jitter Attenuation

The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to
have good jitter attenuation characteristics. By setting the PLL_LRCK bit to a `1' in the register "Clock
Control (address 06h)" on page 37, the PLL will lock to the incoming ADC_LRCK and generate an output
master clock (RMCK) of 256Fs. Table 3 below shows the output of the PLL with typical input Fs values
for ADC_LRCK.

The PLL behavior is affected by the external filter component values. Figure 1 shows the required config-
uration of the external filter components. The set of component values required for 32 kHz to 192 kHz

ADC_LRCK

(slave mode)

PLL (256Fs)

8.192 -

49.152 MHz

P LL_LRCK b it

SW_CTRLx bits

(manual or auto

switch)

O MCK

Auto Detect

Input Clock

1,1.5, 2, 4

single

speed

256

double

speed

128

quad

speed

single

speed

double

speed

quad

speed

not O LM

OLM #1

DAC _FMx bits

ADC_ FMx bits

DAC_OLx

ADC_O Lx bits

ADC_O Lx and

ADC _S P SELx b its

ADC_SCLK

DAC_SCLK

D AC_LRCK

ADC_LRCK

RMCK

OLM #2

not O LM

O LM #1

OLM #2

128FS

256FS

128FS

256FS

Internal

MCLK

RMCK_DIVx bits

Figure 6. Clock Generation

CS42428

sample rate applications are shown in Table 1. The lock time is the worst case for an Fs transition from un-
locked state to locking to 192 kHz.

It is important to treat the LPFLT pin as a low level analog input. It is suggested that the ground end of the
PLL filter be returned directly to the AGND pin independently of the digital ground plane.

3.4.2

OMCK System Clock Mode

A special clock switching mode is available that allows the clock that is input through the OMCK pin to
be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register "Clock
Control (address 06h)" on page 37. An advanced auto switching mode is also implemented to maintain
master clock functionality. The clock auto switching mode allows the clock input through OMCK to be
used as a clock in the system without any disruption when the PLL loses lock, for example, when the
LRCK is removed from ADC_LRCK. This clock switching is done glitch free.

3.4.3

Master Mode

In master mode, the serial interface timings are derived from an external clock attached to OMCK or the
output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 and CLK_SEL bits in
the Clock Control Register (See "Clock Control (address 06h)" on page 37).

The sample rate to OMCK ratios and OMCK frequency requirements for Master mode operation are
shown in Table 2.

3.4.4

Slave Mode

In Slave mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs and must be synchronously derived from the
supplied master clock, OMCK or must be synchronous to the supplied ADC_LRCK used as the input to

Fs Range (kHz) RFILT (k

) CFILT (pF) CRIP (pF) Settling time

32 to 192

2700

680

11 ms

Table 1. PLL External Component Values

Sample

Rate

(kHz)

OMCK (MHz)

Single Speed

(4 to 50 kHz)

Double Speed

(50 to 100 kHz)

Quad Speed

(100 to 192 kHz)

256x

384x

512x

128x

192x

256x

64x

96x

128x

12.2880

18.4320 24.5760

12.2880 18.4320 24.5760

192

12.2880 18.4320 24.5760

Table 2. Common OMCK Clock Frequencies

CS42428

the PLL. In this latter scenario the PLL output becomes the internal master clock. The supported PLL out-
put frequencies are shown in Table 3 below.

The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronous to the corresponding
DAC_LRCK/ADC_LRCK and be equal to 128x, 64x, 48x or 32x Fs depending on the interface format
selected and desired speed mode. One Line Mode #1 is supported in Slave Mode. One Line Mode #2 is
not supported. Refer to Table 4 for required clock ratios.

3.5

Digital Interfaces

3.5.1

Serial Audio Interface Signals

The CS42428 interfaces to an external Digital Audio Processor via two independent serial ports, the
DAC serial port, DAC_SP and the ADC serial port, ADC_SP. The digital output of the internal ADCs use
the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings. These con-
figuration bits and the selection of Single, Double or Quad Speed mode for DAC_SP and ADC_SP are
found in register "Functional Mode (address 03h)" on page 33.

The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for trans-
mitting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42428
(master mode) or it can be input from an external source (slave mode). Master or Slave mode selection is
made using bits DAC_SP M/S and ADC_SP M/S in register "Misc Control (address 05h)" on page 36.

The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the
start of a new sample period. It may be an output of the CS42428 (master mode), or it may be generated
by an external source (slave mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.

The serial data interface format selection (left/right justified, I

S or one line mode) for the ADC serial port

data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:4, is configured using the appropriate

Single Speed

Double Speed

Quad Speed

One Line Mode #1

OMCK/LRCK Ratio

256x, 512x

128x, 256x

128x

256x

SCLK/LRCK Ratio

32x, 48x, 64x, 128x

32x, 64x

128x

Table 4. Slave Mode Clock Ratios

Sample

Rate

(kHz)

PLL Output (MHz)

Single Speed

(4 to 50 kHz)

Double Speed

(50 to 100 kHz)

Quad Speed

(100 to 192 kHz)

256x

8.1920

44.1

11.2896

12.2880

16.3840

88.2

22.5792

24.5760

176.4

45.1584

192

49.1520

Table 3. Common PLL Output Clock Frequencies

CS42428

bits in the register "Interface Formats (address 04h)" on page 34. The serial audio data is presented in 2's
complement binary form with the MSB first in all formats.

DAC_SDIN1, DAC_SDIN2, DAC_SDIN3 and DAC_SDIN4 are the serial data input pins supplying the
internal DAC. ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs
and, when configured for one-line mode, up to four additional ADC channels attached externally to the
signals ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One Line Data
Mode, 6 channels of DAC data are input on DAC_SDIN1, two additional DAC channels on DAC_SDIN4,
and 6 channels of ADC data are output on ADC_SDOUT. Table 5 outlines the serial port channel alloca-
tions.

Serial Inputs / Outputs

DAC_SDIN1 left channel

right channel

one line mode

DAC #1
DAC #2
DAC channels 1,2,3,4,5,6

DAC_SDIN2 left channel

right channel

one line mode

DAC #3
DAC #4
not used

DAC_SDIN3 left channel

right channel

one line mode

DAC #5
DAC #6
not used

DAC_SDIN4 left channel

right channel

one line mode

DAC #7
DAC #8
DAC channels 7,8

ADC_SDOUT left channel

right channel

one line mode

ADC #1
ADC #2
ADC channels 1,2,3,4,5,6

ADCIN1 left channel

right channel

External ADC #3
External ADC #4

ADCIN2 left channel

right channel

External ADC #5
External ADC #6

Table 5. Serial Audio Port Channel Allocations

CS42428

3.5.4

One Line Mode(OLM) Configurations

3.5.4.1

OLM Config #1

One Line Mode Configuration #1 can support up to 8 channels of DAC data, and 6 channels of ADC data.
This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz
on all channels for both the DAC and ADC.

Register / Bit Settings

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = ADC_FMx = 00,01,10

DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported

Set ADC_CLK_SEL = 0

Configure ADC_SDOUT to be clocked from the DAC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01,10

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01,10

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1

Configure DAC Serial Port to master mode.

Set ADC_SP M/S = 1

Configure ADC Serial Port to master mode.

Set EXT ADC SCLK = 0

Identify external ADC clock source as ADC Serial Port.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One
Line Mode

DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK

not valid

One Line
Mode #1

DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK

not valid

One Line
Mode #2

DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK

not valid

DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK

S CLK _P ORT1

LR C K_POR T1

SD IN_POR T1

S CLK _P ORT2

LR C K_POR T2

SD OUT1_POR T2

SD OUT2_POR T2

SD OUT3_POR T2

SD OUT4_POR T2

A DC _SC LK

AD C_LRC K

D AC _SC LK

DA C_LRC K

AD C _S DOU T

D AC _SD IN1

D AC _SD IN2

D AC _SD IN3

D AC _SD IN4

RM CK

A DC IN 1

A DC IN 2

MC LK

SD OUT1

SD OUT2

LR CK

S CLK

64Fs

AD C D ata

64Fs,128Fs, 256Fs

DIG ITA L A UD IO

PRO CESSO R

CS5361

C S5361

MC LK

Figure 13. OLM Configuration #1

CS42428

CS42428

3.5.4.2

OLM Config #2

This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and will handle up
to 20-bit samples at a sampling frequency of 96 kHz on all channels for both the DAC and ADC. The out-
put data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run
at the DAC Serial Port sample frequency.

Register / Bit Settings

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK

Set ADC_FMx = 00,01,10

ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK

Set ADC_CLK_SEL = 1

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01,10

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set CODEC Serial Port to master mode.

Set SAI_SP M/S = 1

Set Serial Audio Interface Port to master mode.

Set EXT ADC SCLK = 1

Identify external ADC clock source as DAC Serial Port.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One
Line Mode

DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM

not valid

One Line
Mode #1

DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=CX_LRCK

DAC_SCLK=128Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=CX_LRCK

not valid

One Line
Mode #2

DAC_SCLK=64Fs
DAC_LRCK=SSM
ADC_SCLK=256Fs
ADC_LRCK=CX_LRCK

not valid

SC LK_PO RT1

LRC K_PO R T1

SD IN _PO R T1

SC LK_PO RT2

LRC K_P OR T2

SD O UT1_PO RT2

SD O UT2_PO RT2

SD O UT3_PO RT2

SD O UT4_PO RT2

R MCK

ADC IN1

ADC IN2

MCLK

SDO UT1

SDO UT2

LRCK

SCLK

64Fs,128Fs

ADC Data

64Fs ,128Fs,

256Fs

DIGITA L AUD IO

PROCESSOR

CS5361

C S5361

AD C_SCLK

ADC _LRC K

AD C_S DO UT

DA C_S CLK

D AC_LRCK

DAC _SD IN1

DAC _SD IN2

DAC _SD IN3

DAC _SD IN4

MCLK

Figure 14. OLM Configuration #2

CS42428

CS42428

3.5.4.3

OLM Config #3

This configuration will support up to 8 channels of DAC data, and 6 channels of ADC data. OLM Config
#3 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz.
Since the ADCs data stream is configured to use the ADC_SDOUT output and the internal and external
ADCs are clocked from the ADC_SP, then the sample rate for the DAC Serial Port can be different from
the sample rate of the ADC serial port.

Register / Bit Settings

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK

Set ADC_FMx = 00,01,10

ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK

Set ADC_CLK_SEL = 1

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01,10

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1

Set DAC Serial Port to master mode.

Set ADC_SP M/S = 0 or 1

Set ADC Serial Port to master mode or slave mode.

Set EXT ADC SCLK = 0

Identify external ADC clock source as ADC Serial Port.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One
Line Mode

DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM

One Line
Mode #1

DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=128Fs
ADC_LRCK=SSM

DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=SSM

DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=SSM

One Line
Mode #2

not valid

SC LK_ POR T1

LRC K_PO RT1

S DIN _PO RT1

SC LK_ POR T2

LRC K_PO RT2

SDO UT1_P ORT2

SDO UT2_P ORT2

SDO UT3_P ORT2

SDO UT4_P ORT2

RM CK

AD CIN1

AD CIN2

MC LK

SDO UT1

SDO UT2

LR CK

SCL K

64Fs,128Fs

DIG ITAL AUD IO

PRO CESSO R

CS5361

ADC_ SCL K

AD C_L RCK

ADC_ SDO UT

DAC _SCL K

D AC_L RCK

DAC_ SDIN1

DAC_ SDIN2

DAC_ SDIN3

DAC_ SDIN4

M CL K

64Fs,128Fs,256Fs

Figure 15. OLM Configuration #3

CS42428

CS42428

3.5.4.4

OLM Config #4

This One-Line Mode configuration can support up to 8 channels of DAC data on 2 DAC_SDIN pins, and
2 channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all
channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to
run at the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at
different Fs rates.

Register / Bit Settings

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK

Set ADC_FMx = 00,01,10

ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK

Set ADC_CLK_SEL = 0 or 1

Configure ADC_SDOUT to be clocked from the ADC_SP or DAC_SP

clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00

Set ADC operating mode to Not One Line Mode since only 2 channels of

ADC are supported

Set DAC_OLx bits = 00,01,10

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 0 or 1

Set DAC Serial Port to master mode or slave mode.

Set ADC_SP M/S = 0 or 1

Set ADC Serial Port to master mode or slave mode.

Set EXT ADC SCLK = 0

External ADCs are not used. Leave bit in default state.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One
Line Mode

DAC_SCLK=64Fs/128Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM

One Line
Mode #1

not valid

One Line
Mode #2

not valid

SCLK _P ORT1

LRCK _P O RT1

SDIN_P ORT 1

S DIN_P O RT2

S CLK _PO RT2

LRCK_P ORT2

S DOUT1_P ORT2

S DOUT2_P ORT2

S DOUT3_P ORT2

S DOUT4_P ORT2

RM CK

ADCIN1

ADCIN2

6 4Fs,12 8Fs , 256 Fs

DIGITAL AUDIO

PRO CESS O R

ADC_S CLK

ADC_LRCK

A DC_S DOUT

DA C_SCLK

DAC_LRCK

DAC_S DIN1

DAC_S DIN2

DAC_S DIN3

DAC_S DIN4

6 4Fs ,1 28Fs

M CLK

Figure 16. OLM Configuration #4

CS42428

CS42428

3.6

Control Port Description and Timing

The control port is used to access the registers, allowing the CS42428 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.

The control port has 2 modes: SPI and I

C, with the CS42428 acting as a slave device. SPI mode is selected

if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I

C mode

is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently se-
lecting the desired AD0 bit address state.

3.6.1

SPI Mode

In SPI mode, CS is the CS42428 chip select signal, CCLK is the control port bit clock (input into the
CS42428 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.

Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 k

resistor, if desired.

There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or

M A P

MSB

LSB

DATA

b y te 1

b y te n

R/W

A D D R E S S

C H IP

ADDRESS

C H IP

C D IN

C C L K

C D O U T

MSB

LSB MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 17. Control Port Timing in SPI Mode

CS42428

not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W)
high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave
the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will
appear consecutively.

3.6.2

C Mode

In I

C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS42428 is being reset.

The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42428 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42428,
the chip address field, which is the first byte sent to the CS42428, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto incre-
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS42428 after each input byte is read, and is input to the
CS42428 from the microcontroller after each transmitted byte.

4 5 6 7

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

1 0 0 1 1 AD1 AD0 0

SDA

INCR

6 5 4 3 2 1 0

7 6 1 0

0 1 2 3

8 9

16 17 18 19

10 11

13 14 15

27 28

DATA +n

Figure 18. Control Port Timing, I

C Slave Mode Write

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

1 0 0 1 1 AD1 AD0 0

SDA

1 0 0 1 1 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR

6 5 4 3 2 1 0

7 0

8 9

12 13 14 15

4 5 6 7

0 1

20 21 22 23 24

26 27 28

2 3

10 11

17 18 19

ACK

DATA + n

STOP

Figure 19. Control Port Timing, I

C Slave Mode Read

CS42428

Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10011xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10011xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.

3.7

Interrupts

The CS42428 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter-
rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active
low with no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with mul-
tiple peripherals connected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See "Interrupt
Status (address 20h) (Read Only)" on page 46. Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the op-
tion of level sensitive or edge sensitive modes within the microcontroller, many different configurations
are possible, depending on the needs of the equipment designer.

CS42428

3.8

Reset and Power-up

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies
drop below the recommended operating condition to prevent power glitch related issues.

When RST is low, the CS42428 enters a low power mode and all internal states are reset, including the
control port and registers, and the outputs are muted. When RST is high, the control port becomes opera-
tional and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the
Power Control Register will then cause the part to leave the low power state and begin operation. If the
internal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has set-
tled. See "Power Control (address 02h)" on page 33 for more details.

The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 80ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.

3.9

Power Supply, Grounding, and PCB layout

As with any high resolution converter, the CS42428 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run
from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead.
In this case, no additional devices should be powered from VD.

For applications where the output of the PLL is required to be low jitter, use a separate, low noise analog
+5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around
the FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42428 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42428 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators
and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-
mize the electrical path from FILT+ and REFGND. The CDB42418 evaluation board demonstrates the op-
timum layout and power supply arrangements.

CS42428

4 REGISTER QUICK REFERENCE

Addr

Function

01h

Chip_ID3

Chip_ID2

Chip_ID1

CHIP_ID0

Rev_ID3

Rev_ID2

Rev_ID1

Rev_ID0

default

02h

Power Control

Reserved

PDN_PLL

PDN_ADC

PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1

PDN

default

03h

Functional Mode

DAC_FM1

DAC_FM0

ADC_FM1

ADC_FM0

Reserved

ADC_CLK

SEL

DAC_DEM

Reserved

default

04h

Interface Formats

DIF1

DIF0

ADC_OL1

ADC_OL0

DAC_OL1

DAC_OL0

Reserved

CODEC_RJ16

default

05h

Misc Control

Ext ADC

SCLK

HiZ_RMCK

Reserved

FREEZE

FILTSEL

HPF_

FREEZE

DAC_SP

M/S

ADC_SP

M/S

default

06h

Clock Control

RMCK_DIV1 RMCK_DIV0

OMCK

Freq1

OMCK

Freq0

PLL_LRCK

SW_CTRL1 SW_CTRL0 FRC_PLL_LK

default

07h

OMCK/PLL_CLK
Ratio

RATIO7

RATIO6

RATIO5

RATIO4

RATIO3

RATIO2

RATIO1

RATIO0

default

08h

Clock Status

Reserved

Active_CLK

PLL_CLK2

PLL_CLK1

PLL_CLK0

default

09h-

0Ch

Reserved

default

0Dh

Volume Control

Reserved

SNGVOL

SZC1

SZC0

AMUTE

Reserved

RAMP_UP

RAMP_DN

default

0Eh

Channel Mute

B4_MUTE

A4_MUTE

B3_MUTE

A3_MUTE

B2_MUTE

A2_MUTE

B1_MUTE

A1_MUTE

default

0Fh

Vol. Control A1

A1_VOL7

A1_VOL6

A1_VOL5

A1_VOL4

A1_VOL3

A1_VOL2

A1_VOL1

A1_VOL0

default

10h

Vol. Control B1

B1_VOL7

B1_VOL6

B1_VOL5

B1_VOL4

B1_VOL3

B1_VOL2

B1_VOL1

B1_VOL0

default

11h

Vol. Control A2

A2_VOL7

A2_VOL6

A2_VOL5

A2_VOL4

A2_VOL3

A2_VOL2

A2_VOL1

A2_VOL0

default

12h

Vol. Control B2

B2_VOL7

B2_VOL6

B2_VOL5

B2_VOL4

B2_VOL3

B2_VOL2

B2_VOL1

B2_VOL0

default

13h

Vol. Control A3

A3_VOL7

A3_VOL6

A3_VOL5

A3_VOL4

A3_VOL3

A3_VOL2

A3_VOL1

A3_VOL0

default

14h

Vol. Control B3

B3_VOL7

B3_VOL6

B3_VOL5

B3_VOL4

B3_VOL3

B3_VOL2

B3_VOL1

B3_VOL0

default

15h

Vol. Control A4

A4_VOL7

A4_VOL6

A4_VOL5

A4_VOL4

A4_VOL3

A4_VOL2

A4_VOL1

A4_VOL0

default

16h

Vol. Control B4

B4_VOL7

B4_VOL6

B4_VOL5

B4_VOL4

B4_VOL3

B4_VOL2

B4_VOL1

B4_VOL0

default

17h

Channel Invert

INV_B4

INV_A4

INV_B3

INV_A3

INV_B2

INV_A2

INV_B1

INV_A1

default

18h

Mixing Ctrl Pair 1

P1_A=B

Reserved

P1_ATAPI4

P1_ATAPI3

P1_ATAPI2

P1_ATAPI1

P1_ATAPI0

default

CS42428

19h

Mixing Ctrl Pair 2

P2_A=B

Reserved

P2_ATAPI4

P2_ATAPI3

P2_ATAPI2

P2_ATAPI1

P2_ATAPI0

default

1Ah

Mixing Ctrl Pair 3

P3_A=B

Reserved

P3_ATAPI4

P3_ATAPI3

P3_ATAPI2

P3_ATAPI1

P3_ATAPI0

default

1Bh

Mixing Ctrl Pair 4

P4_A=B

Reserved

P4_ATAPI4

P4_ATAPI3

P4_ATAPI2

P4_ATAPI1

P4_ATAPI0

default

1Ch

ADC Left Ch.
Gain

Reserved

LGAIN5

LGAIN4

LGAIN3

LGAIN2

LGAIN1

LGAIN0

default

1Dh

ADC Right Ch.
Gain

Reserved

RGAIN5

RGAIN4

RGAIN3

RGAIN2

RGAIN1

RGAIN0

default

1Eh

Interrupt Control

SP_SYNC

Reserved

DE-EMPH1

DE-EMPH0

INT1

INT0

Reserved

default

1Fh

Reserved

default

20h

Interrupt Status

UNLOCK

Reserved

OverFlow

Reserved

default

21h

Interrupt Mask

UNLOCKM

Reserved

OverFlowM

Reserved

default

22h

Interrupt Mode
MSB

UNLOCK1

Reserved

OF1

Reserved

default

23h

Interrupt Mode
LSB

UNLOCK0

Reserved

OF0

Reserved

default

24h-

27h

Reserved

default

28h

MUTEC

Reserved

MCPolarity

M_AOUTA1 M_AOUTB1 M_AOUTA2

M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4
M_AOUTB4

default

29h

GPO7

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Ah

GPO6

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Bh

GPO5

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Ch

GPO4

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Dh

GPO3

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Eh

GPO2

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

2Fh

GPO1

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

default

Addr

Function

CS42428

5.3

Power Control (address 02h)

5.3.1

POWER DOWN PLL (PDN_PLL)

Default = 0

Function:

When enabled, the PLL will remain in a reset state. It is advised that any change of this bit be made
while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audi-
ble artifacts.

5.3.2

POWER DOWN ADC (PDN_ADC)

Default = 0

Function:

When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.

5.3.3

POWER DOWN DAC PAIRS (PDN_DACX)

Default = 0

Function:

When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.

5.3.4

POWER DOWN (PDN)

Default = 1

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power down bit defaults to `enabled' on power-up and
must be disabled before normal operation can occur.

5.4

Functional Mode (address 03h)

5.4.1

DAC FUNCTIONAL MODE (DAC_FMX)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:

Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP).
Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave mode.

Reserved

PDN_PLL

PDN_ADC

PDN_DAC4

PDN_DAC3

PDN_DAC2

PDN_DAC1

PDN

DAC_FM1

DAC_FM0

ADC_FM1

ADC_FM0

Reserved

ADC_SP SEL

DAC_DEM

Reserved

CS42428

5.4.2

ADC FUNCTIONAL MODE (ADC_FMX)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:

Selects the required range of sample rates for the ADC serial port(ADC_SP). These bits must be set
to the corresponding sample rate range when the ADC_SP is in Master or Slave mode.

5.4.3

ADC CLOCK SOURCE SELECT (ADC_CLK SEL)

Default = 0

0 - ADC_SDOUT clocked from the DAC_SP.
1 - ADC_SDOUT clocked from the ADC_SP.
Function:

Selects the desired clocks for the ADC serial output.

5.4.4

DAC DE-EMPHASIS CONTROL (DAC_DEM)

Default = 0

Function:

Enables the digital filter to maintain the standard 15

µs/50 µs digital de-emphasis filter response at

the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regard-
less of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a `1'b, then the
auto-detect sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-
EMPH bits in the Interrupt Control (address 1Eh) register to set the appropriate sample rate.

5.5

Interface Formats (address 04h)

5.5.1

DIGITAL INTERFACE FORMAT (DIFX)

Default = 01

Function:

These bits select the digital interface format used for the ADC & DAC Serial Port when not in one_line
mode. The required relationship between the Left/Right clock, serial clock and serial data is defined by
the Digital Interface Format and the options are detailed in Figures 7 - 9.

DAC_DEM

reg03h[1]

FRC_PLL_LK

reg06h[0]

DE-EMPH[1:0]

reg1Eh[5:4]

De-Emphasis

Mode

No De-Emphasis

Auto-Detect Fs

00
01
10
11

Reserved

32 kHz

44.1 kHz

48 kHz

Table 6. DAC De-Emphasis

DIF1

DIF0

ADC_OL1

ADC_OL0

DAC_OL1

DAC_OL0

Reserved

CODEC_RJ16

CS42428

5.5.2

ADC ONE_LINE MODE (ADC_OLX)

Default = 00

Function:

These bits select which mode the ADC will use. By default one-line mode is disabled but can be se-
lected using these bits. Please see Figures 10 and 11 to see the format of one-line mode 1 and
one-line mode 2.

5.5.3

DAC ONE_LINE MODE (DAC_OLX)

Default = 00

Function:

These bits select which mode the DAC will use. By default one-line mode is disabled but can be se-
lected using these bits. Please see Figures 10 and 11 to see the format of one-line mode 1 and
one-line mode 2.

5.5.4

CODEC RIGHT JUSTIFIED BITS (CODEC_RJ16)

Default = 0

Function:

This bit determines how many bits to use during right justified mode for the DAC and ADC. By default
the DAC and ADC will be in RJ24 bits but can be set to RJ16 bits.

0 - 24 bit mode.
1 - 16 bit mode.

DIF1

DIF0

Description

Format

Figure

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit or 24-bit data

reserved

Table 7. Digital Interface Formats

ADC_OL1

ADC_OL2

Description

Format

Figure

DIF: take the DIF setting from reg04h[7:6]

One-Line #1

One-Line #2

reserved

Table 8. ADC One_Line Mode

DAC_OL1

DAC_OL2

Description

Format

Figure

DIF: take the DIF setting from reg04h[7:6]

One-Line #1

One-Line #2

reserved

Table 9. DAC One_Line Mode

CS42428

5.6

Misc Control (address 05h)

5.6.1

EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)

Default = 0

Function:

This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using
one line mode of operation.

0 - ADC_SCLK is used as external ADC SCLK.
1 - DAC_SCLK is used as external ADC SCLK.

5.6.2

RMCK HIGH IMPEDANCE (HIZ_RMCK)

Default = 0

Function:

This bit is used to create a high impedance output on RMCK when the clock signal is not required.

5.6.3

FREEZE CONTROLS (FREEZE)

Default = 0

Function:

This function will freeze the previous output of, and allow modifications to be made, to the Volume
Control (address 0Fh-16h), Channel Invert (address 17h) and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.

5.6.4

INTERPOLATION FILTER SELECT (FILT_SEL)

Default = 0

Function:

This feature allows the user to select whether the DAC interpolation filter has a fast or slow roll off.
For filter characteristics please See "D/A Digital Filter Characteristics" on page 56.

0 - Fast roll off.
1 - Slow roll off.

5.6.5

HIGH PASS FILTER FREEZE (HPF_FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See "A/D Dig-
ital Filter Characteristics" on page 52.

Ext ADC SCLK

HiZ_RMCK

Reserved

FREEZE

FILT_SEL

HPF_FREEZE

DAC_SP

M/S

ADC_SP

M/S

CS42428

5.7.2

OMCK FREQUENCY (OMCK FREQX)

Default = 00

Function:

Sets the appropriate frequency for the supplied OMCK.

5.7.3

PLL LOCK TO LRCK (PLL_LRCK)

Default = 0
0 - Disabled
1 - Enabled

Function:

When enabled, the internal PLL of the CS42428 will lock to the LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in slave mode.

5.7.4

MASTER CLOCK SOURCE SELECT (SW_CTRLX)

Default = 01

Function:

These two bits, along with the UNLOCK bit in register "Interrupt Status (address 20h) (Read Only)"
on page 46, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, then RMCK will equal OMCK, but all internal and serial port timings are not valid.

5.7.5

FORCE PLL LOCK (FRC_PLL_LK)

Default = 0

Function:

This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on
OMCK. When set to a `1'b, the auto-detect sample frequency feature will be disabled. The OM-
CK/PLL_CLK Ratio (address 07h) (Read Only) register contents are not valid and the PLL_CLK[2:0]
bits will be set to `111'b. Use the DE-EMPH[1:0] bits to properly apply de-emphasis filtering.

OMCK Freq1 OMCK Freq0 Description

11.2896 MHz or 12.2880 MHz

16.9344 MHz or 18.4320 MHz

22.5792 MHz or 24.5760 MHz

Reserved

Table 11. OMCK Frequency Settings

SW_CTRL1 SW_CTRL0

UNLOCK

Description

Manual setting, MCLK sourced from

PLL.

Manual setting, MCLK sourced from OMCK.

0
1

Hold, keep same MCLK source.
Auto switch, MCLK sourced from OMCK.

0
1

Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.

Table 12. Master Clock Source Select

CS42428

5.8

OMCK/PLL_CLK Ratio (address 07h) (Read Only)

5.8.1

OMCK/PLL_CLK RATIO (RATIOX)

Default = sixth

Function:

This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.

5.9

Clock Status (address 08h) (Read Only)

5.9.1

SYSTEM CLOCK SELECTION (ACTIVE_CLK)

Default = x
0 - Output of PLL
1 - OMCK

Function:

This bit identifies the source of the internal system clock (MCLK).

5.9.2

PLL CLOCK FREQUENCY (PLL_CLKX)

Default = xxxh

Function:

The CS42428 will auto-detect the ratio between the OMCK and the recovered clock from the PLL,
which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can
be determined, and this information is displayed according to the following table. If the absolute fre-
quency of the PLL clock does not match one of the given frequencies, this register will display the
closest available value.

NOTE: These bits are set to `111'b when the FRC_PLL_LK bit is `1'b.

RATIO7(2

)

RATIO6(2

)

RATIO5(2

-1

)

RATIO4(2

-2

)

RATIO3(2

-3

)

RATIO2(2

-4

)

RATIO1(2

-5

)

RATIO0(2

-6

)

Reserved

Active_CLK

PLL_CLK2

PLL_CLK1

PLL_CLK0

PLL_CLK2

PLL_CLK1

PLL_CLK0

Description

8.1920 MHz

11.2896 MHz

12.288 MHz

16.3840 MHz

22.5792 MHz

24.5760 MHz

45.1584 MHz

49.1520 MHz

Table 13. PLL Clock Frequency Detection

CS42428

5.10

Volume Control (address 0Dh)

5.10.1 SINGLE VOLUME CONTROL (SNGVOL)

Default = 0

Function:

The individual channel volume levels are independently controlled by their respective Volume Control
registers when this function is disabled. When enabled, the volume on all channels is determined by
the A1 Channel Volume Control register and the other Volume Control registers are ignored.

5.10.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)

Default = 00

00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.

5.10.3 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled
1 - Enabled
Function:

Reserved

SNGVOL

SZC1

SZC0

AMUTE

MUTE ADC_SP

RAMP_UP

RAMP_DN

CS42428

The Digital-to-Analog converters of the CS42428 will mute the output following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.
Detection and muting is done independently for each channel. The quiescent voltage on the output
will be retained and the MUTEC pin will go active during the mute period. The muting function is af-
fected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).

5.10.4 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)

Default = 0

0 - Disabled
1 - Enabled
Function:

An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affect-
ed, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an im-
mediate un-mute is performed in these instances.

Note: For best results, it is recommended that this bit be used in conjunction with the RMP_DN bit.

5.10.5 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)

Default = 0

0 - Disabled
1 - Enabled
Function:

A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this
feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero Cross
bits (SZC[1:0]). When disabled, an immediate mute is performed prior to executing a filter mode or
de-emphasis mode change.

Note: For best results, it is recommended that this bit be used in conjunction with the RMP_UP bit.

5.11

Channel Mute (address 0Eh)

5.11.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)

Default = 0

0 - Disabled
1 - Enabled
Function:

The Digital-to-Analog converter outputs of the CS42428 will mute when enabled. The quiescent volt-
age on the outputs will be retained. The muting function is affected, similar to attenuation changes,
by the Soft and Zero Cross bits (SZC[1:0]).

B4_MUTE

A4_MUTE

B3_MUTE

A3_MUTE

B2_MUTE

A2_MUTE

B1_MUTE

A1_MUTE

CS42428

5.12

Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)

5.12.1 VOLUME CONTROL (XX_VOL)

Default = 0

Function:

The Digital Volume Control registers allow independent control of the signal levels in 0.5 dB incre-
ments from 0 to -127 dB. Volume settings are decoded as shown in Table 14. The volume changes
are implemented as dictated by the Soft and Zero Cross bits (SZC[1:0]). All volume settings less than
-127 dB are equivalent to enabling the MUTE bit for the given channel.

5.13

Channel Invert (address 17h)

5.13.1 INVERT SIGNAL POLARITY (INV_XX)

Default = 0

0 - Disabled
1 - Enabled
Function:

When enabled, these bits will invert the signal polarity of their respective channels.

5.14

Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh)

xx_VOL7

xx_VOL6

xx_VOL5

xx_VOL4

xx_VOL3

xx_VOL2

xx_VOL1

xx_VOL0

Binary Code

Decimal Value

Volume Setting

00000000

0 dB

00101000

-20 dB

01010000

-40 dB

01111000

120

-60 dB

10110100

180

-90 dB

Table 14. Example Digital Volume Settings

INV_B4

INV_A4

INV_B3

INV_A3

INV_B2

INV_A2

INV_B1

INV_A1

Px_A=B

Reserved

Px_ATAPI4

Px_ATAPI3

Px_ATAPI2

Px_ATAPI1

Px_ATAPI0

CS42428

5.15

ADC Left Channel Gain (address 1Ch)

5.15.1 ADC LEFT CHANNEL GAIN (LGAINX)

Default = 00h

Function:

The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two's complement, as shown
in Table 16.

5.16

ADC Right Channel Gain (address 1Dh)

5.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)

Default = 00h

Function:

The level of the right analog channel can be adjusted in 1dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15dB. Levels are decoded in two's complement, as shown in
Table 16.

5.17

Interrupt Control (address 1Eh)

5.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)

Default = 0
0 - DAC & ADC Serial Port timings not in phase
1 - DAC & ADC Serial Port timings are in phase

Function:

Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This
function will operate when both ports are running at the same sample rate or when operating at dif-
ferent sample rates.

Reserved

LGAIN5

LGAIN4

LGAIN3

LGAIN2

LGAIN1

LGAIN0

Reserved

RGAIN5

RGAIN4

RGAIN3

RGAIN2

RGAIN1

RGAIN0

Binary Code

Decimal Value

Volume Setting

001111

+15

+15 dB

001010

+10

+10 dB

000101

+5 dB

000000

0 dB

111011

-5

-5 dB

110110

-10

-10 dB

110001

-15

-15 dB

Table 16. Example ADC Input Gain Settings

SP_SYNC

Reserved

DE-EMPH1

DE-EMPH0

INT1

INT0

Reserved

CS42428

5.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)

Default = 00
00 - Reserved
01 - De-Emphasis for 32 kHz sample rate.
10 - De-Emphasis for 44.1 kHz sample rate.
11 - De-Emphasis for 48 kHz sample rate.

Function:

Used to specify which de-emphasis filter to apply when the FORCE PLL LOCK (FRC_PLL_LK) in
reg06h is enabled.

5.17.3 INTERRUPT PIN CONTROL (INTX)

Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved

Function:

Determines how the interrupt pin (INT) will indicate an interrupt condition.

5.18

Interrupt Status (address 20h) (Read Only)

For all bits in this register, a "1" means the associated interrupt condition has occurred at least once since the register
was last read. A "0" means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always
be "0" in this register.

5.18.1 PLL UNLOCK (UNLOCK)

Default = 0

Function:

PLL unlock status bit. This bit will go high if the PLL becomes unlocked.

5.18.2 ADC OVERFLOW (OVERFLOW)

Default = 0

Function:

Indicates that there is an over-range condition anywhere in the CS42428 ADC signal path.

UNLOCK

Reserved

OverFlow

Reserved

CS42428

5.19

Interrupt Mask (address 21h)

Default = 00000000

Function:

The bits of this register serve as a mask for the interrupt sources found in the register "Interrupt Status
(address 20h) (Read Only)" on page 46. If a mask bit is set to 1, the error is unmasked, meaning that
its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is
masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions
align with the corresponding bits in the Interrupt Status register.

5.20

Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)

Default = 00000000

Function:

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There
are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active
level(Active High or Low) only depends on the INT(1:0) bits located in the register "Interrupt Control
(address 1Eh)" on page 45.

00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved

5.21

MuteC Pin Control (address 28h)

5.21.1 MUTEC POLARITY SELECT (MCPOLARITY)

Default = 0
0 - Active low
1 - Active high

Function:

Determines the polarity of the MUTEC pin.

UNLOCKM

Reserved

OverFlowM

Reserved

UNLOCK1

Reserved

OF1

Reserved

UNLOCK0

Reserved

OF0

Reserved

MCPolarity

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4
M_AOUTB4

CS42428

5.21.2 CHANNEL MUTES SELECT (M_AOUTXX)

Default = 11111
0 - Channel mute is not mapped to the MUTEC pin
1 - Channel mute is mapped to the MUTEC pin

Function:

Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are
mapped, then the MUTEC pin is driven to the "active" state as defined by the POLARITY bit. These
Channel Mute Select bits are "ANDed" together in order for the MUTEC pin to go active. This means
that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, then all corresponding
channels must be muted before the MUTEC will go active.

5.22

General Purpose Pin Control (addresses 29h to 2Fh)

5.22.1 MODE CONTROL (MODEX)

Default = 00
00 - Reserved

01 - Mute Mode
10 - GPO/Overflow Mode
11 - GPO, Drive High Mode

Function:

Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the
Function bits.

GPO/Overflow Mode - The pin is configured as a general purpose output driven low or as a dedicated
ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the
left or right channel. The Functionx bits determine the operation of the pin. When configured as a GPO
with the output driven low, the driver is a CMOS driver. When configured to identify an ADC Overflow
condition, the driver is an open drain driver requiring a pull-up resistor.

GPO, Drive High Mode - The pin is configured as a general purpose output driven high.

5.22.2 POLARITY SELECT (POLARITY)

Default = 0

Function:

Mute Mode - If the pin is configured as a dedicated mute output pin, then the polarity bit determines
the polarity of the mapped pin according to the following

0 - Active low
1 - Active high

GPO/Overflow Mode - If the pin is configured as a GPO/Overflow Mode pin, the polarity bit is ignored.
It is recommended that in this mode this bit be set to 0.

GPO, Drive High Mode - If the pin is configured as a general purpose output driven high, the polarity
bit is ignored. It is recommended that in this mode this bit be set to 0.

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

CS42428

5.22.3 FUNCTIONAL CONTROL (FUNCTIONX)

Default = 00000

Function:

Mute Mode - If the pin is configured as a dedicated mute pin, then the functional bits determine which
channel mutes will be mapped to this pin according to the following table.

0 - Channel mute is not mapped to the GPOx pin
1 - Channel mute is mapped to the GPOx pin:

GPO/Overflow Mode - If the pin is configured as a GPO/Overflow Mode pin, then the Function1 and
Function0 bits determine how the output will behave according to the following table. It is recommend-
ed that in this mode the remaining functional bits be set to 0.

GPO, Drive High Mode - If the pin is configured as a general purpose output, then the functional bits
are ignored and the pin is driven high. It is recommended that in this mode all the functional bits be
set to 0.

GPOx

Reg Address

Function4

Function3

Function2

Function1

Function0

GPO7
pin 42

29h

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4
M_AOUTB4

GPO6
pin 43

2Ah

M_AOUTA1

M_AOUTB1

M_AOUTA2

M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4
M_AOUTB4

GPO5
pin 44

2Bh

M_AOUTA1

M_AOUTB1

M_AOUTA2

M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4
M_AOUTB4

GPO4
pin 45

2Ch

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3

M_AOUTB3

M_AOUTA4
M_AOUTB4

GPO3
pin 46

2Dh

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3

M_AOUTB3

M_AOUTA4
M_AOUTB4

GPO2
pin 47

2Eh

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4

M_AOUTB4

GPO1
pin 48

2Fh

M_AOUTA1

M_AOUTB1

M_AOUTA2
M_AOUTB2

M_AOUTA3
M_AOUTB3

M_AOUTA4

M_AOUTB4

Function1

Function0

GPOx

Driver Type

Drive Low

CMOS

OVFL R or L

Open Drain

CS42428

6 CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T

= 25° C.)

SPECIFIED OPERATING CONDITIONS

= 25° C; AGND=DGND=0, all voltages with respect

to ground; OMCK=12.288 MHz; Master Mode)

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR

latch-up.

2. The maximum over/under voltage is limited by the input current.

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VLS
VLC

4.75
3.13

1.8
1.8

5.0
3.3
5.0
5.0

5.25
5.25
5.25
5.25

V
V
V
V

Ambient Operating Temperature (power applied) CS42428-CQ

CS42428-DQ

-10
-40

-
-

+70
+85

°C

Parameters

Symbol

Min

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VLS
VLC

-0.3
-0.3
-0.3
-0.3

6.0
6.0
6.0
6.0

V
V
V
V

Input Current

(Note 1)

±10

Analog Input Voltage

(Note 2)

AGND-0.7

VA+0.7

Digital Input Voltage

Serial data port interface

(Note 2) Control port interface

IND-S

IND-C

-0.3
-0.3

VLS+ 0.4

VLC+ 0.4

V
V

Ambient Operating Temperature(power applied)

CS42428-CQ
CS42428-DQ

-20
-50

+85
+95

°C
°C

Storage Temperature

stg

-65

+150

°C

CS42428

ANALOG INPUT CHARACTERISTICS

= 25° C; VA = 5 V, VD = 3.3 V, Logic "0" = DGND

=AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.
Full scale input sine wave, 997 Hz.; OMCK = 12.288 MHz; Single speed Mode DAC_SCLK = 3.072 MHz; Double
Speed Mode DAC_SCLK = 6.144 MHz; Quad Speed Mode DAC_SCLK = 12.288 MHz.)

Parameter (Note 3)

Symbol

CS42428-CQ

Min Typ Max

CS42428-DQ

Min Typ Max

Unit

Single Speed Mode (Fs=48 kHz)

Dynamic Range

A-weighted

unweighted

108
105

114

111

-
-

106
103

114
111

-
-

dB
dB

Total Harmonic Distortion + Noise
(Note 4)

-1 dB

-20 dB
-60 dB

THD+N

-
-
-

-100

-91
-51

-94

-
-

-
-
-

-100

-91
-51

-92

-
-

dB
dB
dB

Double Speed Mode (Fs=96 kHz)

Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

108
105

114

111

108

-
-
-

106
103

114
111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise
(Note 4)

-1 dB

-20 dB
-60 dB

40kHz bandwidth -1 dB

THD+N

-
-
-
-

-100

-91
-51
-97

-94

-
-
-

-
-
-
-

-100

-91
-51
-97

-92

-
-
-

dB
dB
dB
dB

Quad Speed Mode (Fs=192 kHz)

Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

108
105

114

111

108

-
-
-

106
103

114
111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise
(Note 4)

-1 dB

-20 dB
-60 dB

40 kHz bandwidth -1 dB

THD+N

-
-
-
-

-100

-91
-51
-97

-94

-
-
-

-
-
-
-

-100

-91
-51
-97

-92

-
-
-

dB
dB
dB
dB

Dynamic Performance for All Modes

Interchannel Isolation

110

Interchannel Phase Deviation

0.0001

Degree

DC Accuracy

Interchannel Gain Mismatch

0.1

Gain Drift

+/-100

ppm/°C

Offset Error

HPF_FREEZE enabled

HPF_FREEZE disabled

-
-

100

-
-

100

-
-

LSB
LSB

Analog Input

Full-scale Differential Input Voltage

1.9

2.0

2.1

1.8

2.0

2.2

Vrms

Input Impedance(differential) (Note 5)

Common Mode Rejection Ratio

CMRR

VQ Nominal Voltage
Output Impedance
Maximum allowable DC current

-
-
-

2.7

0.01

-
-
-

2.7

0.01

-
-
-

CS42428

Notes: 3. Typical performance numbers are taken at 25° C. Min/Max performance numbers are guaranteed across

the specified temperature range, T

4. Referred to the typical full-scale voltage.

5. Measured between AIN+ and AIN-

A/D DIGITAL FILTER CHARACTERISTICS

Notes: 6. The filter frequency response scales precisely with Fs.

7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

FILT+ Nominal Voltage
Output Impedance
Maximum allowable DC current

-
-
-

5.0

0.01

-
-
-

5.0

0.01

-
-
-

Parameter

Symbol

Min

Typ

Max

Unit

Single Speed Mode (2 to 50 kHz sample rates)

Passband

(-0.1 dB)

(Note 6)

0.47

Passband Ripple

±0.035

Stopband (Note

0.58

Stopband Attenuation

-95

Total Group Delay (Fs = Output Sample Rate)

12/Fs

Group Delay Variation vs. Frequency

0.0

µs

Double Speed Mode (50 to 100 kHz sample rates)

Passband

(-0.1 dB)

(Note 6)

0.45

Passband Ripple

±0.035

Stopband

(Note 6)

0.68

Stopband Attenuation

-92

Total Group Delay (Fs = Output Sample Rate)

9/Fs

Group Delay Variation vs. Frequency

0.0

µs

Quad Speed Mode (100 to 192 kHz sample rates)

Passband

(-0.1 dB)

(Note 6)

0.24

Passband Ripple

±0.035

Stopband

(Note 6)

0.78

Stopband Attenuation

-97

Total Group Delay (Fs = Output Sample Rate)

5/Fs

Group Delay Variation vs. Frequency

0.0

µs

High Pass Filter Characteristics

Frequency Response

-3.0 dB
-0.13 dB

(Note 7)

-
-

Hz
Hz

Phase Deviation

@ 20 Hz

(Note 7)

Deg

Passband Ripple

Filter Setting Time

/Fs

CS42428

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency (normalized to Fs)

l
i
t
u

(

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40

0.42

0.44

0.46

0.48

0.50

0.52

0.54

0.56

0.58

0.60

Frequency (normalized to Fs)

i
t
ud

(

)

Figure 20. Single Speed Mode Stopband Rejection

Figure 21. Single Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

Frequency (normalized to Fs)

plit

ude

(

)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

Frequency (normalized to Fs)

l
i
t
u

Figure 22. Single Speed Mode Transition Band (Detail)

Figure 23. Single Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency (normalized to Fs)

plit

(

)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40

0.43

0.45

0.48

0.50

0.53

0.55

0.58

0.60

0.63

0.65

0.68

0.70

Frequency (normalized to Fs)

l
i
t
u

(

Figure 24. Double Speed Mode Stopband Rejection

Figure 25. Double Speed Mode Transition Band

CS42428

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40

0.43

0.45

0.48

0.50

0.53

0.55

Frequency (normalized to Fs)

lit

(

)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

Frequency (normalized to Fs)

l
i
t
u

(

Figure 26. Double Speed Mode Transition Band (Detail)

Figure 27. Double Speed Mode Passband Ripple

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency (normalized to Fs)

plit

ude

(

)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

Frequency (normalized to Fs)

pli

t
ude

(

)

Figure 28. Quad Speed Mode Stopband Rejection

Figure 29. Quad Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

Frequency (normalized to Fs)

l
i
t
u

(

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00

0.05

0.10

0.15

0.20

0.25

Frequency (normalized to Fs)

l
i
t
u

Figure 30. Quad Speed Mode Transition Band (Detail)

Figure 31. Quad Speed Mode Passband Ripple

CS42428

ANALOG OUTPUT CHARACTERISTICS

= 25° C; VA = 5 V, VD = 3.3 V, Logic "0" = DGND

=AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.;
Full scale output 997 Hz sine wave, Test load R

= 3 k

, C

= 30 pF; OMCK = 12.288 MHz; Single speed Mode,

DAC_SCLK = 3.072 MHz; Double Speed Mode, DAC_SCLK = 6.144 MHz; Quad Speed Mode, DAC_SCLK =
12.288 MHz.)

Notes: 8. One-half LSB of triangular PDF dither is added to data.

9. Performance limited by 16-bit quantization noise.

Parameter

Symbol

CS42428-CQ

Min Typ Max

CS42428-DQ

Min Typ Max

Unit

Dynamic performance for all modes

Dynamic Range(Note 8)

24-bit A-weighted

unweighted

16-bit A-Weighted

(Note 9) unweighted

108
105

-
-

114

111

97
94

-
-
-
-

108
105

-
-

114

111

97
94

-
-
-
-

dB
dB
dB
dB

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB
-60 dB

16-bit 0 dB

(Note 9) -20 dB

-60 dB

THD+N

-
-
-
-
-
-

-100

-91
-51
-94
-74
-34

-94

-
-
-
-

-
-
-
-
-
-

-100

-91
-51
-94
-74
-34

-94

-
-
-
-
-

dB
dB
dB
dB
dB
dB

Idle Channel Noise/Signal-to-noise
ratio

114

Interchannel Isolation (1
kHz)

Analog Output Characteristics for all modes

Full Scale Differential Output

.88VA

.92VA

.94VA .88VA

.92VA

.94VA

Vpp

Interchannel Gain Mismatch

0.1

Gain Drift

100

ppm/°C

Output Impedance

OUT

100

AC-Load Resistance

Load Capacitance

CS42428

D/A DIGITAL FILTER CHARACTERISTICS

Notes: 10. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 32 to 55) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

11. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.

Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

12. De-emphasis is available only in Single Speed Mode.

Parameter

Fast Roll-Off

Slow Roll-Off

Unit

Min Typ

Max

Min

Typ

Max

Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz

Passband (Note 10)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.4535
0.4998

0
0

-
-

0.4166
0.4998

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

+0.01

-0.01

+0.01

StopBand

0.5465

0.5834

StopBand Attenuation

(Note 11)

Group Delay

12/Fs

6.5/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.41/Fs

±0.14/Fs

De-emphasis Error (Note 12)

Fs = 32 kHz

(Relative to 1 kHz)

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-

±0.23
±0.14
±0.09

-
-
-

±0.23
±0.14
±0.09

dB
dB
dB

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz

Passband (Note 10)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.4166
0.4998

0
0

-
-

0.2083
0.4998

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

-0.01

0.01

StopBand

0.5834

.7917

StopBand Attenuation

(Note 11)

Group Delay

4.6/Fs

3.9/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.03/Fs

±0.01/Fs

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz

Passband (Note 10)

to -0.01 dB corner

to -3 dB corner

0
0

-
-

0.1046
0.4897

0
0

-
-

0.1042
0.4813

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.01

0.01

-0.01

0.01

StopBand

0.6355

0.8683

StopBand Attenuation

(Note 11)

Group Delay

4.7/Fs

4.2/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.01/Fs

CS42428

SWITCHING CHARACTERISTICS

(For CQ, T

= -10 to +70° C; For DQ, T

= -40 to +85° C;

VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C

= 30 pF)

Notes: 13. After powering up the CS42428, RST should be held low after the power supplies and clocks are settled.

14. See Table 2 on page 15 for suggested OMCK frequencies

15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.

Parameters

Symbol Min

Typ

Max

Units

RST pin Low Pulse Width (Note 13)

PLL Clock Recovery Sample Rate Range

200

kHz

RMCK output jitter

(Note 15)

200

ps RMS

RMCK output duty cycle

OMCK Duty Cycle

(Note 14)

DAC_SCLK, ADC_SCLK Duty Cycle

DAC_LRCK, ADC_LRCK Duty Cycle

Master Mode

RMCK to DAC_SCLK, ADC_SCLK active edge delay

smd

RMCK to DAC_LRCK, ADC_LRCK delay

lmd

Slave Mode

DAC_SCLK, ADC_SCLK Falling Edge to
ADC_SDOUT, ADC_SDOUT Output Valid

dpd

DAC_LRCK, ADC_LRCK Edge to MSB Valid

lrpd

DAC_SDIN Setup Time Before DAC_SCLK Rising
Edge

DAC_SDIN Hold Time After DAC_SCLK Rising Edge

DAC_SCLK, ADC_SCLK High Time

sckh

DAC_SCLK, ADC_SCLK Low Time

sckl

DAC_SCLK, ADC_SCLK rising to DAC_LRCK,
SAI_LRCK Edge

lrckd

DAC_LRCK, ADC_LRCK Edge to DAC_SCLK,
ADC_SCLK Rising

lrcks

DAC_SCLK
ADC_SCLK

(output)

RM CK

smd

lmd

DAC_LRCK
ADC_LRCK

(output)

sckh

sckl

M S B

MS B-1

tdpd

A DC _ SD OU T

DAC _S DIN x

d s

lrpd

lrcks

lrckd

DA C_ SC LK
AD C_ SC LK

(in put)

DA C_ LR CK
AD C_ LR CK

(inp ut)

Figure 56. Serial Audio Port Master Mode Timing

Figure 57. Serial Audio Port Slave Mode Timing

CS42428

SWITCHING CHARACTERISTICS - CONTROL PORT - I

C FORMAT

(For CQ, T

= -10 to +70° C; For DQ, T

= -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic

0 = DGND, Logic 1 = VLC, C

= 30 pF)

Notes: 16. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

17. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

18.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode

Parameter Symbol

Min

Max

Unit

SCL Clock Frequency

scl

100

kHz

RST Rising Edge to Start

irs

500

Bus Free Time Between Transmissions

buf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

hdst

4.0

µs

Clock Low time

low

4.7

µs

Clock High Time

high

4.0

µs

Setup Time for Repeated Start Condition

sust

4.7

µs

SDA Hold Time from SCL Falling

(Note 16)

hdd

µs

SDA Setup time to SCL Rising

sud

250

Rise Time of SCL and SDA

µs

Fall Time SCL and SDA

300

Setup Time for Stop Condition

susp

4.7

µs

Acknowledge Delay from SCL Falling

(Note 17)

ack

(Note 18)

256

---------------------

128

---------------------

------------------

buf

hdst

lo w

hdd

high

sud

Stop

St a rt

S D A

S C L

irs

R S T

hdst

t sust

t susp

Sta rt

Stop

R e p e a te d

ack

Figure 58. Control Port Timing - I

C Format

CS42428

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For CQ, T

= -10 to +70° C; For DQ, T

= -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;

Inputs: Logic 0 = DGND, Logic 1 = VLC, C

= 30 pF)

Notes: 19. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is

dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.

20. Data must be held for sufficient time to bridge the transition time of CCLK.

21. For f

sck

<1 MHz.

Parameter

Symbol Min Typ

Max

Units

CCLK Clock Frequency

(Note 19)

sck

6.0

MHz

CS High Time Between Transmissions

csh

1.0

µs

CS Falling to CCLK Edge

css

CCLK Low Time

scl

CCLK High Time

sch

CDIN to CCLK Rising Setup Time

dsu

CCLK Rising to DATA Hold Time

(Note 20)

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN

(Note 21)

100

Fall Time of CCLK and CDIN

(Note 21)

100

t r2

t f2

t dsu

t dh

t sch

t scl

CCLK

CDIN

t css

t pd

CDOUT

t csh

Figure 59. Control Port Timing - SPI Format

CS42428

DC ELECTRICAL CHARACTERISTICS

= 25° C; AGND=DGND=0, all voltages with respect

to ground; OMCK=12.288 MHz; Master Mode)

Notes: 22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on

highest FS and highest OMCK. Variance between speed modes is negligible.

23. I

measured with no external loading on the SDA pin.

24. Power down mode is defined as RST pin = Low with all clock and data lines held static.

25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure .

DIGITAL INTERFACE CHARACTERISTICS

(For CQ, T

= +25° C; For DQ, T

= -40 to +85° C)

Notes: 26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK,

ADC_SDOUT, DAC_SDIN1-4 ADCIN1/2
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST

27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.

Parameter

Symbol

Min

Typ

Max

Units

Power Supply Current

normal operation, VA=5 V

(Note 22)

VD=5 V

VD=3.3 V

Interface current, VLC=5V (Note 23)

VLS=5 V

power-down state (all supplies) (Note 24)

-
-
-
-
-
-

150
100
250
250
250

-
-
-
-
-
-

mA
mA
mA

µA

Power Consumption

(Note 22)

VA=5 V, VD=VLS=VLC=3.3 V

normal operation

power-down (Note 24)

VA=5 V, VD=VLS=VLC=5 V

normal operation

power-down (Note 24)

-
-
-
-

780

1.25

950

1.25

850

1050

mW
mW
mW
mW

Power Supply Rejection Ratio (Note 25)

(1 kHz)

(60 Hz)

PSRR

-
-

60
40

-
-

dB
dB

Parameters (Note 26)

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

Serial Port

Control Port

0.7xVLS
0.7xVLC

-
-

V
V

Low-Level Input Voltage

Serial Port

Control Port

-
-

0.2xVLS
0.2xVLC

V
V

High-Level Output Voltage at I

=2 mA

(Note 27)Serial Port

Control Port

MUTEC, GPOx

VLS-1.0
VLC-1.0

VA-1.0

-
-
-

V
V
V

Low-Level Output Voltage at I

=2 mA

(Note 27)

Serial Port, Control Port, MUTEC, GPOx

0.4

Input Leakage Current

±10

µA

Input Capacitance

MUTEC Drive Current

CS42428

7 PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

CS42428

8 REFERENCES

1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.

http://www.cirrus.com/products/papers/meas/meas.html

2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,

Version 6.0, February 1998.

3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con-

verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con-
vention of the Audio Engineering Society, September 1997.

4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P.

Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the
85th Convention of the Audio Engineering Society, November 1988.

5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Convert-

ers, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Conven-
tion of the Audio Engineering Society, October 1989.

6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono

Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineer-
ing Society, October 1989.

7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by

Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.

8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fuji-

mori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineer-
ing Society, October 1992.

9) Philips Semiconductor, The I

C-Bus Specification: Version 2.1, Jan. 2000. http://www.semiconduc-

tors.philips.com

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Document Outline

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