Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
Cirrus Logic, Inc.
http://www.cirrus.com
FEATURES
Six 24-bit A/D, Eight 24-bit D/A Converters
ADC Dynamic Range
105 dB Differential
102 dB Single-ended
DAC Dynamic Range
108 dB Differential
105 dB Single-ended
ADC/DAC THD+N
-98 dB Differential
-95 dB Single-ended
Compatible with Industry-standard Time
Division Multiplexed (TDM) Serial Interface
System Sampling Rates up to 192 kHz
Programmable ADC High-pass Filter for DC
Offset Calibration
Logarithmic Digital Volume Control
IC & SPI
TM
Host Control Port
Supports Logic Levels Between 5 V and
1.8 V
Popguard
Technology
GENERAL DESCRIPTION
The CS42448 CODEC provides six multi-bit analog-to-digi-
tal and eight multi-bit digital-to-analog Delta-sigma
converters. The CODEC is capable of operation with either
differential or single-ended inputs and outputs, in a 64-pin
LQFP package.
Six fully differential, or single-ended, inputs are available on
stereo ADC1, ADC2, and ADC3. When operating in Single-
ended Mode, an internal MUX before ADC3 allows selec-
tion from up to four single-ended inputs. Digital volume
control is provided for each ADC channel, with selectable
overflow detection.
All eight DAC channels provide digital volume control and
can operate with differential or single-ended outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42448 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
A/V receivers, DVD receivers, and automotive audio
systems.
ORDERING INFORMATION
See page 67
.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Mute
Control
External
Mute Control
Register
Configuration
Internal Voltage
Reference
Reset
PC
M o
r
T
D
M
Se
r
i
a
l
In
t
e
r
f
a
c
e
Lev
el T
r
ans
lat
o
r
Serial Audio
Input
Digital Supply =
3.3 V to 5 V
Analog Supply =
3.3 V to 5 V
Input Master
Clock
Serial Audio
Output
Multibit
Oversampling
ADC1&2
High Pass
Filter
Differential or
Single-Ended
Analog Inputs
4
Digital
Filters
4
*Optional MUX allows selection from up to 4 single-ended inputs.
Multibit
Oversampling
ADC3
High Pass
Filter
2
Digital
Filters
2
4:2*
Auxilliary Serial
Audio Input
Volume
Controls
Differential or
Single-Ended
Outputs
Digital
Filters
8
Multibit
DAC1-4 and
Analog Filters
8
Modulators
Interrupt
ADC Overflow
& Clock Error
Interrupt
Lev
el
T
r
ans
lat
o
r
I
2
C/SPI
Software Mode
Control Data
CS42448
FEB `05
DS648PP2
108 dB, 192 kHz 6-in, 8-out CODEC
2
DS648PP2
TABLE OF CONTENTS
1 PIN DESCRIPTION .................................................................................................................... 6
1.1 Digital I/O Pin Characteristics ............................................................................................ 8
2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 9
3 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 10
SPECIFIED OPERATING CONDITIONS ............................................................................... 10
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
ANALOG INPUT CHARACTERISTICS (CS42448-CQZ) ....................................................... 11
ANALOG INPUT CHARACTERISTICS (CS42448-DQZ) ....................................................... 12
ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... 13
ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ) ................................................... 14
ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ) ................................................... 16
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ................ 18
SWITCHING SPECIFICATIONS - ADC/DAC PORT .............................................................. 19
SWITCHING CHARACTERISTICS - AUX PORT................................................................... 21
SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE......................................... 22
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................... 23
DC ELECTRICAL CHARACTERISTICS................................................................................. 24
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 24
4 APPLICATIONS ....................................................................................................................... 25
4.1 Overview .......................................................................................................................... 25
4.2 Analog Inputs ................................................................................................................... 25
4.2.1 Line Level Inputs ................................................................................................. 25
4.2.2 ADC3 Analog Input ............................................................................................. 26
4.2.3 High Pass Filter and DC Offset Calibration ......................................................... 27
4.3 Analog Outputs ................................................................................................................ 27
4.3.1 Initialization ......................................................................................................... 27
4.3.2 Output Transient Control ..................................................................................... 27
4.3.3 Popguard .......................................................................................................... 29
4.3.4 Mute Control ........................................................................................................ 29
4.3.5 Line-level Outputs and Filtering .......................................................................... 29
4.3.6 Digital Volume Control ........................................................................................ 30
4.3.7 De-Emphasis Filter .............................................................................................. 30
4.4 System Clocking .............................................................................................................. 31
4.5 CODEC Digital Interface Formats .................................................................................... 31
4.5.1 IS ........................................................................................................................ 33
4.5.2 Left-Justified ........................................................................................................ 33
4.5.3 Right Justified ..................................................................................................... 33
4.5.4 OLM #1 ............................................................................................................... 33
4.5.5 OLM #2 ............................................................................................................... 34
4.5.6 TDM .................................................................................................................... 34
4.5.7 I/O Channel Allocation ........................................................................................ 35
4.6 AUX Port Digital Interface Formats .................................................................................. 36
4.6.1 IS ........................................................................................................................ 36
4.6.2 Left Justified ........................................................................................................ 36
4.7 Control Port Description and Timing ................................................................................ 37
4.7.1 SPI Mode ............................................................................................................ 37
4.7.2 I
2
C Mode ............................................................................................................. 38
4.8 Interrupts .......................................................................................................................... 39
4.9 Recommended Power-up Sequence ............................................................................... 39
4.10 Reset and Power-up ..................................................................................................... 39
4.11 Power Supply, Grounding, and PCB layout ................................................................... 40
DS648PP2
3
5 REGISTER QUICK REFERENCE ........................................................................................... 41
6 REGISTER DESCRIPTION ..................................................................................................... 43
6.1 Memory Address Pointer (MAP)....................................................................................... 43
6.2 Chip I.D. and Revision Register (address 01h) (Read Only)............................................ 43
6.3 Power Control (address 02h)............................................................................................ 44
6.4 Functional Mode (address 03h)........................................................................................ 45
6.5 Interface Formats (address 04h) ...................................................................................... 46
6.6 ADC Control & DAC De-emphasis (address 05h) ............................................................ 48
6.7 Transition Control (address 06h) ...................................................................................... 49
6.8 DAC Channel Mute (address 07h) ................................................................................... 51
6.9 AOUTX Volume Control (addresses 08h- 0Fh) ............................................................ 51
6.10 DAC Channel Invert (address 10h) ................................................................................ 52
6.11 AINX Volume Control (address 11h-16h) ....................................................................... 52
6.12 ADC Channel Invert (address 17h) ................................................................................ 52
6.13 Status Control (address 18h).......................................................................................... 53
6.14 Status (address 19h) (Read Only)................................................................................. 53
6.15 Status Mask (address 1Ah) ............................................................................................ 54
6.16 MUTEC Pin Control (address 1Bh) ................................................................................ 54
7 APPENDIX A: EXTERNAL FILTERS ...................................................................................... 55
7.1 ADC Input Filter ............................................................................................................... 55
7.1.1 Passive Input Filter ............................................................................................. 56
7.1.2 Passive Input Filter w/Attenuation ....................................................................... 56
7.2 DAC Output Filter ............................................................................................................ 58
8 APPENDIX B: ADC FILTER PLOTS ....................................................................................... 59
9 APPENDIX C: DAC FILTER PLOTS ....................................................................................... 61
10 PARAMETER DEFINITIONS ................................................................................................. 63
11 REFERENCES ....................................................................................................................... 64
12 PACKAGE INFORMATION ................................................................................................... 65
12.1 Thermal Characteristics ................................................................................................ 65
13 ORDERING INFORMATION ................................................................................................. 66
14 REVISION HISTORY ............................................................................................................. 67
4
DS648PP2
LIST OF FIGURES
Figure 1. Typical Connection Diagram ............................................................................................ 9
Figure 2. Output Test Load ........................................................................................................... 17
Figure 3. Maximum Loading.......................................................................................................... 17
Figure 4. Serial Audio Interface Slave Mode Timing ..................................................................... 19
Figure 5. TDM Serial Audio Interface Timing ................................................................................ 19
Figure 6. Serial Audio Interface Master Mode Timing ................................................................... 20
Figure 7. Serial Audio Interface Slave Mode Timing ..................................................................... 21
Figure 8. Control Port Timing - IC Format.................................................................................... 22
Figure 9. Control Port Timing - SPI Format................................................................................... 23
Figure 10. Full-Scale Input ............................................................................................................ 26
Figure 11. ADC3 Input Topology................................................................................................... 26
Figure 12. Audio Output Initialization Flow Chart .......................................................................... 28
Figure 13. Full-Scale Output ......................................................................................................... 30
Figure 14. De-Emphasis Curve ..................................................................................................... 30
Figure 15. IS Format .................................................................................................................... 33
Figure 16. Left Justified Format..................................................................................................... 33
Figure 17. Right Justified Format .................................................................................................. 33
Figure 18. One Line Mode #1 Format ........................................................................................... 33
Figure 19. One Line Mode #2 Format ........................................................................................... 34
Figure 20. TDM Format ................................................................................................................. 34
Figure 21. AUX IS Format............................................................................................................ 36
Figure 22. AUX Left Justified Format ............................................................................................ 36
Figure 23. Control Port Timing in SPI Mode.................................................................................. 37
Figure 24. Control Port Timing, IC Write ...................................................................................... 38
Figure 25. Control Port Timing, IC Read...................................................................................... 38
Figure 26. Single to Differential Active Input Filter ........................................................................ 55
Figure 27. Single-Ended Active Input Filter................................................................................... 55
Figure 28. Passive Input Filter....................................................................................................... 56
Figure 29. Passive Input Filter w/Attenuation................................................................................ 57
Figure 30. Active Analog Output Filter .......................................................................................... 58
Figure 31. Passive Analog Output Filter........................................................................................ 58
Figure 32. SSM Stopband Rejection ............................................................................................. 59
Figure 33. SSM Transition Band ................................................................................................... 59
Figure 34. SSM Transition Band (Detail)....................................................................................... 59
Figure 35. SSM Passband Ripple ................................................................................................. 59
Figure 36. DSM Stopband Rejection............................................................................................. 59
Figure 37. DSM Transition Band ................................................................................................... 59
Figure 38. DSM Transition Band (Detail) ...................................................................................... 60
Figure 39. DSM Passband Ripple ................................................................................................. 60
Figure 40. QSM Stopband Rejection............................................................................................. 60
Figure 41. QSM Transition Band................................................................................................... 60
Figure 42. QSM Transition Band (Detail) ...................................................................................... 60
Figure 43. QSM Passband Ripple................................................................................................. 60
Figure 44. SSM Stopband Rejection ............................................................................................. 61
Figure 45. SSM Transition Band ................................................................................................... 61
Figure 46. SSM Transition Band (detail) ....................................................................................... 61
Figure 47. SSM Passband Ripple ................................................................................................. 61
Figure 48. DSM Stopband Rejection............................................................................................. 61
Figure 49. DSM Transition Band ................................................................................................... 61
Figure 50. DSM Transition Band (detail) ....................................................................................... 62
Figure 51. DSM Passband Ripple ................................................................................................. 62
DS648PP2
5
Figure 52. QSM Stopband Rejection ............................................................................................ 62
Figure 53. QSM Transition Band................................................................................................... 62
Figure 54. QSM Transition Band (detail)....................................................................................... 62
Figure 55. QSM Passband Ripple................................................................................................. 62
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