Copyright
Cirrus Logic, Inc. 2004
(All Rights Reserved)
http://www.cirrus.com
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CS4344/5/6/8
10-Pin, 24-Bit, 192 kHz Stereo D/A Converter
Features
Multi-bit Delta-Sigma Modulator
24-Bit Conversion
Automatically Detects Sample Rates up to
192 kHz
105 dB Dynamic Range
-95 dB THD+N
Low Clock Jitter Sensitivity
Single +3.3 V or +5 V Power Supply
Filtered Line Level Outputs
On-Chip Digital De-emphasis
Popguard
TM
Technology
Small 10-Pin TSSOP Package
Description
The CS4344 family members are complete, stereo
digital-to-analog output systems including interpolation,
multi-bit D/A conversion and output analog filtering in a
10-pin package. The CS4344/5/6/8 support all major
audio data interface formats, and the individual devices
differ only in the supported interface format.
The CS4344 family is based on a fourth order multi-bit
delta-sigma modulator with a linear analog low-pass fil-
ter. This family also includes auto-speed mode detection
using both sample rate and master clock ratio as a meth-
od of auto-selecting sampling rates between 2 kHz and
200 kHz.
The CS4344 family contains on-chip digital de-empha-
sis, operates from a single +3.3 V or +5 V power supply,
and requires minimal support circuitry. These features
are ideal for DVD players & recorders, digital televisions,
home theater and set top box products, and automotive
audio systems.
ORDERING INFORMATION
See page 19
I
PC M
Se ria l
In te rfa c e
M u ltib it
M o d ula to r
In te rp o la tio n
Filte r
In te rn a l
V o lta g e
Re fe re n c e
Sw itc h e d
C a p a c ito r
D A C a n d
Filte r
Se ria l A u d io
In p u t
Rig h t
O u tp u t
Le ft
O u tp u t
Sw itc h e d
C a p a c ito r
D A C a n d
Filte r
D e -e m p h a sis
M u ltib it
M o d ula to r
In te rp o la tio n
Filte r
3.3 V o r 5 V
Sep `04
DS613PP2
CS4344/5/6/8
2
DS613PP2
Revision History
Release
Date
Changes
A1
SEP 2003
Initial Release
PP1
JUN 2004
Updated Minimum Voltage Condition on page 5
Updated Analog Dynamic Performance for 3.3 V operation on page 6
Updated Full Scale Output Voltage on page 6
Updated "High-Level Input Voltage" on page 8
Updated Current Consumption Specifications on page 8
Corrected specifications for "Internal SCLK Mode" on page 9
Updated VQ in "Recommended Connection Diagram" on page 11
Updated Ramp Times for "Output Transient Control" on page 15
Updated Legal Notice
PP2
Sep 2004
Update lead-free device ordering info.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this
information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This
document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights,
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for
copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does
not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER
CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SE-
CURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR-
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
CS4344/5/6/8
DS613PP2
3
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ................................................................................................................ 4
2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
SPECIFIED OPERATING CONDITIONS................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
DAC ANALOG CHARACTERISTICS ....................................................................................... 6
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .......................... 7
DIGITAL INPUT CHARACTERISTICS..................................................................................... 8
POWER AND THERMAL CHARACTERISTICS ...................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ........................................ 9
3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 11
4. APPLICATIONS ..................................................................................................................... 12
4.1 Master Clock .................................................................................................................... 12
4.2 Serial Clock ..................................................................................................................... 12
4.2.1 External Serial Clock Mode ................................................................................. 12
4.2.2 Internal Serial Clock Mode .................................................................................. 13
4.3 De-Emphasis ................................................................................................................... 14
4.4 Initialization and Power-Down ......................................................................................... 15
4.5 Output Transient Control ................................................................................................. 15
4.5.1 Power-up ............................................................................................................. 15
4.5.2 Power-down ........................................................................................................ 15
4.6 Grounding and Power Supply Decoupling ....................................................................... 17
4.7 Analog Output and Filtering ............................................................................................. 17
5. PARAMETER DEFINITIONS .................................................................................................. 18
6. ORDER INFORMATION:.................................................................................................... 19
7. FUNCTIONAL COMPATIBILITY ............................................................................................ 19
8. PACKAGE DIMENSIONS ...................................................................................................... 20
9. APPENDIX .............................................................................................................................. 21
CS4344/5/6/8
4
DS613PP2
1.PIN DESCRIPTIONS
Pin Name
# Pin Description
SDIN
1 Serial Audio Data Input (Input) - Input for two's complement serial audio data.
DEM/SCLK
2 De-Emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or
external serial clock input.
LRCK
3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ
5 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+
6 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits.
AOUTL
7 Left Channel Analog Output (Output) - The full scale analog output level is specified in the
Analog Characteristics specification table.
GND
8 Ground (Input) - ground reference.
VA
9 Analog Power (Input) - Positive power for the analog and digital sections.
AOUTR
10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the
Analog Characteristics specification table.
SDIN
AOUTR
DEM/SCLK
VA
LRCK
GND
MCLK
AOUTL
VQ
FILT+
1
2
3
4
5
6
7
8
9
10
CS4344/5/6/8
DS613PP2
5
2.CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and T
A
= 25
C.)
SPECIFIED OPERATING CONDITIONS
(AGND = 0 V; all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS
(AGND = 0 V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Parameters
Symbol Min Nom
Max
Units
DC Power Supply
VA
4.75
3.00
5.0
3.3
5.25
3.47
V
V
Specified Temperature Range
-CZZ
-DZZ
T
A
-10
-40
-
-
+70
+85
C
C
Parameters
Symbol
Min
Max
Units
DC Power Supply
VA
-0.3
6.0
V
Input Current, Any Pin Except Supplies
I
in
-
10
mA
Digital Input Voltage
V
IND
-0.3
VA+0.4
V
Ambient Operating Temperature (power applied)
T
op
-55
125
C
Storage Temperature
T
stg
-65
150
C
CS4344/5/6/8
6
DS613PP2
DAC ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz (Note 1),
Fs = 48/96/192 kHz; Test load R
L
= 3 k
, C
L
= 10 pF (see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz,
unless otherwise specified.)
Note:
1. One-half LSB of triangular PDF dither added to data.
DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
5 V Nom
3.3 V Nom
Min
Typ
Max
Min
Typ
Max
Unit
Dynamic Performance for CS4344/5/6/8-CZZ (-10 to 70C)
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
99
96
90
87
105
102
96
93
-
-
-
-
97
94
90
87
103
100
96
93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-95
-82
-42
-93
-73
-33
-89
-76
-36
-87
-67
-27
-
-
-
-
-
-
-95
-80
-40
-93
-73
-33
-89
-74
-34
-87
-67
-27
dB
dB
dB
dB
dB
dB
Dynamic Performance for CS4344-DZZ (-40 to 85C)
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
95
92
86
83
105
102
96
93
-
-
-
-
93
90
86
83
103
100
96
93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-95
-82
-42
-93
-73
-33
-85
-72
-32
-83
-63
-23
-
-
-
-
-
-
-95
-80
-40
-93
-73
-33
-85
-70
-30
-83
-63
-23
dB
dB
dB
dB
dB
dB
Parameter
Symbol
Min
Typ
Max
Unit
Interchannel Isolation
(1 kHz)
-
100
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/C
Analog Output
Full Scale Output Voltage
0.60VA
0.65VA
0.70VA
Vpp
Quiescent Voltage
V
Q
-
0.5VA
-
VDC
Max DC Current draw from an AOUT pin
I
OUTmax
-
10
-
A
Max Current draw from VQ
I
Qmax
-
100
-
A
Max AC-Load Resistance (see Figure 2 on page 8)
R
L
-
3
-
k
Max Load Capacitance (see Figure 2)
C
L
-
100
-
pF
Output Impedance
Z
OUT
-
100
-
CS4344/5/6/8
DS613PP2
7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The
filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample
rate by multiplying the given characteristic by Fs.) (See note 6)
Notes: 2. Response is clock dependent and will scale with Fs.
3. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
4. Refer to Figure 2.
5. De-emphasis is available only in Single Speed Mode.
6. Amplitude vs. Frequency plots of this data are available in "Appendix" on page 21.
Parameter
Symbol
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response
Single Speed Mode
Passband (Note 2)
to -0.05 dB corner
to -3 dB corner
0
0
-
-
.4780
.4996
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.01
-
+.08
dB
StopBand
.5465
-
-
Fs
StopBand Attenuation
(Note 3)
50
-
-
dB
Group Delay
tgd
-
10/Fs
-
s
De-emphasis Error (Note 5)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
dB
dB
dB
Combined Digital and On-chip Analog Filter Response
Double Speed Mode
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
0
0
-
-
.4650
.4982
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.05
-
+.2
dB
StopBand
.5770
-
-
Fs
StopBand Attenuation
(Note 3)
55
-
-
dB
Group Delay
tgd
-
5/Fs
-
s
Combined Digital and On-chip Analog Filter Response
Quad Speed Mode
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.397
0.476
Fs
Fs
Frequency Response 10 Hz to 20 kHz
0
-
+0.00004
dB
StopBand
0.7
-
-
Fs
StopBand Attenuation
(Note 3)
51
-
-
dB
Group Delay
tgd
-
2.5/Fs
-
s
CS4344/5/6/8
8
DS613PP2
DIGITAL INPUT CHARACTERISTICS
7. I
in
for LRCK is 20
A max.
POWER AND THERMAL CHARACTERISTICS
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.
9. Power down mode is defined when all clock and data lines are held static.
10. Valid with the recommended capacitor values on VQ and FILT+
as shown in the typical connection
diagram in Section 3.
Parameters
Symbol Min Typ
Max
Units
High-Level Input Voltage
(% of VA)
V
IH
55%
-
-
V
Low-Level Input Voltage
(% of VA)
V
IL
-
-
30%
V
Input Leakage Current
(Note 7)
I
in
-
-
10
A
Input Capacitance
-
8
-
pF
5 V Nom
3.3 V Nom
Parameters
Symbol Min
Typ
Max
Min
Typ
Max
Units
Power Supplies
Power Supply Current
normal operation
(Note 8)
power-down state (Note 9)
I
A
I
A
-
-
22
220
30
-
-
-
16
100
21
-
mA
A
Power Dissipation
normal operation
power-down state (Note 9)
-
-
110
1.1
150
-
-
-
53
0.33
69
-
mW
mW
Package Thermal Resistance
JA
-
95
-
-
95
-
C/Watt
Power Supply Rejection Ratio (Note 8)
(1 kHz)
(60 Hz)
PSRR
-
-
60
40
-
-
-
-
60
40
-
-
dB
dB
AOU Tx
AGN D
3.3 F
V
out
R
L
C
L
Figure 1. Output Test Load
100
50
75
25
2.5
5
10
15
Safe Operating
Region
C
a
p
a
c
i
t
i
v
e
L
o
a
d
-
-
C
(p
F)
L
Resistive Load -- R (k
)
L
125
3
20
Figure 2. Maximum Loading
CS4344/5/6/8
DS613PP2
9
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Notes: 11. Not all sample rates are supported for all clock ratios. See table "Common Clock Frequencies" on
page 12 for supported ratio's and frequencies.
12. In Internal SCLK Mode, the Duty Cycle must be 50%
+/- 1/2 MCLK Period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and
MCLK/LRCK ratio. (See figures 7-9)
Parameters
Symbol Min
Typ
Max
Units
MCLK Frequency
0.512
-
50
MHz
MCLK Duty Cycle
45
-
55
%
Input Sample Rate All MCLK/LRCK ratios combined
(Note 11)
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs
2
2
84
42
30
50
100
168
200
50
134
67
34
100
200
200
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
45
50
55
%
SCLK Pulse Width Low
t
sclkl
20
-
-
ns
SCLK Pulse Width High
t
sclkh
20
-
-
ns
SCLK Duty Cycle
45
50
55
%
SCLK rising to LRCK edge delay
t
slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t
slrs
20
-
-
ns
SDIN valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDIN hold time
t
sdh
20
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 12)
-
50
-
%
SCLK Period
(Note 13)
t
sclkw
-
-
ns
SCLK rising to LRCK edge
t
sclkr
-
-
s
SDIN valid to SCLK rising setup time
t
sdlrs
-
-
ns
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
t
sdh
-
-
ns
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
t
sdh
-
-
ns
109
SCLK
-----------------
tsclkw
2
------------------
109
512
(
)Fs
---------------------- 10
+
109
512
(
)Fs
---------------------- 15
+
109
384
(
)Fs
---------------------- 15
+
CS4344/5/6/8
10
DS613PP2
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 3. External Serial Mode Input Timing
S D A TA
*IN T E R N A L S C L K
L R C K
s clkw
t
sd lrs
t
s d h
t
s clk r
t
Figure 4. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4344/5/6/8.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
Figure 5. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4344/5/6/8.
N equals MCLK divided by SCLK
CS4344/5/6/8
DS613PP2
11
3.TYPICAL CONNECTION DIAGRAM
DEM/SCLK
8
Audio
Data
Processor
External Clock
MCLK
AGND
AOUTR
CS4344
CS4345
CS4346
CS4348
SDIN
LRCK
VA
AOUTL
3
1
2
4
9
0.1 F
+
1 F
7
Left Audio
Output
10
Right Audio
Output
+3.3 V to +5 V
3.3 F
10 k
C
470
+
R
+ 470
C =
4Fs(R
470)
R
ext
3.3 F
10 k
C
470
+
R
ext
ext
ext
+
0.1 F
10
F
+
*3.3
F
6
VQ
FILT+
5
Note*
Note* = This circuitry is intended for applications where the
CS4344/5/6/8 connects directly to an unbalanced output of
the design. For internal routing applications please see the
DAC analog output characteristics for loading limitations.
For best 20 kHz response
F
*10
*Popguard ramp can be adjusted by
selecting this capacitor value to be
3.3 F to give 250 ms ramp time
or 10 F to give a 420 ms ramp time.
or
Figure 6. Recommended Connection Diagram
CS4344/5/6/8
12
DS613PP2
4.APPLICATIONS
The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96,
88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input
pin (SDIN). The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN,
and the optional Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/6/8 differ
in serial data formats as shown in Figures 7-10.
4.1 Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the fre-
quency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers
are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the re-
quired MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK,
LRCK and SCLK must be synchronous.
Table 1. Common Clock Frequencies
4.2 Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both
external and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1 External Serial Clock Mode
The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are de-
tected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the
Internal Serial Clock Mode and de-emphasis filter cannot be accessed. The CS4344 family will switch
to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2
consecutive frames of LRCK. Refer to Figure 12.
LRCK
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
384x
512x
768x
1024x
1152x
32
-
-
-
-
8.1920
12.2880
-
-
32.7680 36.8640
44.1
-
-
-
-
11.2896 16.9344 22.5792 33.8680 45.1580
-
48
-
-
-
-
12.2880 18.4320 24.5760 36.8640 49.1520
-
64
-
-
8.1920
12.2880
-
-
32.7680 49.1520
-
-
88.2
-
-
11.2896 16.9344 22.5792 33.8680
-
-
-
-
96
-
-
12.2880 18.4320 24.5760 36.8640
-
-
-
-
128
8.1920
12.2880
-
-
32.7680 49.1520
-
-
-
-
176.4
11.2896 16.9344 22.5792 33.8680
-
-
-
-
-
-
192
12.2880 18.4320 24.5760 36.8640
-
-
-
-
-
-
Mode
QSM
DSM
SSM
CS4344/5/6/8
DS613PP2
13
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format.
Operation in this mode is identical to operation with an external serial clock synchronized with LRCK.
This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.
L R C K
S C L K
L e ft C h a n n e l
R ig h t C h a n n e l
S D A T A
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
M SB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I
2
S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I
2
S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I
2
S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
I
2
S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 7. CS4344 Data Format (I
2
S)
L R C K
S C L K
L e ft C h a n n e l
R ig h t C h a n n e l
S D A T A
+3 +2 +1 LS B
+5 +4
M SB -1 -2 -3 -4 -5
+3 +2 +1 LS B
+5 +4
M SB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4345 Data Format (Left Justified)
CS4344/5/6/8
14
DS613PP2
4.3 De-Emphasis
The CS4344 family includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs
equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes
in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling
edges of LRCK. This function is available only in the internal serial clock mode.
L R C K
S C L K
L e ft C h a n n e l
S D A T A
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
32 clocks
0
R ig h t C h a n n e l
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 9. CS4346 Data Format (Right Justified 24)
L R C K
S C L K
L e ft C h a n n e l
R ig h t C h a n n e l
S D A T A
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 10. CS4348 Data Format (Right Justified 16)
CS4344/5/6/8
DS613PP2
15
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in Figure 12. The CS4344 family enters
the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are re-
set, and the internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-
pass filters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK
are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period
to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Fi-
nally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp
to the quiescent voltage, VQ.
4.5 Output Transient Control
The CS4344 family uses Popguard
TM
technology to minimize the effects of output transients during power-
up and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.5.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to VQ
which is initially low. After MCLK is applied the outputs begin to ramp with VQ towards the nominal
quiescent voltage. This ramp takes approximately 250 ms with a 3.3 F cap connected to VQ (420 ms
with a 10 F connected to VQ) to complete. The gradual voltage ramping allows time for the external
DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid
LRCK and SDIN are supplied (and SCLK if used) approximately 2000 sample periods later audio out-
put begins.
4.5.2 Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before
turning off the power. In order to do this MCLK should be stopped for a period of about 250 ms for a
3.3 F cap connected to VQ (420 ms for a 10 F cap connected to VQ) before removing power. Dur-
ing this time voltage on VQ and the audio outputs discharge gradually to GND. If power is removed
before this time period has passed a transient will occur when the VA supply drops below that of VQ.
There is no minimum time for a power cycle, power may be re-applied at any time.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
CS4344/5/6/8
16
DS613PP2
USER: Apply Power
W ait State
USER: Apply LRCK
MCLK/LRCK Ratio Detection
USER: Applied SCLK
USER: Remove
LRCK
USER: change
MCLK/LRCK ratio
SCLK mode = internal
SCLK mode = external
Normal Operation
De-emphasis
available
Analog Output
is Generated
Normal Operation
De-emphasis
not available
Analog Output
is Generated
USER: change
MCLK/LRCK ratio
USER: Remove
MCLK
USER: Remove
LRCK
USER: Remove
MCLK
USER: Apply MCLK
Power-Down State
VQ and outputs low
VQ and outputs
ram p down
VQ and outputs
ramp down
VQ and outputs ramp up
USER: No SCLK
Figure 12. CS4344/5/6/8 Initialization and Power-Down Sequence
CS4344/5/6/8
DS613PP2
17
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present
on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC
outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click
or pop may be heard as the DAC output automatically goes to it's zero data state.
4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4344 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement
with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capaci-
tors should be located as close to the device package as possible with the smallest capacitors closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 13 - 20. The
recommended external analog circuitry is shown in the "Typical Connection Diagram" on page 11.
CS4344/5/6/8
18
DS613PP2
5.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
CS4344/5/6/8
DS613PP2
19
6.ORDER INFORMATION:
7.FUNCTIONAL COMPATIBILITY
CS4334-KS
CS4344-CZZ
CS4335-KS
CS4345-CZZ
CS4336-KS
CS4346-CZZ
CS4338-KS
CS4348-CZZ
CS4334-BS
CS4344-DZZ
CS4334-DS
CS4344-DZZ
Model
Temperature
Package
Serial Interface
CS4344-CZZ
-10 to +70 C
10-pin Plastic TSSOP - Lead-Free
16 to 24-bit, I2S
CS4344-DZZ
-40 to +85 C
10-pin Plastic TSSOP - Lead-Free
16 to 24-bit, I2S
CS4345-CZZ
-10 to +70 C
10-pin Plastic TSSOP - Lead-Free
16 to 24-bit, left justified
CS4346-CZZ
-10 to +70 C
10-pin Plastic TSSOP - Lead-Free
24-bit, right justified
CS4348-CZZ
-10 to +70 C
10-pin Plastic TSSOP - Lead-Free
16-bit, right justified
CS4344/5/6/8
20
DS613PP2
8.PACKAGE DIMENSIONS
Notes: 1. Reference
document: JEDEC MO-187
2. D does not include mold flash or protrusions which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.0433
--
--
1.10
A1
0
--
0.0059
0
--
0.15
A2
0.0295
--
0.0374
0.75
--
0.95
b
0.0059
--
0.0118
0.15
--
0.30
4, 5
c
0.0031
--
0.0091
0.08
--
0.23
D
--
0.1181 BSC
--
--
3.00 BSC
--
2
E
--
0.1929 BSC
--
--
4.90 BSC
--
E1
--
0.1181 BSC
--
--
3.00 BSC
--
3
e
--
0.0197 BSC
--
--
0.50 BSC
--
L
0.0157
0.0236
0.0315
0.40
0.60
0.80
L1
--
0.0374 REF
--
--
0.95 REF
--
0
--
8
0
--
8
Controlling Dimension is Millimeters
10LD TSSOP (3 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
L1
c
CS4344/5/6/8
DS613PP2
21
9.APPENDIX
Figure 13. Single Speed Stopband Rejection
Figure 14. Single Speed Transition Band
Figure 15. Single Speed Transition Band
Figure 16. Single Speed Passband Ripple
CS4344/5/6/8
22
DS613PP2
Figure 17. Double Speed Stopband Rejection
Figure 18. Double Speed Transition Band
Figure 19. Double Speed Transition Band
Figure 20. Double Speed Passband Ripple
CS4344/5/6/8
DS613PP2
23
Figure 21. Quad Speed Stopband Rejection
Figure 22. Quad Speed Transition Band
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
Amplitude (dB)
Frequency(normalized to Fs)
Figure 23. Quad Speed Transition Band
Figure 24. Quad Speed Passband Ripple
0.4
0.45
0.5
0.55
0.6
0.65
0.7
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Amplitude (dB)
Frequency(normalized to Fs)
PDF 
ZIP