Advance Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 1999

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

CS4397

24-Bit, Multi-Standard D/A Converter for Digital Audio

Features

24 Bit Conversion

Up to 192 kHz Sample Rates

120 dB Dynamic Range

-100 dB THD+N

Supports PCM, DSD and External
Interpolation filters

Advanced Dynamic-Element Matching

Low Clock Jitter Sensitivity

Digital De-emphasis for 32 kHz, 44.1 kHz and
48 kHz

External Reference Input

Description

The CS4397 is a complete high performance 24-bit
48/96/192 kHz stereo digital-to-analog conversion sys-
tem. The device includes a digital interpolation filter
followed by a oversampled multi-bit delta-sigma modula-
tor which drives dynamic-element-matching (DEM)
selection logic. The output from the DEM block controls
the input to a multi-element switched capacitor DAC/low-
pass filter, with fully-differential outputs. This multi-bit ar-
chitecture features significantly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced DEM guarantees low noise and distortion at
all signal levels.

ORDERING INFORMATION

CS4397-KS

-10° to 70° C 28-pin Plastic SOIC

CDB4397

Evaluation Board

SCLK

MCLK

LRCK

SDATA

AOUTL+

AOUTR+

SERIAL INTERFACE

AND FORMAT SELECT

INTERPOLATION

SOFT MUTE

MODULATOR

DYNAMIC

DE-EMPHASIS

SWITCHED

AOUTL-

AOUTR-

FILT+

FILTER

INTERPOLATION

FILTER

MULTI-BIT

MODULATOR

MULTI-BIT

ELEMENT

MATCHING

LOGIC

DYNAMIC

ELEMENT

MATCHING

LOGIC

CAPACITOR-DAC

AND FILTER

SWITCHED

CAPACITOR-DAC

AND FILTER

VREF

CMOUT

FILT-

VOLTAGE REFERENCE

HARDWARE MODE CONTROL

CLOCK

DIVIDER

(CONTROL PORT)

(AD0/CS)

(AD1/CDIN) (SCL/CCLK)

(SDA/CDOUT)

RESET

MUTEC MUTE

JUL `99

DS333PP1

CS4397

DS333PP1

TABLE OF CONTENTS

1.0 CHARACTERISTICS/SPECIFICATIONS ..................................................................... 4

ANALOG CHARACTERISTICS................................................................................... 4

Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz ...................... 4
Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz .................... 4
Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz ..................... 4

ANALOG CHARACTERISTICS................................................................................... 5

Power Supplies .................................................................................................... 5
Analog Output ...................................................................................................... 5
Combined Digital and On-chip Analog Filter Response - Single Speed Mode .... 6
Combined Digital and On-chip Analog Filter Response - Double Speed Mode ... 6
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode ..... 6

ANALOG CHARACTERISTICS - DSD MODE ............................................................ 7

Dynamic Performance - DSD Mode ..................................................................... 7
Analog Output - DSD Mode ................................................................................. 7
Combined Digital and On-chip Analog Filter Response - DSD Mode .................. 7

ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE .................................. 8

Dynamic Performance Mode ................................................................................ 8
Analog Output ...................................................................................................... 8
Combined Digital and On-chip Analog Filter Response - 8x Interpolator Mode ... 8

DIGITAL CHARACTERISTICS.................................................................................... 9
ABSOLUTE MAXIMUM RATINGS .............................................................................. 9
RECOMMENDED OPERATING CONDITIONS .......................................................... 9
SWITCHING CHARACTERISTICS ........................................................................... 10
DSD - SWITCHING CHARACTERISTICS ................................................................ 11
8X INTERPOLATOR - SWITCHING CHARACTERISTICS....................................... 12
SWITCHING CHARACTERISTICS - CONTROL PORT ........................................... 13

C® Mode ......................................................................................................... 13

SPI Mode ........................................................................................................... 14

2.0 TYPICAL CONNECTION DIAGRAM .......................................................................... 15
3.0 REGISTER DESCRIPTION ........................................................................................ 16

3.1 Differential DC offset calibration ........................................................................ 16
3.2 Soft Mute ........................................................................................................... 16
3.3 Mode Select ....................................................................................................... 17
3.4 Power DowN ...................................................................................................... 17

4.0 PIN DESCRIPTION - PCM MODE .............................................................................. 18
5.0 PIN DESCRIPTION - DSD MODE .............................................................................. 23
6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE .................................................... 24
7.0 APPLICATIONS .......................................................................................................... 25

7.1 Recommended Power-up Sequence ................................................................. 25

8.0 CONTROL PORT INTERFACE .................................................................................. 26

8.1 SPI Mode ........................................................................................................... 26
8.2 I

C Mode ........................................................................................................... 26

8.2 Memory Address Pointer (MAP) ....................................................................... 26

9.0 PARAMETER DEFINITIONS ...................................................................................... 33
10.0 REFERENCES .......................................................................................................... 33
11.0 PACKAGE DIMENSIONS ......................................................................................... 34

CS4397

DS333PP1

TABLE OF FIGURES

Figure 1. Serial Audio Input Timing ......................................................................... 10
Figure 2. Direct Stream Digital - Serial Audio Input Timing ..................................... 11
Figure 3. Serial Audio Input Timing ......................................................................... 12
Figure 4. I2C Control Port Timing ............................................................................ 13
Figure 5. SPI Control Port Timing ........................................................................... 14
Figure 6. Typical Connection Diagram - Hardware Mode (Control Port Mode) ....... 15
Figure 7. Control Port Timing, I

C Mode ................................................................. 27

Figure 8. Control Port Timing, SPI mode ................................................................ 27
Figure 9. Single-speed Transition Band .................................................................. 29
Figure 10.Single-speed Stopband Rejection ............................................................ 29
Figure 11.Single-speed Transition Band .................................................................. 29
Figure 12.Single-speed Frequency Response ......................................................... 29
Figure 13.Double-speed Stopband .......................................................................... 29
Figure 14.Double-speed Transition Band ................................................................. 29
Figure 15.Double-speed Transition Band ................................................................. 29
Figure 16.Double-speed Frequency Response ........................................................ 29
Figure 17.Quad-speed Stopband Rejection ............................................................. 30
Figure 18.Quad-speed Transition Band ................................................................... 30
Figure 19.Quad-speed Transition Band ................................................................... 30
Figure 20.Quad-speed Frequency Response .......................................................... 30
Figure 21.8x Interpolator Stop Band ........................................................................ 30
Figure 22.8x Interpolator Transition Band ................................................................ 30
Figure 23.8x Interpolator Transition Band ................................................................ 30
Figure 24.8x Interpolator Frequency Response ....................................................... 30
Figure 25.DSD Frequency Response ...................................................................... 31
Figure 26.DSD Transition Band ............................................................................... 31
Figure 27.DSD Transition Band ............................................................................... 31
Figure 28.De-Emphasis Curve ................................................................................. 31
Figure 29. Format 0, Left Justified ............................................................................ 32
Figure 30. Format 1, I

S .......................................................................................... 32

Figure 31. Format 2, Right Justified, 16-Bit Data ..................................................... 32
Figure 32.Format 3, Right Justified, 24-Bit Data ...................................................... 32
Figure 33. Format 4, 8x Interpolator Mode ............................................................... 32

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

"The I

C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.

CS4397

DS333PP1

1.0 CHARACTERISTICS/SPECIFICATIONS

ANALOG CHARACTERISTICS

= 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = DGND;

Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz
to 20 kHz, unless otherwise specified. Test load R

= 1 k

, C

= 10 pF)

Notes: 1. Triangular PDF dithered data.

2. Performance limited by 16-bit quantization noise.

Parameter

Symbol

Min

Typ

Max

Unit

Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz

Dynamic Range

(Note 1)

24-Bit

unweighted

A-Weighted

16-Bit

unweighted

(Note 2)

A-Weighted

TBD
TBD

-
-

117

120

95
98

-
-
-
-

dB
dB
dB
dB

Total Harmonic Distortion + Noise

(Note 1)

24-Bit

0 dB

-20 dB
-60 dB

16-Bit

0 dB

(Note 2)

-20 dB
-60 dB

THD+N

-
-
-
-
-
-

-100

-97
-57
-95
-75
-35

TBD
TBD
TBD

-
-
-

dB
dB
dB
dB
dB
dB

Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz

Dynamic Range

(Note 1)

24-Bit

unweighted

A-Weighted

40 kHz bandwidth

unweighted

16-Bit

unweighted

(Note 2)

A-Weighted

TBD
TBD
TBD

-
-

117

120

114

92
98

-
-
-
-
-

dB
dB
dB
dB
dB

Total Harmonic Distortion + Noise

(Note 1)

24-Bit

0 dB

-20 dB
-60 dB

16-Bit

0 dB

(Note 2)

-20 dB
-60 dB

THD+N

-
-
-
-
-
-

-100

-97
-57
-95
-75
-35

TBD
TBD
TBD

-
-
-

dB
dB
dB
dB
dB
dB

Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz

Dynamic Range

(Note 1)

24-Bit

unweighted

A-Weighted

40 kHz bandwidth

unweighted

16-Bit

unweighted

(Note 2)

A-Weighted

TBD
TBD
TBD

-
-

117

120

114

92
98

-
-
-
-
-

dB
dB
dB
dB
dB

Total Harmonic Distortion + Noise

(Note 1)

24-Bit

0 dB

-20 dB
-60 dB

16-Bit

0 dB

(Note 2)

-20 dB
-60 dB

THD+N

-
-
-
-
-
-

-100

-97
-57
-95
-75
-35

TBD
TBD
TBD

-
-
-

dB
dB
dB
dB
dB
dB

CS4397

DS333PP1

ANALOG CHARACTERISTICS

(Continued)

Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing

the capacitance will also increase the PSRR.

Parameter

Symbol

VD = 3 V

VD = 5 V

Unit

Power Supplies

Min

Typ

Max Min

Typ

Max

Supply Current

normal operation

VA = 5 V

normal operation

power-down state

+ I

-
-
-

TBD

TBD
TBD

-
-
-

TBD

TBD
TBD

mA
mA

Power Dissipation normal operation
VA = 5 V

power-down

-
-

TBD

0.3

TBD

-
-

TBD

0.3

TBD

mW
mW

Power Supply Rejection Ratio (1 kHz)

(Note 3)

(120 Hz)

PSRR

-
-

60
40

-
-

60
40

-
-

dB
dB

Parameter

Symbol

Min

Typ

Max

Unit

Analog Output

Full Scale Differential Output Voltage

TBD

1.4VREF

TBD

Vpp

Common Mode Voltage

0.5VREF

VDC

Interchannel Gain Mismatch

0.1

Gain Drift

100

ppm/°C

Differential DC Offset

2.0

TBD

AC-Load Resistance

Load Capacitance

100

Interchannel Isolation

(1 kHz)

CS4397

DS333PP1

ANALOG CHARACTERISTICS

(Continued)

Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (

Figures 9-28

) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs.

For Double-Speed Mode, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs.

6. Group Delay for Fs=48 kHz 37/48 kHz=770

7. De-emphasis is available only in Single Speed Mode.

Parameter

Symbol

Min

Typ

Max

Unit

Combined Digital and On-chip Analog Filter Response - Single Speed Mode

Passband

(Note 4)

to -0.1 dB corner

to -3 dB corner

-
-

0.470
0.492

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-.020

+0.015

Passband Ripple

±0.0001

StopBand

.5465

StopBand Attenuation

(Note 5)

102

Group Delay

(Note 6)

tgd

37/Fs

De-emphasis Error

(Note 7)

Fs = 32 kHz

(Relative to 1 kHz)

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-

±0.10
±0.10
±0.13

dB
dB
dB

Combined Digital and On-chip Analog Filter Response - Double Speed Mode

Passband

(Note 4)

to -0.1 dB corner

to -3 dB corner

0
0

-
-

0.448
0.486

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.017

0.035

Passband Ripple

±0.0008

StopBand

.570

StopBand Attenuation

(Note 5)

Group Delay

tgd

20/Fs

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode

Passband

(Note 4)

to -0.1 dB corner

to -3 dB corner

-
-

0.385
0.472

Fs
Fs

Frequency Response 10 Hz to 20 kHz

+0.015

Passband Ripple

±0.00065

StopBand

0.635

StopBand Attenuation

(Note 5)

Group Delay

tgd

11/Fs

CS4397

DS333PP1

ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE

= 25 °C; Logic "1" =

VD = 5 V; VA = 5V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Base Band Fs = 48 kHz, SCLK =
6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

= 1 k

, C

10 pF)

Notes: 9. Measurement Bandwidth is 6.08 to 9.6 Fs

Parameter

Symbol

Min

Typ

Max

Unit

Dynamic Performance Mode

Dynamic Range

(Note 1)

unweighted

A-Weighted

TBD
TBD

117

120

-
-

dB
dB

Total Harmonic Distortion + Noise

(Note 1)

0 dB

-20 dB
-60 dB

THD+N

-
-
-

-100

-97
-57

TBD
TBD
TBD

dB
dB
dB

Analog Output

Full Scale Differential Output Voltage

TBD

0.7VREF

TBD

Vpp

Common Mode Voltage

0.5VREF

VDC

Interchannel Gain Mismatch

0.1

Gain Drift

100

ppm/°C

Differential DC Offset

2.0

TBD

Combined Digital and On-chip Analog Filter Response - 8x Interpolator Mode

Passband

(Note 4)

to -0.1 dB corner

to -3 dB corner

-
-

2.10
3.52

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.0008

Passband Ripple

StopBand

6.08

StopBand Attenuation

(Note 9)

Group Delay

tgd

0.9/Fs

CS4397

DS333PP1

DIGITAL CHARACTERISTICS

= 25°C; VD = 3.0V - 5.25V)

ABSOLUTE MAXIMUM RATINGS

(AGND = 0 V, all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(DGND = 0V; all voltages with respect to ground)

Parameters

Symbol Min Typ

Max

Units

High-Level Input Voltage

VD = 5 V
VD = 3 V

2.0
2.0

-
-

V
V

Low-Level Input Voltage

VD = 5 V
VD = 3 V

-
-

0.8
0.8

V
V

Input Leakage Current

±10

Input Capacitance

Maximum MUTEC Drive Current

Parameter

Symbol Min

Max

Unit

DC Power Supply: Positive Analog

Positive Digital
Reference Voltage

VREF

-0.3
-0.3
-0.3

6.0
6.0

V
V
V

Input Current, Any Pin Except Supplies

±10

Digital Input Voltage

IND

-0.3

(VD)+0.4

Ambient Operating Temperature (power applied)

-55

125

°C

Storage Temperature

stg

-65

150

°C

Parameter

Symbol Min Typ

Max

Unit

DC Power Supply: Positive Digital

Positive Analog
Reference Voltage

VREF

3.0

4.75
TBD

3.3
5.0
5.0

5.25
5.25

V
V
V

Specified Temperature Range

-10

°C

CS4397

DS333PP1

SWITCHING CHARACTERISTICS

= -10 to 70°C; Logic 0 = AGND = DGND; Logic

1 = VD = 5.25 to 3.0 Volts; C

= 20 pF)

Parameter

Symbol Min Typ

Max

Unit

Input Sample Rate (Single-speed mode)

(Double-speed mode)

(Quad-speed mode)

Fs
Fs
Fs

16
50

100

-
-
-

100
200

kHz
kHz
kHz

LRCK Duty Cycle

MCLK Frequency

(Single-speed 256 Fs,

Double speed 128 Fs or Quad-speed 64 Fs)

4.096

12.8

MHz

MCLK Frequency

(Single-speed 384 Fs,

Double speed 192 Fs or Quad-speed, 96 Fs

6.144

19.2

MHz

MCLK Frequency

(Single-speed 512 Fs,

Double speed 256 Fs or Quad-speed, 128 Fs

8.192

25.6

MHz

MCLK Frequency

(Single-speed 768 Fs,

Double speed 384 Fs or Quad-speed, 192 Fs

12.288

38.4

MHz

MCLK Duty Cycle

SCLK Frequency (Single-speed mode)

(Double-speed mode)

(Quad-speed mode)

-
-
-

256×Fs
128×Fs

64×Fs

Hz
Hz
Hz

SCLK rising to LRCK edge delay

slrd

SCLK rising to LRCK edge setup time

slrs

SDATA valid to SCLK rising setup time

sdlrs

SCLK rising to SDATA hold time

sdh

slrs

slrd

sdlrs

sdh

SDATA

SCLK

LRCK

Figure 1. Serial Audio Input Timing

CS4397

DS333PP1

SWITCHING CHARACTERISTICS - CONTROL PORT

= 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, C

= 30 pF)

Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Parameter

Symbol

Min

Max

Unit

Mode

SCL Clock Frequency

scl

100

KHz

RST Rising Edge to Start

irs

500

Bus Free Time Between Transmissions

buf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

hdst

4.0

µs

Clock Low time

low

4.7

µs

Clock High Time

high

4.0

µs

Setup Time for Repeated Start Condition

sust

4.7

µs

SDA Hold Time from SCL Falling

(Note 11)

hdd

µs

SDA Setup time to SCL Rising

sud

250

Rise Time of Both SDA and SCL Lines

µs

Fall Time of Both SDA and SCL Lines

300

Setup Time for Stop Condition

susp

4.7

µs

buf

hdst

low

t r

t f

hdd

high

t sud

t sust

t susp

Stop

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 4. I

C Control Port Timing

CS4397

DS333PP1

SWITCHING CHARACTERISTICS - CONTROL PORT

= 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, C

= 30 pF)

Notes: 12. t

spi

only needed before first falling edge of CS after RST rising edge. t

spi

= 0 at all other times.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For F

SCK

< 1 MHz

Parameter

Symbol

Min

Max

Unit

SPI Mode

CCLK Clock Frequency

sclk

MHz

RST Rising Edge to CS Falling

srs

500

CCLK Edge to CS Falling

(Note 12)

spi

500

CS High Time Between Transmissions

csh

1.0

µs

CS Falling to CCLK Edge

css

CCLK Low Time

scl

CCLK High Time

sch

CDIN to CCLK Rising Setup Time

dsu

CCLK Rising to DATA Hold Time

(Note 13)

Rise Time of CCLK and CDIN

(Note 14)

100

Fall Time of CCLK and CDIN

(Note 14)

100

CCLK Falling to CDOUT valid

t r2

t f2

t dsu t dh

t sch

t scl

CCLK

t css

t csh

t spi

t srs

RST

t ov

CDIN

CDOUT

Figure 5. SPI Control Port Timing

CS4397

DS333PP1

3.0 REGISTER DESCRIPTION

3.1 DIFFERENTIAL DC OFFSET CALIBRATION

Mode Control Register (address 01h)

Access:

R/W in I

C and SPI.

Default:

0 - Disabled

Function:

Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be
automatically reset following completion of the calibration sequence.

3.2 SOFT MUTE

Mode Control Register (address 01h)

Access:

R/W in I

C and SPI.

Default:

0 - Enabled

Function:

The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go low at the completion of the ramp period.

The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE.

CAL

MUTE

PDN

CAL

MODE

Disabled : CAL complete

Enabled : CAL initiated

Table 1.

CAL

MUTE

PDN

MUTE

MODE

Enabled

Disabled

Table 2.

CS4397

DS333PP1

3.3 MODE SELECT

Mode Control Register (address 01h)

Access:

R/W in I

C and SPI.

Default:

00000

Function:

The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14. The op-
tions include:

Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 29-33

Selection of the standard 15

s/50

s digital de-emphasis filter response, Figure 28, which requires re-

configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.

Selection of the appropriate clocking mode to match the input sample rates.

Access to the Direct Stream Digital Mode

Access to the 8x Interpolation Input Mode

3.4 POWER DOWN

Mode Control Register (address 01h)

Access:

R/W in I

C and SPI.

Default:

1 - Powered Down

Function:

The analog and digital sections will be placed into a power-down mode when this function is enabled. This
bit must be cleared to resume normal operation.

CAL

MUTE

PDN

CAL

MUTE

PDN

PDN

MODE

Disabled

Enabled

Table 3.

CS4397

DS333PP1

4.0 PIN DESCRIPTION - PCM MODE

Reset - RST

Pin 1, Input
Function:

The device enters a low power mode and all internal state machines registers are reset when low. When
high, the device will be in a normal operation mode .

Digital Ground - DGND

Pins 6 and 9, Inputs
Function:

Digital ground reference.

Digital Power - VD

Pins 7 and 8, Input
Function:

Digital power supply. Typically 5.0 to 3.0 VDC.

Master Clock - MCLK

Pin 10, Input
Function:

The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample
rates and the required master clock frequencies.

RST

DESCRIPTION

Enabled

Normal operation mode

1
2
3
4
5
6
7
8
9
10
11
12

1
2

28
27
26
25
24
23
22
21
20
19
18
17

13
14

16
15

Reset

RST

VREF

Voltage Reference

See Description

M4(AD0/CS)

FILT+

Reference Filter

See Description

M3(AD1/CDIN)

FILT-

Reference Ground

See Description

M2(SCL/CCLK)

CMOUT

Common ModeS Voltage

See Description M0(SDA/CDOUT)

AOUTL-

Differential Output

Digital Ground

DGND

AOUTL+

Differential Output

Digital Power

Analog Power

Digital Power

AGND

Analog Ground

Digital Ground

DGND

AOUTR+

Differential Output

Master Clock

MCLK

AOUTR-

Differential Output

Serial Clock

SCLK

AGND

Analog Ground

Left/Right Clock

LRCK

MUTEC

Mute Control

Serial Data

SDATA

C/H

Control port/Hardware select

See Description

MUTE

Soft Mute

CS4397

DS333PP1

Serial Clock - SCLK

Pin 11, Input
Function:

Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right
clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in Figures 29-33

Left/Right Clock - LRCK

Pin 12, Input
Function:

The Left/Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 29-33

Serial Audio Data - SDATA

Pin 13, Input
Function:

Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed inin Figures 29-33

Soft Mute - MUTE

Pin 15, Input
Function:

The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-

Sample Rate

(kHz)

MCLK (MHz)

256x

384x

512x

768x

8.1920

12.2880

16.3840

24.5760

44.1

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x

192x

256x

384x

8.1920

12.2880

16.3840

24.5760

88.2

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

MCLK (MHz)

64x

96x

128x

192x

176.4

11.2896

16.9344

22.5792

33.8688

192

12.2880

18.4320

24.5760

36.8640

Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies

CS4397

DS333PP1

cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go active at the completion of the ramp period.

The converter analog outputs will mute when enabled. The bias voltage on the outputs will be retained
and MUTEC will go active during the mute period.

Control Port / Hardware Mode Select - C/H

Pin 16, Input
Function:

Determines if the device will operate in either the Hardware Mode or Control Port Mode.

Mute Control - MUTEC

Pin 17, Output
Function:

The Mute Control pin goes low during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.

Analog Ground - AGND

Pins 18 and 21, Inputs
Function:

Analog ground reference.

Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+

Pins 19, 20, 23 and 24, Outputs
Function:

The full scale differential analog output level is specified in the Analog Characteristics specifications table.

Analog Power - VA

Pin 22, Input
Function:

Power for the analog and reference circuits. Typically 5VDC.

Mute

DESCRIPTION

Enabled

Normal operation mode

C/H

DESCRIPTION

Hardware Mode Enabled

Control Port Mode Enabled

CS4397

DS333PP1

Common Mode Voltage - CMOUT

Pin 25, Output
Function:

Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from
CMOUT to analog ground, as shown in Figure 6. CMOUT has a typical source impedence of 25 k

and

any current drawn from this pin will alter device performance

Reference Ground - FILT-

Pin 26, Input
Function:

Ground reference for the internal sampling circuits. Must be connected to analog ground.

Reference Filter - FILT+

Pin 27, Output
Function:

Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current.

Voltage Reference Input- VREF

Pin 28, Input
Function:

Analog voltage reference. Typically 5VDC.

HARDWARE MODE

Mode Select - M0, M1, M2, M3, M4

Pins 2, 3, 4, 5 and 14, Inputs
Function:

The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14. The op-
tions include;

Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 29-33

Selection of the standard 15

s/50

s digital de-emphasis filter response, Figure 28, which requires re-

configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.

Selection of the appropriate clocking mode to match the input sample rates.

Access to the Direct Stream Digital Mode

Access to the 8x Interpolation Input Mode

CONTROL PORT MODE

Address Bit 0 / Chip Select - AD0 / CS

Pin 2, Input
Function:

In I

C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The

device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.

CS4397

DS333PP1

5.0 PIN DESCRIPTION - DSD MODE

Master Clock - MCLK

Pin 10, Input
Function:

The master clock frequency must be either 4x or 6x the DSD data rate for 64x oversampled DSD data
and 2x or 3x the DSD data rate for 128x oversampled DSD data, refer to Table 7.

CLKMODE

Pin 12, Input
Function:

This pin determines the allowable Master Clock to DSD data ratio as defined in Table 7.

DSD Serial Clock - DSD_SCLK

Pin 11, Input
Function:

Clocks the individual bits of the DSD audio data into the DSD_L and DSD_R pins.

Audio Data - DSD_L and DSD_R

Pins 13 and 14, Inputs
Function:

Direct Stream Digital audio data is clocked into DSD_L and DSD_R via the DSD serial clock.

CLKMODE

DSD Over-

Sampling Ratio

64x

128x

Table 7. MCLK to DSD Data Rate Clock Ratios

Refer to PCM mode

RST

VREF

Refer to PCM mode

M4(ADO/CS)

FILT+

Refer to PCM mode

M3(AD1/CDIN)

FILT-

Refer to PCM mode

M2(SCL/CCLK)

CMOUT

Refer to PCM mode

Refer to PCM mode M0(SDA/CDOUT)

AOUTL-

Refer to PCM mode

DGND

AOUTL+

Refer to PCM mode

AGND

Refer to PCM mode

DGND

AOUTR+

Refer to PCM mode

Master Clock

MCLK

AOUTR-

Refer to PCM mode

DSD Serial Clock

DSD_SCLK

AGND

Refer to PCM mode

Master Clock Mode

CLKMODE MUTEC

Refer to PCM mode

Left Channel Data

DSD_L

C/H

Refer to PCM mode

Right Channel Data

DSD_R

MUTE

Refer to PCM mode

1
2
3
4
5
6
7
8
9
10
11
12

1
2

28
27
26
25
24
23
22
21
20
19
18
17

13
14

16
15

CS4397

DS333PP1

6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE

Master Clock - MCLK

Pin 10, Input
Function:

The master clock frequency must be either 32x, 48x, 64x or 96x the input sample rate. Table 8 illustrates
the standard audio sample rates and the required master clock frequencies.

Bit Clock - BCKI

Pin 11, Input
Function:

Clocks the individual serial data bits into the DIL and DIR pins. Refer to Figure 33

Word Clock - WCKI

Pin 12, Input
Function:

The word clock determines which channel is currently being input on the serial audio data input, SDATA.
The frequency of the word clock must be at 8x the baseband sample rate. Refer to Figure 33.

Serial Audio Data - DIR and DIL

Pins 12 and 13, Inputs
Function:

Two's complement MSB-first serial data is input on these pins. The data is clocked into DIL and DIR via
the bit clock. Refer to Figure 33.

Sample Rate

(kHz)

MCLK (MHz)

32x

48x

64x

96x

32 x 8

8.1920

12.2880

16.384

24.576

44.1 x 8

11.2896

16.9344

22.579

33.869

48 x 8

12.2880

18.4320

24.576

36.864

Table 8. Common Clock Frequencies

Refer to PCM mode RST

VREF

Refer to PCM mode

Refer to PCM mode M4(AD0/CS)

FILT+

Refer to PCM mode

Refer to PCM mode M3(AD1/CDIN)

FILT-

Refer to PCM mode

Refer to PCM mode M2(SCL/CCLK)

CMOUT

Refer to PCM mode

Refer to PCM mode M0(SDA/CDOUT)

AOUTL-

Refer to PCM mode

Refer to PCM mode DGND

AOUTL+

Refer to PCM mode

Refer to PCM mode VD

Refer to PCM mode

Refer to PCM mode VD

AGND

Refer to PCM mode

Refer to PCM mode DGND

AOUTR+

Refer to PCM mode

Master Clock MCLK

AOUTR-

Refer to PCM mode

Bit Clock BCKI

AGND

Refer to PCM mode

Word Clock WCKI

MUTEC

Refer to PCM mode

Left Channel Data DIL

C/H

Refer to PCM mode

Right Channel Data DIR

MUTE

Refer to PCM mode

1
2
3
4
5
6
7
8
9
10
11
12

1
2

28
27
26
25
24
23
22
21
20
19
18
17

13
14

16
15

CS4397

DS333PP1

8.0 CONTROL PORT INTERFACE

The control port is used to load all the internal settings of the CS4397. The operation of the control port
may be completely asynchronous to the audio sample rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if no operation is required.

The control port has 2 modes: SPI and I

C, with the CS4397 operating as a slave device in both modes. If

C operation is desired, AD0/CS should be tied to VD or DGND. If the CS4397 ever detects a high to low

transition on AD0/CS after power-up, SPI mode will be selected.

8.1 SPI Mode

In SPI mode, CS is the CS4397 chip select signal, CCLK is the control port bit clock, CDIN is the input
data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data
is clocked on the rising edge of CCLK.

Figure 7 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first
7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W).
The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data
which will be placed into the register designated by the MAP.

8.2 I

C Mode

In I

C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL,

with the clock to data relationship as shown in Figure 3. There is no CS pin. Pins AD0 and AD1 form the
partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the
first byte sent to the CS4397, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the
AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If
the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to
be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the
contents of the register pointed to by the MAP will be output after the chip address.

For more information on I

C, please see "The I

C-Bus Specification: Version 2.0", listed in the References

section.

Memory Address Pointer (MAP)

INCR (Auto MAP Increment Enable)

MAP0-2 (Memory Address Pointer)

Default = `0'

Default = `001'

0 - Disabled

1 - Enabled

INCR

Reserved

MAP2

MAP1

MAP0

CS4397

DS333PP1

(DIF1)

(DIF0)

DESCRIPTION

FORMAT

FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit Data

Right Justified, 24-bit Data

Table 9. Single Speed (16 to 50 kHz) Digital Interface Format Options

(DEM1)

(DEM0)

DESCRIPTION

FIGURE

32 kHz De-Emphasis

44.1 kHz De-Emphasis

48 kHz De-Emphasis

De-Emphasis Disabled

Table 10. Single Speed (16 to 50 kHz) De-Emphasis Options

DESCRIPTION

Left Justified up to 24-bit data, Format 0

S up to 24-bit data, Format 1

Right Justified 16-bit data, Format 2

Right Justified 24-bit data, Format 3

Table 11. Double Speed (50 to 100 kHz) Sample Rate Mode Options

DESCRIPTION

Left Justified up to 24-bit data, Format 0

S up to 24-bit data, Format 1

Right Justified 16-bit data, Format 2

Right Justified 24-bit data, Format 3

Table 12. Quad (100 to 200 kHz) Sample Rate Mode Options

DESCRIPTION

(DIR)

Right Justified 20-bit data

(DIR)

Right Justified 24-bit data

Table 13. 8x Interpolated Input Mode Options

DESCRIPTION

(DSD_R)

64x Oversampled DSD

(DSD_R)

128x Oversampled DSD

Table 14. Direct Stream Digital Options

CS4397

DS333PP1

-160

-140

-120

-100

-80

-60

-40

-20

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6

Frequency (normalized to Fs)

i
t
ude

0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6

-160

-140

-120

-100

-80

-60

-40

-20

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

Frequency (normalized to Fs)

i
t
ude

Figure 9. Single-speed Transition Band

Figure 10. Single-speed Stopband Rejection

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

Frequency (normalized to Fs)

i
t
ude

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

Frequency (normalized to Fs)

i
t
ude

Figure 11. Single-speed Transition Band

Figure 12. Single-speed Frequency Response

-140

-120

-100

-80

-60

-40

-20

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

Frequency (normalized to Fs)

i
t
ude

-140

-120

-100

-80

-60

-40

-20

0.4

0.45

0.5

0.55

0.6

Frequency (normalized to Fs)

i
t
ude

Figure 13. Double-speed Stopband

Figure 14. Double-speed Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.42

0.43

0.44

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

Frequency (normalized to Fs)

i
t
ude

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

Frequency (normalized to Fs)

i
t
ude

Figure 15. Double-speed Transition Band

Figure 16. Double-speed Frequency Response

CS4397

DS333PP1

-160

-140

-120

-100

-80

-60

-40

-20

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

Frequency (normalized to Fs)

i
t
ude

-160

-140

-120

-100

-80

-60

-40

-20

0.5

0.52

0.54

0.56

0.58

0.6

0.62

0.64

0.66

0.68

0.7

Frequency (normalized to Fs)

i
t
ude

Figure 17. Quad-speed Stopband Rejection

Figure 18. Quad-speed Transition Band

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Frequency (normalized to Fs)

i
t
ude

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.35

0.37

0.39

0.41

0.43

0.45

0.47

0.49

0.51

0.53

Frequency (normalized to Fs)

i
t
ude

Figure 19. Quad-speed Transition Band

Figure 20. Quad-speed Frequency Response

Figure 21. 8x Interpolator Stop Band

Figure 22. 8x Interpolator Transition Band

-140

-120

-100

-80

-60

-40

-20

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

Frequency (normalized to Fs)

i
t
ude

.3 .4 .5 .6 .7 .8 .9 1.0

-120

-100

-80

-60

-40

-20

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

Frequency (normalized to Fs)

i
t
ude

2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4

.3 .4 .5 .6 .7 .8

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

0.2

0.3

0.4

0.5

0.6

Frequency (normalized to Fs)

i
t
ude

0 .05 .1 1.5 .2 .25 .3

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.5

0.6

0.7

0.8

0.9

1.1

1.2

Frequency (normalized to Fs)

i
t
ude

2 2.4 2.8 3.2 3.6 4.0 4.4 4.8

.25 .3 3.5 4.0 4.5 5.0 5.5 6.0

Figure 23. 8x Interpolator Transition Band

Figure 24. 8x Interpolator Frequency Response

CS4397

DS333PP1

9.0 PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

10.0 REFERENCES

1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.

Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2) CDB4397 Evaluation Board Datasheet

3) "The I

C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

Document Outline

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Document Outline

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