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1
Copyright
Cirrus Logic, Inc. 1997
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS5126
16-Bit, Stereo A/D Converter for Digital Audio
Features
l
Monolithic CMOS A/D Converter
- Inherent Sampling Architecture
- Stereo or Monaural Capability
- Serial Output
l
Monaural Sampling Rates up to 100 kHz
- 50 kHz/Channel Stereo Sampling
l
Signal-to-(Noise+Distortion): 92 dB
l
Dynamic Range: 92 dB
- 95 dB in 2X Oversampling Schemes
l
Interchannel Isolation: 90 dB
l
2's Complement or Binary Coding
l
Low Power Dissipation: 260 mW
- Power Down Mode for Portable Applications
l
Evaluation Board Available
Description
The CS5126 CMOS analog-to-digital converter is an ide-
al front-end for stereo or monaural digital audio systems.
The CS5126 can be configured to handle two channels
at up to 50 kHz sampling per channel, or it can be con-
figured to sample one channel at rates up to 100 kHz.
The CS5126 executes a successive approximation algo-
rithm using a charge redistribution architecture. On-chip
self-calibration circuitry has 18-bit resolution thus avoid-
ing any degradation in performance with low-level
signals. The charge redistribution technique also pro-
vides an inherent sampling function which avoids the
need for external sample/hold amplifiers.
Signal-to-(noise+distortion) in stereo operation is 92 dB,
and is dominated by internal broadband noise (1/2 LSB
rms). When the CS5126 is configured for 2X oversam-
pling, digital post-filtering bandlimits this white noise to
20 kHz, increasing dynamic range to 95 dB.
ORDERING INFORMATION
CS5126-KP
0 to 70 C
28-pin Plastic DIP
CS5126-KL
0 to 70 C
28-pin PLCC
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DS32F1
ANALOG CHARACTERISTICS
(T
A
= 25
C; VA+, VD+ = 5V; VA-, VD- = -5V;
Full-Scale Input Sinewave, 1kHz; f
clk
= 24.576MHz; VREF = 4.5V; Analog Source Impedance = 200
;
Stereo operation, L/R toggling at 48 kHz unless otherwise specified.)
Parameter*
Symbol
Min
Typ
Max
Units
Resolution
-
-
16
Bits
Dynamic Performance
Signal-to-(Noise plus Distortion)
VIN =
FS
(10 Hz to 20 kHz)
VIN = -20dB
(f = 20 kHz)
S/(N+D)
90
70
92
72
-
-
dB
dB
Total Harmonic Distortion
THD
-
0.001
-
%
Dynamic Range
Stereo Mode
Monaural (20 kHz BW)
DR
90
-
92
95
-
-
dB
dB
Idle Channel Noise
V
n(ic)
-
1/2
-
LSB
rms
Interchannel Isolation
(Note 1)
I
ic
88
90
-
dB
Interchannel Mismatch
M
ic
-
0.01
-
dB
dc Accuracy
Full-Scale Error
FSE
-
4
-
LSB
Bipolar Offset Error
BPO
-
4
-
LSB
Analog Input
Aperture Time
t
apt
-
30
-
ns
Aperture Jitter
t
ajt
-
100
-
ps
Input Capacitance
(Note 2)
C
in
-
200
-
pF
Power Supplies
Power Supply Current
Positive Analog
(Note 3)
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
I
A+
I
A-
I
D+
I
D-
-
-
-
-
18
-18
8
-8
23
-23
12
-12
mA
mA
mA
mA
Power Dissipation
(SLEEP High)
(Notes 3, 4)
(SLEEP Low)
P
do
P
ds
-
-
260
1
350
-
mW
mW
Power Supply Rejection
Positive Supplies
(Note 5)
Negative Supplies
PSR
-
-
84
84
-
-
dB
dB
Notes:
1. One input grounded; dc to 20kHz, Full Scale input on the other channel.
Guaranteed by characterization.
2. Applies only in the track mode. When converting or calibrating, input capacitance will typically
be 10 pF.
3. All outputs unloaded. All inputs CMOS levels.
4. Power dissipation in sleep mode applies with no master clock applied (CLKIN high or low).
5. With 300mV p-p, 1kHz ripple applied to each supply separately. A plot of typical power supply
rejection appears in the
Analog Circuit Connections
section.
* Refer to
Parameter Definitions
at the end of this data sheet.
Specifications are subject to change without notice.
CS5126
2
DS32F1
DIGITAL CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+, VD+ = 5V
10%; VA-,VD- = -5V
10%)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
V
IH
2.0
-
-
V
Low-Level Input Voltage
V
IL
-
-
0.8
V
High-Level Output Voltage
(Note 6)
V
OH
(VD+)-1.0V
-
-
V
Low-Level Output Voltage
Iout = 1.6 mA
V
OL
-
-
0.4
V
Input Leakage Current
I
in
-
-
10
A
Notes:
6. I
OUT
= -100
A. This specification guarantees that each digital output will drive one TTL load
(V
OH
= 2.4V @ I
OUT
= -40
A).
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0V, see note 7.)
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Positive Digital
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
Analog Reference Voltage
VREF
2.5
4.5
(VA+)-0.5
V
Analog Input Voltage
(Note 8)
V
AIN
-VREF
-
VREF
V
Notes:
7. All voltages with respect to ground.
8. The CS5126 can accept input voltages up to the analog supplies (VA+, VA-). It will produce an
output of all 1's for inputs above VREF and all 0's for inputs below -VREF.
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
Symbol
Min
Max
Units
DC Power Supplies:
Positive Digital
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
-0.3
0.3
-0.3
0.3
(VA+)+0.3
-6.0
6.0
-6.0
V
V
V
V
Input Current, Any Pin Except Supplies
(Note 9)
I
in
-
10
mA
Analog Input Voltage
(AIN and VREF pins)
V
INA
(VA-)-0.3
(VA+)+0.3
V
Digital Input Voltage
V
IND
-0.3
(VD+)+0.3
V
Ambient Temperature
(power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
Notes:
9. Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
CS5126
DS32F1
3
SWITCHING CHARACTERISTICS
(T
A
= 25
C; VA+, VD+ = 5V
10%; VA-, VD- = -5V
10%;
Inputs: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF)
Parameter
Symbol
Min
Typ
Max
Units
Master Clock Period
t
clk
40
-
-
ns
HOLD to SSH2 Falling
(Note 10)
t
dfsh2
-
80
-
ns
HOLD to TRKL, TRKR
SSH1 Falling
t
dfsh1
198t
clk
-
214t
clk
+50
ns
HOLD to TRKL, TRKR
SSH1, SSH2 Rising
t
drsh
-
80
-
ns
RST Pulse Width
t
rst
150
-
-
ns
RST to STBY Falling
t
drrs
-
100
-
ns
RST Rising to STBY Rising
t
cal
-
34,584,480
-
t
clk
HOLD Pulse Width
t
hold
2t
clk
+50
-
192t
clk
ns
HOLD to L/R Edge
(Note 10)
t
dhlri
-30
-
192t
clk
ns
SCLK period
t
sclk
200
-
-
ns
SCLK Pulse Width Low
t
sclkl
50
-
-
ns
SCLK Pulse Width High
t
sclkh
50
-
-
ns
SCLK Falling to SDATA Valid
t
dss
-
100
140
ns
HOLD Falling to SDATA Valid
t
dhs
-
140
200
ns
Notes: 10. SSH2 only works correctly if HOLD falling edge is within
30ns of L/R edge OR if HOLD falling edge
occurs between 30ns before HOLD rises to 192 t
clk
after HOLD falls.
TRKR (o)
TRKL (o)
HOLD (i)
SSH2 (o)
dfsh2
t
drsh
t
dfsh1
t
Control Output Timing
rst
t
cal
t
drrs
t
RST
STBY
Reset and Calibration Timing
dhlri
t
hold
t
L/R
HOLD
Channel Selection Timing
sclkl
t
sclkh
t
dss
t
SDATA
SCLK
sclk
t
Serial Data Timing
SCLK
MSB
dhs
t
HOLD
SDATA
Data Transmit Start Timing
CS5126
4
DS32F1
GENERAL DESCRIPTION
The CS5126 is a 2-channel, 100kHz A/D con-
verter designed specifically for stereo digital
audio. The device includes an inherent sam-
ple/hold and an on-chip analog switch for stereo
operation. Both left and right channels can thus
be sampled and converted at rates up to 50kHz
per channel. Alternatively, the CS5126 can be
implemented in 2X oversampling schemes for
improved dynamic range and distortion.
Output data is available in serial form with
either binary or 2's complement coding. Control
outputs are also supplied for use with an external
sample/hold amplifier to implement simultane-
ous sampling.
THEORY OF OPERATION
The CS5126 implements a standard successive
approximation algorithm using a charge-redistri-
bution architecture. Instead of the traditional re-
sistor network, the DAC is an array of binary-
weighted capacitors. When not converting, the
CS5126 tracks the analog input signal. The input
voltage is applied across each leg of the DAC
capacitor array, thus performing a voltage-to-
charge conversion.
When the conversion command is issued, the
charge is trapped on the capacitor array and the
analog input is thereafter ignored. In effect, the
entire DAC capacitor array serves as analog
memory during conversion much like a hold ca-
pacitor in a sample/hold amplifier.
The conversion consists of manipulating the bi-
nary-weighted legs of the capacitor array to the
voltage reference and analog ground. All legs
share one common node at the input to the con-
verter's comparator. This forms a binary-
weighted capacitive divider. Since the charge at
the comparator's input remains fixed, the voltage
at that point depends on the proportion of ca-
pacitance tied to VREF versus AGND. The suc-
cessive-approximation algorithm is used to find
the proportion of capacitance which will drive
the voltage to the comparator's trip point. That
binary fraction of capacitance represents the con-
verter's digital output.
Calibration
The ability of the CS5126 to convert accurately
clearly depends on the accuracy of its DAC. The
CS5126 uses an on-chip self-calibration scheme
to insure low distortion and excellent dynamic
range independent of input signal conditions.
Each binary-weighted bit capacitor actually con-
sists of several capacitors which can be manipu-
lated to adjust the overall bit weight. During
calibration, an on-chip microcontroller manipu-
lates the sub-arrays to precisely ratio the bits.
Each bit is adjusted to just balance the sum of
all less significant bits plus one dummy LSB
(for example, 16C = 8C + 4C + 2C + C + C).
The result is typical differential nonlinearity of
1/4 LSB. That is, codes typically range from
3/4 to 5/4 LSB's wide.
The CS5126 should be reset upon power-up,
thus initiating a calibration cycle which takes 1.4
seconds to complete. The CS5126 then stores its
calibration coefficients in on-chip SRAM, and
can be recalibrated at any later time.
SYSTEM DESIGN WITH THE CS5126
All timing and control inputs to the CS5126 can
be easily generated from a master system clock.
The CS5126 outputs serial data and a variety of
digital outputs which can be used to control an
external sample/hold amplifier for simultaneous
sampling. The actual circuit connections depend
on the system architecture (stereo or monaural
2X oversampling), and on the sampling charac-
teristics (simultaneous or sequential sampling
between channels).
CS5126
DS32F1
5
System Initialization
Upon power up, the CS5126 must be reset to
guarantee a consistent starting condition and in-
itially calibrate the device. Due to the CS5126's
low power dissipation and low temperature drift,
no warm-up time is required before reset to ac-
commodate any self-heating effects. However,
the voltage reference input should have stabi-
lized to within 0.25% of its final value before
RST rises to guarantee an accurate calibration.
Later, the CS5126 may be reset at any time to
initiate a single full calibration. Reset overrides
all other functions. If reset, the CS5126 will
clear and initiate a new calibration cycle mid-
conversion or midcalibration.
When RST is brought low all internal logic
clears. When it returns high a calibration cycle
begins which takes 34,584,480 master clock cy-
cles to complete (approximately 1.4 seconds
with a standard 24MHz master clock). The
CS5126's STBY output remains low throughout
the calibration sequence, and a rising transition
indicates the device is ready for normal opera-
tion.
A simple power-on reset circuit can be built us-
ing a resistor and capacitor as shown in Fig-
ure 1. The RC time constant must be long
enough to guarantee the rest of the system is
fully powered up and stable by the end of reset.
Master Clock
The CS5126 operates from an externally-sup-
plied master clock. In stereo operation, the mas-
ter clock frequency is set at 512 times the per-
channel sampling rate (256 in 2X oversampling
schemes). The CS5126 can accept master clocks
up to 24.576 MHz for 48kHz stereo sampling or
96kHz monaural oversampling.
All timing and control inputs for channel selec-
tion, sampling, and serial data transmission may
be divided down from the master clock. This
yields a completely synchronous system, avoid-
ing sampling and conversion errors due to asyn-
chronous digital noise.
CIRCUIT CONNECTIONS
Stereo Operation
Figure 2 shows the standard circuit connections
for operating the CS5126 in its stereo mode. The
HOLD, L/R, and SCLK inputs are derived from
the master clock using a binary divider string. A
24.576 MHz master clock is required for a sam-
pling rate of 48kHz per channel.
For 48kHz stereo sampling, the CS5126 must
sample and convert at a 96kHz rate to handle
both channels. The master clock is divided by
256 and applied to the HOLD input. A falling
transition on the HOLD pin places the input in
the hold mode and initiates a conversion cycle.
The HOLD input is latched internally by the
master clock, so it can return high anytime after
one master clock cycle plus 50ns.
In stereo operation the CS5126 alternately sam-
ples and converts the left and right input chan-
nels. This alternating channel selection is
achieved by dividing the HOLD input by two
(that is, dividing the master clock by 512) and
applying it to the L/R input. Upon completion of
each conversion cycle, the CS5126 automatically
returns to the track mode. The status of L/R as
CS5126
+5V
RST
R
C
Figure 1. Power-On Reset Circuit
CS5126
6
DS32F1
each conversion finishes determines which chan-
nel is acquired and tracked. The L/R input must
remain valid at least until 30ns before the next
falling transition on HOLD.
As shown in the timing diagram in Figure 3, the
CS5126 uses pipelined data transmission. That
is, data from a particular conversion transmits
during the next conversion cycle. The serial
clock input, SCLK, is derived by dividing the
master clock by 16. The MSB (most-significant-
bit) will be stable on the first rising edge of
SCLK after a falling transition on HOLD. With
a serial clock of f
clk
/16, transmission of all 16
output bits will span an entire conversion and
acquisition cycle.
STEREO MODE PERFORMANCE
As illustrated in Figure 4, the CS5126 typically
provides 92dB S/(N+D) and 0.001% THD. Un-
like conventional successive-approximation
ADC's, the CS5126's signal-to-noise and dy-
namic range are not limited by differential non-
linearities (DNL) caused by calibration errors.
Rather, the dominant noise source is broadband
thermal noise which aliases into the baseband.
This white broadband noise also appears as an
idle channel noise of 1/2 LSB (rms).
VA+
VA-
VD+
VD-
AINL
AINR
VREF
AGND
REFBUF
L/R
HOLD
SCLK
CLKIN
SDATA
DGND
+5V
-5V
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
Right Ch.
Analog In
Left Ch.
Analog In
f /256
clk
f /16
clk
f
clk
f /512
clk
1
F
+
+ 1
F
+
1
F
+ 1
F
Voltage
Reference
CS5126
10
10
200
200
Anti Alias
Filter
Anti Alias
Filter
1 nF
SLEEP
1 nF
Figure 2. Stereo Mode Connection Diagram
SCLK (i)
L/R (i)
HOLD (i)
Rch Conv.
Lch Conv.
Rch Acq.
Lch Acq.
LSB
MSB
LSB
MSB
LSB
MSB
SDATA (o)
Internal
Status
Right Channel Data
Left Channel Data
Figure 3. Stereo Mode Timing
CS5126
DS32F1
7
Differential Nonlinearity
The self-calibration scheme utilized in the
CS5126 features a calibration resolution of 1/4
LSB, or 18-bits. This ideally yields DNL of
1/4 LSB, with code widths ranging from 3/4 to
5/4 LSB's. This insures consistent sound quality
independent of signal level.
Traditional laser trimmed ADC's have signifi-
cant differential nonlinearities which are disas-
trous to sound quality with low-level signals.
Appearing as wide and narrow codes, DNL
often causes entire sections of the transfer func-
tion to be missing. Although their affect is minor
on S/(N+D) with high amplitude signals, DNL
errors dominate performance with low-level sig-
nals. For instance, a signal 80dB below full-
scale will slew past only 6 or 7 codes. Half of
those codes could be missing with a conven-
tional hybrid ADC capable of only 14-bit DNL.
The most common source of DNL errors in con-
ventional ADC's is bit weight errors. These can
arise due to accuracy limitations in factory trim
stations, thermal or physical stresses after cali-
bration, and/or drifts due to aging or temperature
variations in the field. Bit-weight errors have a
drastic effect on a converter's ac performance.
They can be analyzed as step functions superim-
posed on the input signal. Since bits (and their
errors) switch in and out throughout the transfer
curve, their effect is signal dependent. That is,
harmonic and intermodulation distortion, as well
as noise, can vary with different input condi-
tions.
Differential nonlinearities in successive-approxi-
mation ADC's also arise due to dynamic errors
in the comparator. Such errors can dominate if
the converter's throughput/sampling rate is
driven too high. The comparator will not be al-
lowed sufficient time to settle during each bit
decision in the successive-approximation algo-
b. Left Channel with 1 kHz, -80 dB Input
Figure 4. FFT Plot of CS5126 in Stereo Mode
(Left Channel with 1 kHz, Full-Scale Input)
a. Left Channel with 1 kHz, -10 dB Input
Figure 5. FFT Plots of CS5126 in Stereo Mode
Signal
Amplitude
Relative to
Full Scale
Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
24kHz
Sampling Rate: 48 kHz
Full Scale: 9V p-p
S/(N+D): 83.27 dB
1 kHz
(dc to 20 kHz)
S/(N+D): 84.06 dB
Signal
Amplitude
Relative to
Full Scale
Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
24kHz
Sampling Rate: 48 kHz
Full Scale: 9V p-p
S/(N+D): 13.70 dB
1 kHz
(dc to 20 kHz)
S/(N+D): 14.49 dB
Signal
Amplitude
Relative to
Full Scale
Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
24kHz
Sampling Rate: 48 kHz
Full Scale: 9V p-p
S/(N+D): 91.75 dB
1 kHz
(dc to 20 kHz)
S/(N+D): 92.53 dB
CS5126
8
DS32F1
rithm. The worst-case codes for dynamic errors
are the major transitions (1/2 FS; 1/4, 3/4 FS;
etc.). Since DNL effects are most critical with
low-level signals, the codes around in mid-scale,
(that is, 1/2 FS), are most important. Yet those
codes are worst-case for dynamic DNL errors!
With all linearity calibration performed on-chip
to 18-bits, the CS5126 maintains accurate bit
weights. DNL errors are dominated by residual
calibration errors of
1/4 LSB rather than dy-
namic errors in the comparator. Furthermore, all
DNL effects on S/(N+D) are buried by white
broadband noise. This yields excellent sound
quality independent of signal level.
(See Figure 5)
Sampling Distortion
Like most discrete sample/hold amplifier de-
signs, the CS5126's inherent sample/hold exhib-
its a frequency-dependent distortion due to
nonideal sampling of the analog input voltage.
The calibrated capacitor array used during con-
versions is also used to track and hold the ana-
log input signal. The conversion is not per-
formed on the analog input voltage per se, but is
actually performed on the charge trapped on the
capacitor array at the moment the HOLD com-
mand is given. The charge on the array ideally
assumes a linear relationship to the analog input
voltage. Any deviation from this linear relation-
ship will result in conversion errors even if the
conversion process proceeds flawlessly.
At dc, the DAC capacitor array's voltage coeffi-
cient dictates the converter's linearity. This vari-
ation in capacitance with respect to applied sig-
nal voltage yields a nonlinear relationship be-
tween the charge on the array and the analog in-
put voltage and places a bow or wave in the
transfer function. This is the dominant source of
distortion at low input frequencies (Figure 4).
The ideal relationship between the charge on the
array and the input voltage can also be distorted
at high signal frequencies due to nonlinearities
in the internal MOS switches. Dynamic signals
cause ac current to flow through the switches
connecting the capacitor array to the analog in-
put pin in the track mode. Nonlinear on-resis-
tance in the switches causes a nonlinear voltage
drop. This effect worsens with increased signal
frequency and slew rate as shown in Figure 6
since the magnitude of the steady state current
increases. First noticeable at 1kHz, this distor-
tion assumes a linear relationship with input fre-
quency. With signals 20dB or more below full-
scale, it no longer dominates the converter's
overall S/(N+D) performance.
This distortion is strictly an ac sampling phe-
nomenon. If significant energy exists at high fre-
quencies, the effect can be eliminated using an
external track-and-hold amplifier to allow the ar-
ray's charge current to decay, thereby eliminat-
ing any voltage drop across the switches. Since
the CS5126 has a second sampling function on-
chip, the external track-and-hold can return to
the track mode once the converter's HOLD input
falls. It need only acquire the analog input by
the time the entire conversion cycle finishes.
Analog Input Frequency
5kHz
10kHz
15kHz
20kHz
25kHz
T
HD (
%
)
0.020
0.012
0.008
0.004
0
0.016
Figure 6. THD vs Input Frequency
( 9V p-p Full-Scale Input)
CS5126
DS32F1
9
Simultaneous Sampling
The CS5126 offers four digital output signals,
SSH1, SSH2, TRKL, and TRKR which can be
used to control external sample/hold amplifiers
to achieve simultaneous sampling and/or reduce
sampling distortion.
Figure 7 shows the timing relationships for
SSH1, SSH2, TRKL, and TRKR. In the stereo
configuration shown in Figure 1 the CS5126
samples the left and right channels 180
out of
phase. Simultaneous sampling between the left
and right channels can be achieved as shown in
Figure 8a using the CS5126's SSH2 output. The
external sample/hold will freeze the right chan-
nel analog signal as the CS5126 freezes the left
channel input at AINL. It will hold that signal
valid at AINR until the CS5126 begins a right
channel conversion. Once that conversion be-
gins, the sample/hold returns to the sample
mode. The acquisition time for the external sam-
ple/hold amplifier must not exceed the CS5126's
minimum conversion time of 192 master clock
cycles (7.8
s for 48kHz stereo sampling).
The CS5126's sampling distortion with high-fre-
quency, high-amplitude input signals may be im-
proved if a low distortion sample/hold amplifier
is used as shown in Figure 8a. The right channel
input at AINR will appear as dc to the CS5126
resulting in no ac current flowing through the
internal MOS switches. Sampling distortion can
likewise be improved for both channels using
the SSH1 output as shown in Figure 8b. Simi-
AINL
AINR
SSH2
S/H
a. Standard Connections
AINL
AINR
SSH1
S/H
S/H
b. High-Slew Conditions
Figure 8. Simultaneous Sampling Connections
Lch Acq.
Rch Acq.
Rch Convert
Lch Acq.
Lch Convert
Rch Convert
SSH1 (o)
SSH2 (o)
TRKL (o)
TRKR (o)
Acq. & Track
Hold
Acquire & Track
Hold
Internal
Status
L/R (i)
HOLD (i)
Figure 7. External Sampling Control Output Timing
CS5126
10
DS32F1
larly, the acquisition time for the external sam-
ple/hold amplifiers must not exceed the mini-
mum conversion time of 192 master clock cycles
(7.8
s for 48kHz stereo sampling).
Oversampling
The CS5126 can alternatively be used to over-
sample one channel (monaural) by 2X simply by
tying the L/R input high or low. This moves
much of the anti-alias burden from analog filters
to digital post-filtering. The analog filters' cor-
ner can be pushed out in frequency with lower
roll-off, allowing lower passband ripple and
more linear phase in the audioband. Digital FIR
filtering, meanwhile, can be used to implement
high roll-off filters with ultra-low passband rip-
ple and perfectly linear phase.
Oversampling not only improves system-level
filtering performance, but it also enhances the
ADC's dynamic range and distortion charac-
teristics. All noise energy in a sampled, digital
signal aliases into the baseband between dc and
one-half the sampling rate. For an ideal succes-
sive-approximation ADC the noise spectral con-
tent is white. Therefore, in a 2X oversampling
scheme such as 96kHz sampling the ADC's
noise will be be spread uniformly from dc to
48kHz. Digital post-filtering then rejects noise
outside of the 20kHz or 22kHz bandwidth, re-
sulting in improved signal-to-noise and dynamic
range. For a white noise spectrum, a 2X reduc-
tion in bandwidth yields a 3dB improvement in
dynamic range.
Due to its on-chip self-calibration scheme, the
CS5126's dynamic range is limited only by
white broadband noise rather than signal-depend-
ent DNL errors. Therefore, the CS5126 picks up
a full 3dB improvement in dynamic range to
95dB when implemented in 2X oversampling
schemes.
Oversampling and digital filtering also enhance
the ADC's distortion performance. Consider for
example a full-scale 15kHz input signal to the
CS5126 sampling at 96kHz. Sampling distortion
produces THD of approximately 0.005% (86dB)
at the converter's output. Most of the distortion
energy resides in the second and third harmonics
VA-
VD-
AINL*
AINR
VREF
AGND
REFBUF
+5V*
SCLK
CLKIN
SDATA
DGND
HOLD
+5V
-5V
Voltage
Reference
0.1
F
0.1
F
f /256
clk
f /16
clk
f
clk
10
Anti Alias
Filter
Analog
Input
+ 1
F
+
1
F
+ 1
F
+
1
F
1nF
10
200
CS5126
* AINR can alternatively be used
with L/R grounded
SLEEP
VD+
VA+
L/R
0.1
F
0.1
F
0.1
F
Figure 9. Monaural 2X Oversampling Connections
CS5126
DS32F1
11
at 30kHz and 45kHz. Meanwhile, digital filters
such as the SM5805 shown in Figure 10 will
roll-off rapidly from 22kHz to 28kHz and reject
distortion energy in the second, third, and fourth
harmonics. Clearly, oversampling results in su-
perior system-level distortion.
Still, if the CS5126's distortion performance
with high-frequency, high-amplitude signals
must be enhanced in 2X oversampling schemes,
the TRKL or TRKR outputs can be used. Either
TRKL or TRKR will fall at the end of each con-
version cycle depending on which channel is be-
ing acquired. The AINL and TRKL connections
(or AINR and TRKR) can be used as shown in
Figure 11 to control an external low-distortion
sample/hold to create an effective dc input for
the CS5126 and remove sampling distortion.
Digital Circuit Connections
When TTL loads are utilized the potential for
crosstalk between digital and analog sections of
the system is increased. This crosstalk is due to
high digital supply and signal currents arising
from the TTL drive current required of each
digital output. Connecting CMOS logic to the
digital outputs is recommended. Suitable logic
families include 4000B, 74HC, 74AC, 74ACT,
and 74HCT.
The CS5126 has a power down mode, initiated
by bringing SLEEP low. During power down,
the A/D Converter's calibration information is
retained. The CS5126 may be used for conver-
sion immediately after SLEEP is brought high.
AINL
TRKL
S/H
L/R
+5V
Left
Analog In
Figure 11. High-Slew Monaural Connections
Signal
Amplitude
Relative to
Full Scale
Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
48kHz
Sampling Rate: 96 kHz
Full Scale: 9V p-p
S/(N+D): 91.44 dB
1 kHz
(dc to 20 kHz)
S/(N+D): 95.25 dB
Figure 12. FFT Plot of CS5126 in Monaural 2X Over-
sampling Mode
+5V
AINL
L/R
AINL
L/R
DINL
IBO
IBCK
DINR
SM5805
Digital Filter
Left Channel
Analog In
Right Channel
Analog In
Anti Alias
Filter
Anti Alias
Filter
CS5126
CS5126
SCLK
SDATA
HOLD
SCLK
SDATA
HOLD
CLKIN
CLKIN
CKIN
OBCK
WDCK
LRCK
DOL
DATA IN
f s
512 f s
256 f s
32 f s
2 f s
System
Figure 10. Example Oversampling System Diagram
CS5126
12
DS32F1
ANALOG CIRCUIT CONNECTIONS
Most popular successive-approximation A/D
converters generate dynamic loads at their ana-
log connections. The CS5126 internally buffers
all analog inputs (AIN, VREF, and AGND) to
ease the demands placed on external circuitry.
However, accurate system operation still requires
careful attention to details at the design stage re-
garding source impedances as well as grounding
and decoupling schemes.
Reference Considerations
An application note titled "Voltage references
for the CS501X/CSZ511X Series of A/D Convert-
ers" is available which describes the dynamic
load conditions presented by the VREF input on
Crystal's self-calibrating SAR A/D converters
(including the CS5126). As the CS5126 se-
quences through bit decisions it switches por-
tions of the capacitor array to the VREF pin in
accordance with the successive-approximation
algorithm. For proper operation, the source im-
pedance at the VREF pin must remain low at
frequencies up to 1MHz.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the frequencies of interest, so the ref-
erence voltage can simply be derived as shown
in Figure 13a. Although very low cost, this ref-
erence has almost no power supply rejection
from the VA+ line.
Alternatively, a more stable and precise refer-
ence can be generated using a TL431 shunt ref-
erence from T.I. or Motorola, as shown in Fig-
ure 13b.
The magnitude of the current load on the exter-
nal reference circuitry will scale to the master
clock frequency. At the full-rated 24 MHz clock
the reference must supply a maximum load cur-
rent of 20
A peak-to-peak (2
A typical). An
output impedance of 2
will therefore yield a
maximum error of 40mV. With a 4.5V reference
and LSB size of 138mV this would insure ap-
proximately 1/4 LSB accuracy. A 10
F capaci-
tor exhibits an impedance of less than 2
at fre-
quencies greater than 16kHz. A high-quality tan-
talum capacitor in parallel with a smaller ce-
ramic capacitor is recommended.
VA+
IN4148
100
F
AGND
VREF
10 k
0.1
F
100
+
a. Simple Reference
+12 or +15 V
10
F
AGND
VREF
1.6 k
0.1
F
50
+
0.1
F
2 k
2 k
TL431
b. Low-cost Shunt Reference
Figure 13. Suggested Voltage Reference Circuits
CS5126
DS32F1
13
The CS5126 can operate with a wide range of
reference voltages, but signal-to-noise perform-
ance is maximized by using as wide a signal
range as possible. The recommended reference
voltage is 4.5 volts. The CS5126 can actually
accept reference voltages up to the positive ana-
log supply. However, as the reference voltage
approaches VA+ the external drive requirements
may increase at VREF.
An internal reference buffer is used to protect
the external reference from current transients
during conversion. This internal buffer enlists
the aid of an external 0.1
F ceramic capacitor
w h i c h m u s t b e t i e d b e t w e e n i t s o ut p u t ,
REFBUF, and the negative analog supply, VA-.
Analog Input Connection
Each time the CS5126 finishes a conversion cy-
cle it switches the internal capacitor array to the
appropriate analog input pin, AINL or AINR.
This creates a minor dynamic load at the sam-
pling frequency. All throughput specifications
apply for maximum analog source impedances
of 200
at AINL and AINR. In addition, the
comparator requires source impedances of less
than 400
around 2MHz for stability, which is
met by practically all bipolar op amps. For more
information, see our Application Note: "Input
Buffers for the CS501X/CSZ511X Series of A/D
Converters"
Analog Input Range/Coding Format
The CS5126 features a bipolar input range with
the reference voltage applied to VREF defining
both positive and negative full-scale. The coding
format is set by the state of the CODE input. If
high, coding is 2's complement; if low, the
CS5126's output is in offset-binary format.
Grounding and Power Supply Decoupling
T h e C S 5 1 2 6 u s e s t h e a n a l o g g r o u n d
connection, AGND, only as a reference voltage.
No dc power or signal currents flow through the
AGND connection, thus minimizing the potential
for interchannel crosstalk. Also, AGND is com-
pletely independent of DGND. However, any
noise riding on the AGND input relative to the
system's analog ground will induce conversion
errors. Therefore, both analog inputs and the ref-
erence voltage should be referred to the AGND
pin, which should be used as the entire system's
analog ground. The digital and analog supplies
are isolated within the CS5126 and are pinned
out separately to minimize coupling between the
analog and digital sections of the chip. All four
supplies should be decoupled to their respective
grounds using 0.1
F ceramic capacitors. If sig-
nificant low frequency noise is present on the
supplies, 1
F tantalum capacitors are recom-
mended in parallel with the 0.1
F capacitors.
The positive digital power supply of the CS5126
must never exceed the positive analog supply by
more than a diode drop or the CS5126 could
experience permanent damage. If the two sup-
plies are derived from separate sources, care
must be taken that the analog supply comes up
first at power-up. The system connection dia-
grams in figures 2 and 9 show a decoupling
scheme which allows the CS5126 to be powered
from a single set of
5V rails. The positive
digital supply is derived from the analog supply
through a 10
resistor to avoid the analog sup-
ply dropping below the digital supply. If this
scheme is utilized, care must be taken to insure
that any digital load currents (which flow
through the 10
resistors) do not cause the
magnitude of digital supplies to drop below the
analog supplies by more than 0.5 volts. Digital
CS5126
14
DS32F1
supplies must always remain above the mini-
mum specification.
As with any high-precision A/D converter, the
CS5126 requires careful attention to grounding
and layout arrangements. However, no unique
layout issues must be addressed to properly ap-
ply the CS5126. The CDB5126 evaluation board
is available for the CS5126, which avoids the
need to design, build, and debug a high-preci-
sion PC board to initially characterize the part.
The board comes with a socketed CS5126, and
can be quickly reconfigured to simulate any
combination of sampling and master clock con-
ditions.
Power Supply Rejection
The CS5126 features a fully differential compa-
rator design, resulting in superior power supply
rejection. Rejection is further enhanced by the
on-chip self-calibration and "auto-zero" process.
Figure 14 shows worst-case rejection for all
combinations of conversion rates and input con-
ditions.
Power Supply Ripple Frequency
1 kHz
10 kHz
100 kHz
1 MHz
P
o
we
r
S
u
p
p
l
y
Re
j
e
c
t
i
o
n
(
d
B)
90
80
70
60
50
40
30
20
Figure 14. Power Supply Rejection
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
CS5126
DS32F1
15
PIN DESCRIPTIONS
NEGATIVE DIGITAL POWER
VD-
SLEEP
SLEEP (LOW POWER) MODE
RESET & INITIATE CALIBRATION
RST
TST4
TEST
MASTER CLOCK INPUT
CLKIN
TST3
TEST
NO CONNECTION
NC
VA+
POSITIVE ANALOG POWER
STANDBY (CALIBRATING)
STBY
AINR
RIGHT CHANNEL ANALOG INPUT
DIGITAL GROUND
DGND
VA-
NEGATIVE ANALOG POWER
POSITIVE DIGITAL POWER
VD+
AGND
ANALOG GROUND
TRACKING LEFT CHANNEL
TRKL
REFBUF
REFERENCE BUFFER
TRACKING RIGHT CHANNEL
TRKR
VREF
VOLTAGE REFERENCE
SIMULTANEOUS SAMPLE/HOLD 1
SSH1
AINL
LEFT CHANNEL ANALOG INPUT
SIMULTANEOUS SAMPLE/HOLD 2
SSH2
TST2
TEST
HOLD & CONVERT
HOLD
TST1
TEST
LEFT/RIGHT CHANNEL SELECT
L/R
CODE
BINARY/2's COMPLEMENT SELECT
SERIAL DATA CLOCK
SCLK
SDATA
SERIAL DATA OUTPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NEGATIVE DIGITAL POWER
VD-
RESET & INITIATE CALIBRATION
RST
SLEEP
SLEEP (LOW POWER) MODE
MASTER CLOCK INPUT
CLKIN
TST4
TEST
NO CONNECTION
NC
TST3
TEST
STANDBY (CALIBRATING)
STBY
VA+
POSITIVE ANALOG POWER
DIGITAL GROUND
DGND
AINR
RIGHT CHANNEL ANALOG INPUT
POSITIVE DIGITAL POWER
VD+
VA-
NEGATIVE ANALOG POWER
TRACKING LEFT CHANNEL
TRKL
AGND
ANALOG GROUND
TRACKING RIGHT CHANNEL
TRKR
REFBUF REFERENCE BUFFER
SIMULTANEOUS SAMPLE/HOLD 1
SSH1
VREF
VOLTAGE REFERENCE
SIMULTANEOUS SAMPLE/HOLD 2
SSH2
AINL
LEFT CHANNEL ANALOG INPUT
HOLD & CONVERT
HOLD
TST2
TEST
LEFT/RIGHT CHANNEL SELECT
L/R
TST1
TEST
SERIAL DATA CLOCK
SCLK
CODE
BINARY/2's COMPLEMENT SELECT
SDATA
SERIAL DATA OUTPUT
top
view
22
20
24
19
21
23
25
3
27
2
4
26
28
1
12
14
16
18
13
15
17
8
6
10
5
7
9
11
CS5126
16
DS32F1
Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive digital power supply. Nominally +5 volts.
VD- - Negative Digital Power, PIN 1.
Negative digital power supply. Nominally -5 volts.
DGND - Digital Ground, PIN 6.
Digital ground reference.
VA+ - Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 23.
Negative analog power supply. Nominally -5 volts.
AGND - Analog Ground, PIN 22.
Analog ground reference.
Oscillator
CLKIN - Clock Input, PIN 3.
All conversions and calibrations are timed from a master clock which must be externally
supplied.
Digital Inputs
HOLD - Hold, PIN 12.
A falling transition on this pin sets the CS5126 to the hold state and initiates a conversion. This
input must remain low at least one master clock cycle plus 50ns.
L/R - Left/Right Input Channel Select, PIN 13.
Status at the end of a conversion cycle determines which analog input channel will be acquired
for the next conversion cycle.
SLEEP - Sleep, PIN 28.
When brought low causes the CS5126 to enter a low-power quiescent state. All calibration
coefficients are retained in memory, so no recalibration is needed after returning to the normal
operating mode.
CODE - 2's Complement/Binary Coding Select, PIN 16.
Determines whether data appears in 2's complement or offset-binary format. If high, 2's
complement; if low, offset-binary.
SCLK - Serial Clock, PIN 14.
Serial data changes status on a falling edge of this input, and is valid on a rising edge.
CS5126
DS32F1
17
RST - Reset, PIN 32.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration
sequence is initiated which takes 34,584,480 master clock cycles to complete.
Analog Inputs
AINL, AINR - Left and Right Channel Analog Inputs, PINS 19 and 24.
Analog input connections for the left and right input channels.
VREF - Voltage Reference, PIN 20.
The analog reference voltage which sets the analog input range. Its magnitude sets both positive
and negative full-scale.
Digital Outputs
STBY - Standby (Calibrating), PIN 5.
Indicates calibration status after reset. Remains low throughout the calibration sequence and
returns high upon completion.
SDATA - Serial Output, PIN 15.
Presents each output data bit on a falling edge of the SCLK input. Data is valid to be latched
on the rising edge of SCLK.
SSH1, SSH2 - Simultaneous Sample/Hold 1 and 2, PINS 10 and 11.
Used to control external sample/hold amplifier(s) to achieve simultaneous stereo sampling.
TRKL, TRKR - Tracking Left, Tracking Right, PINS 8 and 9.
Indicate the end of a conversion cycle. Either TRKL or TRKR falls at the end of a conversion
cycle depending on the status of L/R and which channel is to be tracked.
Analog Outputs
REFBUF - Reference Buffer Output, PIN 21.
Reference buffer output. A 0.1
F ceramic capacitor must be tied between this pin and VA-.
Miscellaneous
NC - No Connection, PIN 4.
Must be left floating for proper operation.
TST1, TST2, TST3, TST4 - Test, PINS 17, 18, 26, 27.
Allow access to the CS5126's test functions which are reserved for factory use. Must be tied to
VD+.
CS5126
18
DS32F1
PARAMETER DEFINITIONS
Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms
value of the signal. Units in percent.
Signal-to-Noise plus Distortion Ratio - The ratio of the rms value of the signal to the rms sum of all
other spectral components below the Nyquist rate (excepting dc), including distortion components. Ex-
pressed in decibels.
Dynamic Range - Full-scale Signal-to-Noise plus Distortion with the input signal 60dB below full-
scale. Units in decibels.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter's output with the input under test grounded and a full-scale signal ap-
plied to the other channel. Units in decibels.
Full Scale Error - The deviation of the last code transition from the ideal (VREF-3/2 LSB's) after all
offsets have been externally compensated. Units in decibels relative to full scale.
Bipolar Offset - The deviation of the mid-scale transition (011...111 to 100...000) from the ideal
(1/2 LSB below AGND). Units in microvolts.
Interchannel Mismatch - The difference in output codes between the left and right channels with the
same analog input applied. Units expressed in decibels relative to full scale. Tested at full scale input.
Aperture Time - The time required after the hold command for the sampling switch to open fully.
Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanosec-
onds.
Aperture Jitter - The range of variation in the aperture time. Effectively the "sampling window"
which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in
picoseconds.
CS5126
DS32F1
19
Notes
21
Copyright
Cirrus Logic, Inc. 1998
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CDB5126
Evaluation Board for CS5126
Features
l
Serial to Parallel Conversion
l
All Timing Signals Provided
l
Adjustable Voltage Reference
l
5 V Regulators
l
Digital and Analog Patch Areas
Description
The CDB5126 Evaluation Board allows fast evaluation of
the CS5126 2-Channel, 16-bit Analog-to-Digital
Converter.
Analog inputs are via BNC connectors. Digital outputs
are available both directly from the ADC in serial form,
and in 16 bit parallel form.
An adjustable monolithic voltage reference is included.
ORDERING INFORMATION
CDB5126
Evaluation Board
I
-15V
+15V
VA+
VA-
VD+
VD-
VREF
REFBUF
AINL
AINR
BP/UP
SLEEP
TEST
TEST
CODE
Clock
Generator
Sampling
Timing
Control
Serial
to
Parallel
Conversion
Serial
Clock
Switching
CLKIN
HOLD
L/R
SDATA
SCLK
TRKR
TRKL
SSH2
Digital
Patch
Area
TP
TP
TP
TP
He
a
der
HOLD
EXT
CLKIN
Mode
Select
Switches
VA-
Analog
Patch
Area
AINL
AINR
+5V Regulators
0V
AGND
VL+
+5V
0V
DGND
CS5126
SSH1
Voltage
Reference
MAR `95
DS32DB5
Power Supplies
Figure 1 shows the power supply arrangements.
The analog section of the board is powered by
15 volts, which is regulated down to
5 V for
the ADC. A separate +5 V digital supply is re-
quired to power the discrete logic. Be sure to
switch on the
15 V at the same time as, or be-
fore, the + 5 V logic supply. This will make sure
that the CLK and other logic signal are not driv-
ing the part before it is powered.
Analog Input
The analog input range is either
V
ref
in the bi-
polar mode or 0 V to +V
ref
in the unipolar mode.
The voltage reference is factory set to the recom-
mended value of +4.5 volts, so the typical input
signal ranges become
4.5 volts or 0 V to +4.5
V.
The source driving the analog inputs should have
a low (< 200
at high frequency) output imped-
ance. Be careful not to overdrive the inputs
outside the power supplies of the ADC (
5 V).
Figure 2 shows the buffer circuit used at the
Crystal factory to drive the ADC when perform-
ing FFT testing. See the CS5126 data sheet for
example FFT test results.
Voltage Reference
As shown in Figure 3, an LT1019-5 voltage ref-
erence provides a stable 4.5 V reference for the
ADC. An optional OP27 buffer filters out excess
reference noise and provides a very low output
impedance. To try the unbuffered LT1019-5 di-
rectly, solder in J2 and cut the VREF trace.
Alternatively the shunt reference based reference
schematic given in the CS5126 data sheet can be
evaluated by adding it to the analog patch area.
+15V
-15V
C22
C23
C24
C25
0.22
F
0.47
F
+5VA
-5VA
J1
+ C20
47
F
C21
+
47
F
0.22
F
79L05
OUT
COM
IN
U5
78L05
OUT
COM
U4
IN
D2
D1
0.47
F
C26
+ C27
47
F
0.1
F
D3
+15V
-15V
0V
Analog
0V
Digital
+5V
Logic
TP16
+5VL
Figure 1. Power Supplies
CDB5126
22
DS32DB5
4.99 k
In A
In B
4.99 k
1 nF C0G
ceramic
4.99 k
4.99 k
1 nF C0G
ceramic
V+
V-
50 k
1 M
121 k
Offset
ADJ
1 M
1 nF C0G
ceramic
6.81 k
V+
V-
1 nF C0G
ceramic
200
Vout
+15 V
-15 V
10
V+
V-
1
F
tantalum
35 V
10
1
F
tantalum
35 V
0.01
F
ceramic
0.01
F
ceramic
OP27
2
3
7
4
6
Notes:
1) In B and offset adjust are optional.
2) Offset adjustment range is
+ 10 mV with values shown.
Figure 2. Example Input Buffer Circuit (not provided on the CDB5126 evaluation board)
OP27
C6
0.1
F
C7
0.01
F
2
3
4
7
6
R3
22
R4
47 k
R5
1 k
+15V
-15V
C4
0.1
F
C8
16
F
+
C9
0.1
F
TP4
J2
VREF
AGND
C1
10
F
+
C2
0.1
F
R2
1 k
R1
25 k
OUT
TRIM
GND
IN
LT1019-5
U2
+15V
2
4
5
6
CW
20
22
TP1
U1
CS5126
Figure 3. Voltage Reference
CDB5126
DS32DB5
23
A 5 volt reference can be used provided the sup-
plies to the ADC are elevated to
5.3 volts. This
can be done by inserting 22
resistors in series
with the regulator (U4 and U5) common leads.
Master Clock
The CS5126 requires an external 24.576 MHz
clock for a 96 kHz sample rate. A 24.576 MHz
clock oscillator module (U6) is provided. An ex-
ternal clock can also be selected by P1, via a
BNC connector. R15 is an optional 75
termi-
nating resistor for the external clock BNC.
VA+
VD+
CLKIN
3
TP15
NC
4
TP10
J4
1
0
P1
R15
75
BNC3
EXT
CLKIN
10
R7
+5VA
+ C17
C15
1
F
0.1
F
C14
C16
+
1
F
0.1
F
12
14
13
TP13
TP12
TP11
P2
P3
1
0
BNC4
R29
75
HOLD
P4
0
1
2
R17
10 k
+5VL
R23
1 k
R16
+5VL
23
1
10
R6
+
C18
C11
C12
C19
+
-5VA
1
F
0.1
F
1
F
0.1
F
C10
0.1
F
21
24
19
TP2
TP3
VA-
VD-
REFBUF
AINR
AINL
6
2
26
15
11
10
9
8
5
28
16
17
27
18
R8, p.4
47 k
R14
10 k
SW7
C13
0.1
F
+5VL
1
2
3
4
5
47 k
TP9
TP8
TP7
TP6
TP5
TP14
6-way DIP switch
SW1 thru SW6
VREF
AGND
20
22
C9
C9
25
7
47 k
R 8
p.2
p.7
p.6
p.3
p.5
U6
U7
U8, U9 U7, Q9 Output
P8
P8
U8, pin 14
P9
SCLK
DGND
SDATA
SSH2
CODE
TST4
TST1
SLEEP
STBY
TRKL
TRKR
RST
TST
L/R
HOLD
SSH1
TST2
U1
CS5126
BNC1
AINR
BNC2
AINL
Figure 4. ADC Connections
CDB5126
24
DS32DB5
Sampling Clock Generation Logic
The CS5126 requires an external serial clock to
clock out the data. The CDB5126 board has the
logic necessary to generate the master clock,
HOLD, L/R, and SCLK to allow fast evaluation
of the ADC. In most systems, these timing sig-
nals will be available from the main timing
section, typically generated by a logic array of
some variety. HOLD may be brought in exter-
nally via a
BNC, optionally terminated by R29. SCLK and
L/R select may be brought in externally via test
points and removing jumpers.
Figure 5 shows the on-board clock generation
circuitry. U7 (74HC4040) produces binary di-
vided ratios of the 24.576 MHz master clock. Q4
generates a 1.5 MHz clock, which is used for
SCLK. Q8 generates a 96 kHz clock, used for
HOLD, and Q9 generates a 48 kHz clock, option-
ally used to toggle L/R select. This set of clocks
causes the CS5126 to continuously convert, gen-
erating a continuous stream of serial data bits. To
correctly identify the last bit of each word, U12
produces a pulse only when Q4, Q5, Q6, Q7, Q8,
and optionally Q9 are all high. This state is
latched by U10A to prevent any glitches, and the
resulting signal (attached to TP18) is used to
latch the U8-U9 shift registers.
Serial to Parallel Conversion
Figure 6 shows the serial to parallel conversion
circuit. Two 74HC595 shift register/latches con-
nected in series with SDATA assemble 16-bit,
parallel words, clocked by SCLK. As discussed
above, the outputs are latched inside the
74HC595 at the end of each 16-bit word. The
outputs are brought out to a 40-way header (P5).
Only low capacitance, twisted pair, ribbon cable
should be used.
Q12
Q11
Q10
Q9
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
U7
7
4HCT4040
15
14
12
10
11
9
7
6
5
3
2
4
13
1
16
8
U6
OUT
14
7
8
C28
0.1
F
+5VL
+5VL
C29
0.1
F
U11
12
13
11
P10
0
1
2
R28
470
1
R19
47 k
47 k
U12
14
C32
0.1
F
7
8
U11
14
C30
0.1
F
7
3
1
2
CLR
K
Q
Q
J
4
C31
0.1
F
1
14
2
3
11
12
13
P12
U11, pin 8
0
1
74HC30
74HC00
U10A
74HC73
Crystal
Oscillator
Module
P4
P1
(CLKIN)
P2
(HOLD)
+5VL
P3
U8, U9
Shift CLK
U8, U9
Latch CLK
P9
P7
1
0
11
12
2
3
4
5
6
R18
47 k
R16, p.5
47 k
R16, p.3
47 k
R16
p.4
Figure 5. Timing Generator
CDB5126
DS32DB5
25
13
10
11
12
8
9
16
13
11
12
8
14
10
16
14
RST
Shift CLK
Latch CLK
DATA IN
OE
Q H
G
Q
F
Q
E
Q
D
Q
C
Q
B
Q
A
Q
U9
74HC595
+5VL
+5VL
0.1
F
C5
R 31
47 k
0.1
F
C3
6
6
5
4
10
7
5
8
J
K
RST
U10B
74HC73
Q
+5VL
0
1
2
3
4
8
9
U11
10
TP 17
P8
P6
R 22
47 k
+5VL
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DACK
CS
DRDY
RST
Shift CLK
Latch CLK
DATA OUT
OE
Q H
G
Q
F
Q
E
Q
D
Q
C
Q
B
Q
A
Q
DATA IN
U8
74HC595
7
6
5
4
3
2
1
15
7
6
5
4
3
2
1
15
R16, p.9
47 k
+5VL
R16, p.6
47 k
R16, p.7
47 k
U11
TP 18
74HC00
74HC00
P7
SDATA (U1)
P9, P3
TRKL (U1)
TRKR (U1)
P12
P11
0
1
P5
40 way
header
R 30
47 k
Figure 6. Serial to Parallel Converter
CDB5126
26
DS32DB5
P1
0 - Select external clock via BNC connector
1 - Select on-board clock generated by U6.
P2
0 - Select on-board generated HOLD.
1 - Select external HOLD via BNC connector.
P3
Connect SCLK to on-board shift registers.
P4
0 -
Pull L
/
R select pin high, selecting the left channel only.
1 - Drive L/R select at 48 kHz from the on-board timing generator.
2 - Pull L/R select pin low, selecting the right channel only.
P6
Connect the OE pins of the shift registers to ground. Permanently enables the 3-state output buffers.
P7
0 - Connects the on-board Data Ready signal to the shift registers.
1 - Connects the NAND gate outputs (U11, pin 11) to the shift registers.
P8
1 - Connects the un-latched on-board Data Ready signal to P5.
2 - Connects TRKL and TRKR
ANDED together to P5. This signal can be used as an "End of Convert"
indicator.
3 - Connects TRKL to P5.
4 - Connects TRKR to P5.
P9
Connects the on-board generated SCLK to the rest of the on-board circuitry.
P10
0 - Causes the on-board Data Ready generating circuit to flag data ready every conversion.
1 - Causes the on-board Data Ready generating circuit to flag data ready every left conversion. P4 must
be in position 1 for this to work.
2 - Causes the on-board Data Ready generating circuit to flag data ready every right conversion. P4 must
be in position 1 for this to work.
P11
0 - Connects TRKL & TRKR to U10B, the handshake flip-flop.
1 - Connects the on-board data ready signal to U10B.
P12
0 - Allows selection of the DRDY signals for alternate channels.
1 - Connects the TRKL & TRKR to U11, pin 13.
Factory default state for CS5126
Table 1. Solder Link Options
Table 2. Shorting Plug Selectable Options
J1
-
Joins analog ground to digital ground on the board.
J2
-
Joins LT1019-5 reference directly to the VREF pin on the ADC. Before doing this, break the connection
between R3 and the ADC VREF pin by using a twist drill to remove the central feedthrough. This option
allows evaluation of different reference configurations.
J4
-
Connects an external clock to CLKIN on the ADC.
CDB5126
DS32DB5
27
U10B (74HC73) is used as a handshake flip-flop
with the computer system attached to the evalu-
ation board. The board brings DRDY low. The
computer reads the data and then sets DACK mo-
mentarily high. This resets U10B for the next
word. This handshake can be disabled by setting
P8 jumper to position 1.
DIP Switches
Figure 7 and Table 3 shows the DIP switch se-
lectable options.
Test Points
Table 4 is a list of the test points provided on the
Evaluation Board.
ON
OPEN
1
2
4
5
6
SLEEP mode
set at logic "1" for CS5126
(user option)
Output Encoding
set at logic "1" for CS5126
No Connect
Logic "0" = ON = CLOSED / Logic "1" = OFF = OPEN
Figure 7. DIP switch configuration
Switch
Logic
Mode
1
0
SLEEP mode
1
Normal mode
2, 3, 4
set to "1" for CS5126
5
0
Offset binary output code
1
2's complement output code
6
Unconnected. Available for
user's applications
Table 3. DIP Switch Selection Options
CS5126
TP1
VREF
TP2
AINR
TP3
AINL
TP4
AGND
TP5
SSH2
TP6
SSH1
TP7
TRKR
TP8
TRKL
TP9
STBY
TP10
NC
TP11
L/R
TP12
SCLK
TP13
HOLD
TP14
SDATA
TP15
CLKIN
TP16
DGND
TP17
TRKL + TRKR
TP18
Latch Clock for the 74HC595
shift registers
Table 4. CDB5126 Test Points
CDB5126
28
DS32DB5
Miscellaneous Hints on Using the Evaluation
Board
Always hit the reset button after powering-up the
board. The CS5126 is self calibrating and require
the reset signal to initiate the calibration proce-
dure.
P4 controls the ADC input mux. This is used to
set the mux to be continuously connected to one
channel, or to be toggling between two channels.
This is very useful for evaluating oversampled
vs. regular sampling digital audio.
P10 controls the Data Ready pulses from the on-
board logic. To cause every data sample to be
read, select option 0. If you wish to read only
every alternate sample, then select option 1 or 2,
depending on whether you wish to read every left
channel value, or every right channel value. This
is useful for evaluating the part with a test system
which does not separate alternate values.
CDBCAPTURE Interface
Figure 8 illustrates the CDBCAPTURE interface
that can be constructed in the digital patch area.
A 2-row, 10 pin stake header is wired as shown.
GND
(GND-Digital Patch)
+5V
+5V
FRAME
SCLK
SDATA
(+5VL - Digital Patch)
(+5VL - Digital Patch)
GND
GND
GND
GND
(DRDY - P8)
(SCLK - U9-11)
(SDATA - U8-14)
Circuit Board
(Top View)
Figure 8. CDBCAPTURE Header Signal Pattern
CDB5126
DS32DB5
29
Figure 9. CDB5126 Component Layout
CDB5126
30
DS32DB5
Notes
CDB5126
DS32DB5
31
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