Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2003
(All Rights Reserved)
http://www.cirrus.com
CS5361
114 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
!
Advanced Multi-bit Delta-Sigma Architecture
!
24-Bit Conversion
!
114 dB Dynamic Range
!
-105 dB THD+N
!
System Sampling Rates up to 192 kHz
!
135 mW Power Consumption
!
High Pass Filter and DC Offset Calibration
!
Supports Logic Levels Between 5 and 2.5 V
!
Differential Analog Architecture
!
Linear Phase Digital Anti-Alias Filtering
!
Overflow Detection
General Description
The CS5361 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion and anti-alias filtering, generating 24-
bit values for both left and right inputs in serial form at
sample rates up to 192 kHz per channel.
The CS5361 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
The CS5361 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
A/V receivers, DVD-R, CD-R, digital mixing consoles,
and effects processors.
ORDERING INFORMATION
CS5361-KS
-10 to 70C
24-pin SOIC
CS5361-KZ
-10 to 70C
24-pin TSSOP
CS5361-BZ
-40 to 85C
24-pin TSSOP
CS5361-DZ
-40 to 85C
24-pin TSSOP
CDB5361
Evaluation Board
Voltage Reference
Serial Output Interface
Digital
Filter
High
Pass
Filter
High
Pass
Filter
Decimation
Digital
Filter
Decimation
DAC
-
+
S/H
DAC
-
+
S/H
AINR+
SCLK
SDOUT
MCLK
RST
VQ
LRCK
AINR-
AINL+
AINL-
FILT+
I
2
S/LJ
M/S
HPF
MODE0
MODE1
REFGND
V
L
MDIV
LP Filter
LP Filter
OVFL
MAR `03
DS467PP3
CS5361
2
TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS (CS5361-KS/KZ) .................................................................... 5
ANALOG CHARACTERISTICS (CS5361-BZ/DZ) .................................................................... 6
DIGITAL FILTER CHARACTERISTICS.................................................................................... 7
DC ELECTRICAL CHARACTERISTICS................................................................................. 10
DIGITAL CHARACTERISTICS ............................................................................................... 10
THERMAL CHARACTERISTICS............................................................................................ 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 11
2.0 PIN DESCRIPTIONS ............................................................................................................ 14
3.0 TYPICAL CONNECTION DIAGRAM .................................................................................... 15
4.0 APPLICATIONS .................................................................................................................... 16
4.1 Operational Mode/Sample Rate Range Select ................................................................ 16
4.2 System Clocking .............................................................................................................. 16
4.2.1 Slave Mode ......................................................................................................... 16
4.2.2 Master Mode ....................................................................................................... 17
4.3 Power-up Sequence ........................................................................................................ 18
4.4 Analog Connections ......................................................................................................... 18
4.5 High Pass Filter and DC Offset Calibration ..................................................................... 19
4.6 Overflow Detection ........................................................................................................... 19
4.6.1 OVFL Output Timing ........................................................................................... 19
4.7 Grounding and Power Supply Decoupling ....................................................................... 19
4.8 Synchronization of Multiple Devices ................................................................................ 20
5.0 PARAMETER DEFINITIONS ................................................................................................ 21
6.0 PACKAGE DIMENSIONS
.................................................................................................. 22
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to
www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT-
ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
CS5361
3
LIST OF FIGURES
Figure 1. Single Speed Mode Stopband Rejection ..................................................... 8
Figure 2. Single Speed Mode Transition Band ........................................................... 8
Figure 3. Single Speed Mode Transition Band (Detail) .............................................. 8
Figure 4. Single Speed Mode Passband Ripple ......................................................... 8
Figure 5. Double Speed Mode Stopband Rejection ................................................... 8
Figure 6. Double Speed Mode Transition Band ......................................................... 8
Figure 7. Double Speed Mode Transition Band (Detail) ............................................. 9
Figure 8. Double Speed Mode Passband Ripple ....................................................... 9
Figure 9. Quad Speed Mode Stopband Rejection ...................................................... 9
Figure 10. Quad Speed Mode Transition Band .......................................................... 9
Figure 11. Quad Speed Mode Transition Band (Detail) ............................................. 9
Figure 12. Quad Speed Mode Passband Ripple ........................................................ 9
Figure 13. Master Mode, Left Justified SAI .............................................................. 12
Figure 14. Slave Mode, Left Justified SAI ................................................................ 12
Figure 15. Master Mode, I
2
S SAI .............................................................................. 12
Figure 16. Slave Mode, I
2
S SAI ................................................................................ 12
Figure 17. OVFL Output Timing ............................................................................... 12
Figure 18. Left Justified Serial Audio Interface ......................................................... 13
Figure 19. I
2
S Serial Audio Interface ........................................................................ 13
Figure 20. OVFL Output Timing, I2S Format ............................................................ 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................. 13
Figure 22. Typical Connection Diagram ................................................................... 15
Figure 23. CS5361 Master Mode Clocking ............................................................... 17
Figure 24. CS5361 Recommended Analog Input Buffer .......................................... 18
LIST OF TABLES
Table 1. CS5361 Mode Control .............................................................................. 16
Table 2. CS5361 Slave Mode Clock Ratios ........................................................... 16
Table 3. CS5361 Common Master Clock Frequencies .......................................... 17
CS5361
4
1.0 CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and T
A
= 25
C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1)
Notes: 1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR
latch-up.
3. The maximum over/under voltage is limited by the input current.
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies:
Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
4.75
3.1
2.37
5.0
3.3
3.3
5.25
5.25
5.25
V
V
V
Ambient Operating Temperature
Commercial (-KS/-KZ)
Industrial (-BZ)
Automotive (-DZ)
T
AC
T
AI
T
AA
-10
-40
-40
-
-
-
70
85
85
C
C
C
Parameter
Symbol
Min
Max
Units
DC Power Supplies:
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 2)
I
in
-
10
mA
Analog Input Voltage
(Note 3)
V
IN
GND - 0.7
VA + 0.7
V
Digital Input Voltage
(Note 3)
V
IND
-0.7
VL + 0.7
V
Ambient Operating Temperature (Power Applied)
T
A
-50
+95
C
Storage Temperature
T
stg
-65
+150
C
CS5361
5
ANALOG CHARACTERISTICS (CS5361-KS/KZ)
(Test conditions (unless otherwise speci-
fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.)
Notes: 4. Referred to the typical full-scale input voltage.
5.
Measured between AIN+ and AIN-
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
108
105
114
111
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-105
-91
-51
-99
-
-
dB
dB
dB
Double Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
108
105
-
114
111
108
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
THD+N
-
-
-
-
-105
-91
-51
-102
-99
-
-
-
dB
dB
dB
dB
Quad Speed Mode
Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
108
105
-
114
111
108
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
THD+N
-
-
-
-
-105
-91
-51
-102
-99
-
-
-
dB
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation
-
110
-
dB
Interchannel Phase Deviation
-
0.0001
-
Degree
DC Accuracy
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-
5
%
Gain Drift
-
100
-
ppm/C
Offset Error
HPF enabled
HPF disabled
-
-
0
100
-
-
LSB
LSB
Analog Input Characteristics
Full-scale Input Voltage (at VA = 5 V)
1.9
2.0
2.1
Vrms
Input Impedance (Differential)
(Note 5)
37
-
-
k
Common Mode Rejection Ratio
CMRR
-
82
-
dB
CS5361
6
ANALOG CHARACTERISTICS (CS5361-BZ/DZ)
(Test conditions (unless otherwise speci-
fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.)
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
106
103
114
111
-
-
dB
dB
Total Harmonic Distortion + Noise
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-105
-91
-51
-97
-
-
dB
dB
dB
Double Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
106
103
-
114
111
108
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
THD+N
-
-
-
-
-105
-91
-51
-102
-97
-
-
-
dB
dB
dB
dB
Quad Speed Mode
Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
106
103
-
114
111
108
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
THD+N
-
-
-
-
-105
-91
-51
-102
-97
-
-
-
dB
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation
-
110
-
dB
Interchannel Phase Deviation
-
0.0001
-
Degree
DC Accuracy
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-
5
%
Gain Drift
-
100
-
ppm/C
Offset Error
HPF enabled
HPF disabled
-
-
0
100
-
-
LSB
LSB
Analog Input Characteristics
Full-scale Input Voltage (at VA = 5 V)
1.8
2.0
2.2
Vrms
Input Impedance (Differential)
(Note 5)
37
-
-
k
Common Mode Rejection Ratio
CMRR
-
82
-
dB
CS5361
7
DIGITAL FILTER CHARACTERISTICS
Notes: 6. The filter frequency response scales precisely with Fs.
7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
Parameter
Symbol
Min
Typ
Max
Unit
Single Speed Mode (2 kHz to 50 kHz sample rates)
Passband
(-0.1 dB)
(Note 6)
0
-
0.47
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 6)
0.58
-
-
Fs
Stopband Attenuation
-95
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
12/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
Double Speed Mode (50 kHz to 100 kHz sample rates)
Passband
(-0.1 dB)
(Note 6)
0
-
0.45
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 6)
0.68
-
-
Fs
Stopband Attenuation
-92
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
9/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
Quad Speed Mode (100 kHz to 200 kHz sample rates)
Passband
(-0.1 dB)
(Note 6)
0
-
0.24
Fs
Passband Ripple
-
-
0.035
dB
Stopband
(Note 6)
0.78
-
-
Fs
Stopband Attenuation
-97
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
t
gd
-
5/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0.0
s
High Pass Filter Characteristics
Frequency Response
-3.0 dB
-0.13 dB
(Note 7)
-
1
20
-
-
Hz
Hz
Phase Deviation
@ 20 Hz
(Note 7)
-
10
-
Deg
Passband Ripple
-
-
0
dB
Filter Settling Time
10
5
/Fs
s
CS5361
8
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
pl
it
ude
(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
A
m
pl
i
t
ude
(
d
B
)
Figure 1. Single Speed Mode Stopband Rejection
Figure 2. Single Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
Frequency (normalized to Fs)
A
m
p
lit
u
d
e
(
dB
)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
A
m
pl
i
t
ude
(
d
B
)
Figure 3. Single Speed Mode Transition Band (Detail)
Figure 4. Single Speed Mode Passband Ripple
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
p
l
i
t
ud
e
(
dB
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Amp
l
i
t
u
d
e
(
d
B)
Figure 5. Double Speed Mode Stopband Rejection
Figure 6. Double Speed Mode Transition Band
CS5361
9
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.40
0.43
0.45
0.48
0.50
0.53
0.55
Frequency (normalized to Fs)
Amp
lit
u
d
e
(
d
B)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
A
m
pl
i
t
ud
e
(
d
B
)
Figure 7. Double Speed Mode Transition Band (Detail)
Figure 8. Double Speed Mode Passband Ripple
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
A
m
pl
it
u
d
e
(
dB
)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
Frequency (normalized to Fs)
A
m
pli
t
ude
(
d
B
)
Figure 9. Quad Speed Mode Stopband Rejection
Figure 10. Quad Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
Frequency (normalized to Fs)
A
m
p
l
i
t
ud
e
(
dB
)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
A
m
pl
i
t
ude
(
d
B
)
Figure 11. Quad Speed Mode Transition Band (Detail)
Figure 12. Quad Speed Mode Passband Ripple
CS5361
10
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground.
MCLK=12.288 MHz; Master Mode)
Notes: 8. Power Down Mode is defined as RST = Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
THERMAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Current
VA
(Normal Operation)
VL,VD = 5 V
VL,VD = 3.3 V
I
A
I
D
I
D
-
-
-
17.5
22
14.5
21
26
17
mA
mA
mA
Power Supply Current
VA
(Power-Down Mode) (Note 8)
VL,VD=5 V
I
A
I
D
-
-
2
2
-
-
mA
mA
Power Consumption
(Normal Operation)
VL, VD=5 V
VL, VD = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
198
135
20
235
161
-
mW
mW
mW
Power Supply Rejection Ratio
(1 kHz)
(Note 9)
PSRR
-
65
-
dB
V
Q
Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
2.5
25
0.01
-
-
-
V
k
mA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
5
18
0.01
-
-
-
V
k
mA
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
(% of VL)
V
IH
70%
-
-
V
Low-Level Input Voltage
(% of VL)
V
IL
-
-
30%
V
High-Level Output Voltage at I
o
= 100
A
(% of VL)
V
OH
70%
-
-
V
Low-Level Output Voltage at I
o
= 100
A
(% of VL)
V
OL
-
-
15%
V
OVFL Current Sink
I
ovfl
-
-
4.0
mA
Input Leakage Current
I
in
-
-
10
A
Parameter
Symbol
Min
Typ
Max
Unit
Allowable Junction Temperature
-
-
135
C
Junction to Ambient Thermal Impedance
JA
-
70
-
C/W
CS5361
11
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V;
Logic "1" = VL, C
L
= 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Input Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
50
100
200
kHz
kHz
kHz
OVFL to LRCK edge setup time
t
setup
16/f
sclk
-
-
s
OVFL to LRCK edge hold time
t
hold
1/f
sclk
-
-
s
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period
t
clkw
40
-
1953
ns
MCLK Pulse Width High
t
clkh
16
-
-
ns
MCLK Pulse Width Low
t
clkl
16
-
-
ns
Master Mode
SCLK falling to LRCK
t
mslr
-20
-
20
ns
SCLK falling to SDOUT valid
t
sdo
0
-
32
ns
SCLK Duty Cycle
-
50
-
%
Slave Mode
Single Speed
Output Sample Rate
Fs
2
-
50
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
163
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
32
ns
SCLK falling to LRCK edge
t
slrd
-20
-
20
ns
Double Speed
Output Sample Rate
Fs
50
-
100
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
163
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
32
ns
SCLK falling to LRCK edge
t
slrd
-20
-
20
ns
Quad Speed
Output Sample Rate
Fs
100
-
200
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
t
sclkw
81
-
-
ns
SCLK High/Low
t
sclkhl
20
-
-
ns
SCLK falling to SDOUT valid
t
dss
-
-
32
ns
SCLK falling to LRCK edge
t
slrd
-10
-
10
ns
CS5361
12
SCLK output
t msl
r
SDOUT
t sd
o
LRCK
output
MSB
MSB-1
SCLK input
LRCK input
sclkl
t
dss
t
MSB
MSB-1
MSB-2
lrdss
t
sclkh
t
t
sclkw
SDOUT
s rd
l
t
Figure 13. Master Mode, Left Justified SAI
Figure 14. Slave Mode, Left Justified SAI
SCLK
output
tmslr
SDOUT
t
sdo
LRCK output
MSB
SCLK input
LRCK input
sclkl
t
dss
t
MSB
MSB-1
sclkh
t
tsclkw
SDOUT
Figure 15. Master Mode, I
2
S SAI
Figure 16. Slave Mode, I
2
S SAI
OVFL
t setup
LRCK
t hold
Figure 17. OVFL Output Timing
CS5361
13
S D A T A
2 3 2 2
7
6
23 2 2
S C L K
L R C K
2 3 2 2
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
9
9
L eft C h a n n e l
R ig h t C h a n n e l
Figure 18. Left Justified Serial Audio Interface
S D A T A
2 3 22
8
7
2 3 2 2
S C L K
LR C K
2 3 2 2
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
9
9
L e ft C h a n n e l
R ig h t C h a n n e l
Figure 19. I
2
S Serial Audio Interface
LRCK
OVFL
SCLK
OVFL_R
OVFL_L
OVFL_R
Figure 20. OVFL Output Timing, I
2
S Format
LRCK
OVFL
SCLK
OVFL_R
OVFL_L
OVFL_R
Figure 21. OVFL Output Timing, Left-Justified Format
CS5361
14
2.0 PIN DESCRIPTIONS
RST
1
24
FILT+
M/S
2
23
REFGND
LRCK
3
22
VQ
SCLK
4
21
AINR+
MCLK
5
20
AINR-
VD
6
19
VA
GND
7
18
GND
VL
8
17
AINL-
SDOUT
9
16
AINL+
MDIV
10
15
OVFL
HPF
11
14
M1
I
2
S/LJ
12
13
M0
Pin Name
#
Pin Description
RST
1
Reset (Input) - The device enters a low power mode when low.
M/S
2
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
LRCK
3
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
4
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
GND
7,18
Ground (Input) - Ground reference. Must be connected to analog ground.
VL
8
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
9
Serial Audio Data Output (Output) - Output for two's complement serial audio data.
MDIV
10
MCLK Divider (Input) - Enables a master clock divide by two function.
HPF
11
High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
I
2
S/LJ
12
Serial Audio Interface Format Select (Input) -Selects either the left-justified or I
2
S format for the SAI.
M0
M1
13,
14
Mode Selection (Input) - Determines the operational mode of the device.
OVFL
15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
AINL+
AINL-
16,
17
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VA
19
Analog Power (Input) - Positive power supply for the analog section.
AINR-
AINR+
20,
21
Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REF_GND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
CS5361
15
3.0 TYPICAL CONNECTION DIAGRAM
FILT+
AINL+
AINL-
V
D
0.1
F
A/D CONVERTER
SCLK
CS5361
M / S
MCLK
AINR+
AINR-
VQ
47
F
+
RST
VA
V
L
+5V
1
F
+5V to 2.5V
5.1
1
F
+
+
+
SDOUT
GND
I
2
S/LJ
LRCK
GND
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.1
F
0.1
F
0.1
F
0.1
F
HPF
M0
M1
REFGND
MDIV
+5 V to 3.3 V
1
F
0.1
F
1
F
+
Analog
Input
Buffer
(Figure 3)
Analog
Input
Buffer
(Figure 3)
OVFL
VL
10 k
Figure 22. Typical Connection Diagram
CS5361
16
4.0 APPLICATIONS
4.1
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 200 kHz. The CS5361 must be set to
the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.
4.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are
synchronously generated on-chip, or Slave Mode, which requires external generation of the
left/right and serial clocks. The device also includes a master clock divider in Master Mode where
the master clock will be internally divided prior to any other internal circuitry when MDIV is en-
abled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.
4.2.1
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously
derived from the master clock and be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance. Refer to Table 2 for required clock ratios.
Table 2. CS5361 Slave Mode Clock Ratios
M1 (Pin 14)
M0 (Pin 13)
MODE
Output Sample Rate (Fs)
0
0
Single Speed Mode
2 kHz - 50 kHz
0
1
Double Speed Mode
50 kHz - 100 kHz
1
0
Quad Speed Mode
100 kHz - 200 kHz
1
1
Reserved
Table 1. CS5361 Mode Control
Single Speed Mode
Fs = 2 kHz to 50 kHz
Double Speed Mode
Fs = 50 kHz to 100 kHz
Quad Speed Mode
Fs = 100 kHz to 200 kHz
MCLK/LRCK Ratio
256x, 512x
128x, 256x
128x
SCLK/LRCK Ratio
32x, 64x, 128x
32x, 64x
64x
CS5361
17
4.2.2
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are inter-
nally derived from the master clock with the left/right clock equal to Fs and the serial clock equal
to 64x Fs, as shown in Figure 2. Refer to Table 3 for common master clock frequencies.
128
256
64
M0
M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
2
4
1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
2
1
0
1
MCLK
MDIV
Figure 23. CS5361 Master Mode Clocking
SAMPLE RATE (kHz)
MDIV = 0
MCLK (MHz)
MDIV = 1
MCLK (MHz)
32
8.192
16.384
44.1
11.2896
22.5792
48
12.288
24.576
64
8.192
16.384
88.2
11.2896
22.5792
96
12.288
24.576
176.4
11.2896
22.5792
192
12.288
24.576
Table 3. CS5361 Common Master Clock Frequencies
CS5361
18
4.3
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies,
clocks and configuration pins are stable. It is also recommended that reset be enabled if the an-
alog or digital supplies drop below the minimum specified operating voltages to prevent power
glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore,
there is a delay between the release of reset and the generation of valid output, due to the finite
output impedance of FILT+ and the presence of the external capacitance.
4.4
Analog Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for input signals
which are (n
6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3
which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition
to providing the optimum source impedance for the modulators. The use of capacitors which
have a large voltage coefficient (such as general purpose ceramics) must be avoided since these
can degrade signal linearity.
Please see the Addendum at the end of the data sheet for an analog input buffer that can be used
with both the CS5351 as well as the CS5361 with a simple change in the bill of materials.
CS5361 AIN+
CS5361 AIN-
COG
2700 pF
AIN+
AIN-
10 F
10 F
100 k
634 k
91
10 k
10 k
100 k
634
91
470 pF
COG
470 pF
COG
VQ
Figure 24. CS5361 Recommended Analog Input Buffer
CS5361
19
4.5
High Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC off-
set into the A/D converter. The CS5361 includes a high pass filter after the decimator to remove
any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching
between devices in a multichannel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the dec-
imation filter. If the HPF pin is taken high during normal operation, the current value of the DC
offset register is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1) Running the CS5361 with the high pass filter enabled until the filter settles. See the Digital
Filter Characteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path be-
tween the calibration point and the CS5361.
4.6
Overflow Detection
The CS5361 includes overflow detection on both the left and right channels. This time multi-
plexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and
OVFL_R data will go to a logical low as soon as an overrange condition in either channel is de-
tected. The data will remain low as specified in the Switching Characteristics - Serial Audio Port
section. This ensures sufficient time to detect an overrange condition regardless of the speed
mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has
not been any other overrange condition detected. Please note that an overrange condition on ei-
ther channel will restart the timeout period for both channels.
4.6.1
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I
2
S
format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23
and 24. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the
data. In left-justified format, the rising edge of LRCK would latch the right channel overflow sta-
tus, and the falling edge of LRCK would latch the left channel overflow status. In I
2
S format, the
falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK
would latch the left channel overflow status.
4.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5361 requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 22 shows the rec-
ommended power arrangements, with VA and VL connected to clean supplies. VD, which pow-
ers the digital filter, may be run from the system logic supply or may be powered from the analog
supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling
capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being
the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in
CS5361
20
order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors,
particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF-
GND. The CDB5361 evaluation board demonstrates the optimum layout and power supply ar-
rangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sam-
pling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the
CS5361's in the system. If only one master clock source is needed, one solution is to place one
CS5361 in Master mode, and slave all of the other CS5361's to the one master. If multiple master
clock sources are needed, a possible solution would be to supply all clocks from the same exter-
nal source and time the CS5361 reset with the inactive edge of MCLK. This will ensure that all
converters begin sampling on the same clock edge.
CS5361
21
5.0 PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
CS5361
22
6.0 PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.598
0.614
15.20
15.60
E
0.291
0.299
7.40
7.60
e
0.040
0.060
1.02
1.52
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
0
8
0
8
24L SOIC (300 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
1
e
CS5361
23
Notes: 1."D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2.Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.
3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.043
--
--
1.10
A1
0.002
0.004
0.006
0.05
--
0.15
A2
0.03346
0.0354
0.037
0.85
0.90
0.95
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.303
0.307
0.311
7.70
7.80
7.90
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
0.026 BSC
--
--
0.65 BSC
--
L
0.020
0.024
0.028
0.50
0.60
0.70
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters.
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
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