Document Outline
- CS5504 Device Data Sheet
- Analog Characteristics
- Dynamic Charcteristics
- 5V Digital Charcteristics
- 3.3V Digital Charcteristics
- 5V Switching Characteristics
- 3.3V Switching Characteristics
- 5V Switching Characteristics
- 3.3V Switching Charcteristics
- Recommended Operating Conditions
- Absolute Maximum Ratings
- General Description
- Theory of Operation
- Ordering Information
- Environmental, Manufacturing, & Handling Information
- CDB5504 Evaluation Board Data Sheet
1
Copyright
Cirrus Logic, Inc. 1997
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS5504
Low Power, 20-Bit A/D Converter
Features
l
Delta-
sigma A/D Converter
- 20-bit
, No Missing Codes
- Linearity Error: 0.0007%FS
l
2 Differential Inputs
- Pin
-selectable Unipolar/Bipolar Ranges
- Common Mode Rejection
105 dB @ dc
120 dB @ 50, 60 Hz
l
Either 5V or 3.3V Digital Interface
l
On-chip Self-
calibration Circuitry
l
Output Update Rates up to 200/
Sps
l
Low Power Consumption: 4.4 mW
Description
The CS5504 is a 2-channel, fully differential 20-bit, seri-
al-output CMOS A/D converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high
-resolution measurement at output word
rates up to 200 samples per second.
The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20
Sps).
The CS5504 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
Low power, high
-resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery-
powered instruments.
ORDERING INFORMATION
See
page 23
.
CS5504-BS
-40 to +85 C 20-pin SOIC
I
CS
AIN1-
A0
VREF+
VREF-
DGND
VD+
SCLK
SDATA
DRDY
CAL
BP/UP
CONV
XIN
AIN1+
8
10
1
12
13
16
2
18
19
20
4
7
3
5
AIN2-
AIN2+
9
11
XOUT
6
17
VA-
15
VA+
14
MUX
4th-Order
Delta-Sigma
Modulator
Digital
Filter
Calibration
C
Serial
Interface
Logic
OSC
Calibration SRAM
MAR `95
DS126F1
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5504
Low-power, 20-bit A/D Converter
AUG `05
DS126F2
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CDB5504
Evaluation Board for CS5504 A/D Converter
AUG `05
DS126DB2
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5504
Low-power, 20-bit A/D Converter
AUG `05
DS126F2
ANALOG CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+ = 5V
10%; VA- = -5V
10%; VD+ =
3.3V
5%; VREF+ = 2.5V, VREF- = 0V; f
CLK
= 32.768kHz; Bipolar Mode; R
source
= 1k
with a 10nF to GND
at AIN.) (Notes 1, 2)
Parameter*
Min
Typ
Max
Units
Specified Temperature Range
-40 to +85
C
Accuracy
Linearity Error
-
0.0007
0.0015
%FS
Differential Nonlinearity
(No Missing Codes)
20
-
-
Bits
Full Scale Error
(Note 3)
-
4
32
LSB
Full Scale Drift
(Note 4)
-
8
-
LSB
Unipolar Offset
(Note 3)
-
8
32
LSB
Unipolar Offset Drift
(Note 4)
-
8
-
LSB
Bipolar Offset
(Note 3)
-
4
16
LSB
Bipolar Offset Drift
(Note 4)
-
4
-
LSB
Noise (Referred to Output)
-
2.6
-
LSB
rms
Analog Input
Analog Input Range:
Unipolar
(Note 5)
Bipolar
-
-
0 to +2.5
2.5
-
-
V
V
Common Mode Rejection:
dc
50, 60- Hz
(Note 2)
-
120
105
-
-
-
dB
dB
Off Channel Isolation
-
120
-
dB
Input Capacitance
-
15
-
pF
DC Bias Current
(Note 1)
-
5
-
nA
Power Supplies
DC Power Supply Currents:
ITotal
IAnalog
IDigital
-
-
-
465
425
40
600
-
-
A
A
A
Power Dissipation
(Note 6)
-
4.4
6.0
mW
Power Supply Rejection
-
80
-
dB
Notes:
1. Both source resistance and shunt capacitance are critical in determining the CS5504's source
impedance requirements. Refer to the text section
Analog Input Impedance Considerations
.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25 C
5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. All outputs unloaded. All inputs CMOS levels.
* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
CS5504
2
DS126F1
CS5504
2
DS126F2
5V DIGITAL CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+, VD+ = 5V
10%; VA- = -5V
10%;
DGND = 0.) (Notes 2, 7)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage:
XIN
All Pins Except XIN
V
IH
V
IH
3.5
2.0
-
-
-
-
V
V
Low-Level Input Voltage:
XIN
All Pins Except XIN
V
IL
V
IL
-
-
-
-
1.5
0.8
V
V
High-Level Output Voltage
(Note 8)
V
OH
(VD+)-1.0
-
-
V
Low-Level Output Voltage
Iout = 1.6 mA
V
OL
-
-
0.4
V
Input Leakage Current
I
in
-
1
10
A
3-State Leakage Current
I
OZ
-
-
10
A
Digital Output Pin Capacitance
C
out
-
9
-
pF
Notes:
7. All measurements are performed under static conditions.
8. I
out
= -100
A. This guarantees the ability to drive one TTL load. (V
OH
= 2.4V @ I
out
= -40
A).
DYNAMIC CHARACTERISTICS
Parameter
Symbol
Ratio
Units
Modulator Sampling Frequency
f
s
f
clk
/2
Hz
Output Update Rate (CONV = 1)
f
out
f
clk
/1622
Sps
Filter Corner Frequency
f
-3dB
f
clk
/1928
Hz
Settling Time to 1/2 LSB (FS Step)
t
s
1/f
out
s
3.3V DIGITAL CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+ = 5V
10%; VD+ = 3.3V
5%;
VA- = -5V
10%; GND = 0V.) (Notes 2, 7)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage:
XIN
All Pins Except XIN
V
IH
V
IH
0.7VD+
0.6VD+
-
-
-
-
V
V
Low-Level Input Voltage:
XIN
All Pins Except XIN
V
IL
V
IL
-
-
-
-
0.3VD+
0.16VD+
V
V
High-Level Output Voltage
Iout = -400
A
V
OH
(VD+)-0.3
-
-
V
Low-Level Output Voltage
Iout = 400
A
V
OL
-
-
0.3
V
Input Leakage Current
I
in
-
1
10
A
3-State Leakage Current
I
OZ
-
-
10
A
Digital Output Pin Capacitance
C
out
-
9
-
pF
CS5504
DS126F1
3
CS5504
DS126F2
3
5V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+, VD+ = 5V
10%;
VA- = -5V
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
Master Clock Frequency
Internal Oscillator
External Clock
XIN
f
clk
30.0
30
32.768
-
53.0
330
kHz
kHz
Master Clock Duty Cycle
40
-
60
%
Rise Times:
Any Digital Input
(Note 9)
Any Digital Output
t
rise
-
-
-
50
1.0
-
s
ns
Fall Times:
Any Digital Input
(Note 9)
Any Digital Output
t
fall
-
-
-
20
1.0
-
s
ns
Start-Up
Power-On Reset Period
(Note 10)
t
res
-
10
-
ms
Oscillator Start-up Time
XTAL = 32.768 kHz (Note 11)
t
osu
-
500
-
ms
Wake-up Period
(Note 12)
t
wup
-
1800/f
clk
-
s
Calibration
CONV Pulse Width (CAL=1)
(Note 13)
t
ccw
100
-
-
ns
CONV and CAL High to Start of Calibration
t
scl
-
-
2/f
clk
+200
ns
Start of Calibration to End of Calibration
t
cal
-
3246/f
clk
-
s
Conversion
Set Up Time
A0 to CONV High
t
sac
50
-
-
ns
Hold Time
A0 after CONV High
t
hca
100
-
-
ns
CONV Pulse Width
t
cpw
100
-
-
ns
CONV High to Start of Conversion
t
scn
-
-
2/f
clk
+200
ns
Set Up Time
BP/UP stable prior to DRDY falling
t
bus
82/f
clk
-
-
s
Hold Time
BP/UP stable after DRDY falls
t
buh
0
-
-
ns
Start of Conversion to End of Conversion
(Note 14)
t
con
-
1624/f
clk
-
s
Notes:
9. Specified using 10% and 90% points on waveform of interest.
10. An internal power-on-reset is activated whenever power is applied to the device.
11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
12. The wake-up period begins once the oscillator starts; or when using an external f
clk
, after the
power-on reset time elapses.
13. Calibration can also be initiated by pulsing CAL high while CONV=1.
14. Conversion time will be 1622/f
clk
if CONV remains high continuously.
CS5504
4
DS126F1
CS5504
4
DS126F2
3.3V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+ = 5V
10%; VD+ = 3.3V
5%; VA- = -5V
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
Master Clock Frequency
Internal Oscillator
External Clock
XIN
f
clk
30.0
30
32.768
-
53.0
330
kHz
kHz
Master Clock Duty Cycle
40
-
60
%
Rise Times:
Any Digital Input
(Note 9)
Any Digital Output
t
rise
-
-
-
50
1.0
-
s
ns
Fall Times:
Any Digital Input
(Note 9)
Any Digital Output
t
fall
-
-
-
20
1.0
-
s
ns
Start-Up
Power-On Reset Period
(Note 10)
t
res
-
10
-
ms
Oscillator Start-up Time
XTAL = 32.768 kHz (Note 11)
t
osu
-
500
-
ms
Wake-up Period
(Note 12)
t
wup
-
1800/f
clk
-
s
Calibration
CONV Pulse Width (CAL=1)
(Note 13)
t
ccw
100
-
-
ns
CONV and CAL High to Start of Calibration
t
scl
-
-
2/f
clk
+200
ns
Start of Calibration to End of Calibration
t
cal
-
3246/f
clk
-
s
Conversion
Set Up Time
A0 to CONV High
t
sac
50
-
-
ns
Hold Time
A0 after CONV High
t
hca
100
-
-
ns
CONV Pulse Widh
t
cpw
100
-
-
ns
CONV High to Start of Conversion
t
scn
-
-
2/f
clk
+200
ns
Set Up Time
BP/UP stable prior to DRDY falling
t
bus
82/f
clk
-
-
s
Hold Time
BP/UP stable after DRDY falls
t
buh
0
-
-
ns
Start of Conversion to End of Conversion
(Note 14)
t
con
-
1624/f
clk
-
s
CS5504
DS126F1
5
CS5504
DS126F2
5
t
ccw
XIN
Calibration
Standby
Standby
t
scl
t
cal
XIN/2
STATE
CAL
CONV
Figure 1. Calibration Timing (Not to Scale)
t
buh
XIN
XIN/2
Conversion
Standby
Standby
CONV
STATE
t
sac
t
hca
A0
t
scn
t
con
DRDY
BP/UP
t
bus
t
cpw
Figure 2. Conversion Timing (Not to Scale)
CS5504
6
DS126F1
CS5504
6
DS126F2
5V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+, VD+ = 5V
10%;
VA- = -5V
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
Serial Clock
f
sclk
0
-
2.5
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t
ph
t
pl
200
200
-
-
-
-
ns
ns
Access Time:
CS Low to data valid (Note 15)
t
csd
-
60
200
ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit
t
dd
-
150
310
ns
Output Float Delay:
CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z
t
fd1
t
fd2
-
-
60
160
150
300
ns
ns
Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f
clk
cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/f
clk
+ 200 ns after CS goes low.
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.
3.3V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+ = 5V
10%; VD+ = 3.3V
5%; VA- = -5V
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Parameter
Symbol
Min
Typ
Max
Units
Serial Clock
f
sclk
0
-
1.25
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t
ph
t
pl
200
200
-
-
-
-
ns
ns
Access Time:
CS Low to data valid (Note 15)
t
csd
-
100
200
ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit
t
dd
-
400
600
ns
Output Float Delay:
CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z
t
fd1
t
fd2
-
-
70
320
150
500
ns
ns
CS5504
DS126F1
7
CS5504
DS126F2
7
SCLK(i)
MSB-1
MSB
MSB-2
SDATA(o) Hi-Z
MSB-1
MSB
LSB+2
LSB+1
LSB
SCLK(i)
SDATA(o) Hi-Z
t
fd1
t
csd
t
dd
t
ph
t
pl
t
dd
t
csd
CS
CS
DRDY
DRDY
t
fd2
Figure 3. Timing Relationships; Serial Data Read (Not to Scale)
CS5504
8
DS126F1
CS5504
8
DS126F2
RECOMMENDED OPERATING CONDITIONS
(DGND = 0V) (Note 18)
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Positive Digital
(VA+) - (VA-)
Positive Analog
Negative Analog
VD+
V
diff
VA+
VA-
3.15
4.5
4.5
0
5.0
10
5.0
-5.0
5.5
11
11
-5.5
V
V
V
V
Analog Reference Voltage
(Note 19)
(VREF+)-
(VREF-)
1.0
2.5
3.6
V
Analog Input Voltage: (Note 20)
Unipolar
Bipolar
VAIN
VAIN
0
-((VREF+)-(VREF-))
-
-
(VREF+)-(VREF-)
(VREF+)-(VREF-)
V
V
Notes: 18. All voltages with respect to ground.
19. The CS5504 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode
the CS5504 will output all 1's if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-))
and will output all 0's if the input becomes more negative than 0 Volts. In bipolar mode the CS5504
will output all 1's if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output
all 0's if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Digital Ground
(Note 21)
Positive Digital
(Note 22)
Positive Analog
Negative Analog
DGND
VD+
VA+
VA-
-0.3
-0.3
-0.3
+0.3
-
-
-
-
(VD+)-0.3
6.0 or VA+
12
-6.0
V
V
V
V
Input Current, Any Pin Except Supplies
(Notes 23, 24)
I
in
-
-
10
mA
Output Current
I
out
-
-
25
mA
Power Dissipation (Total)
(Note 25)
-
-
500
mW
Analog Input Voltage
AIN and VREF pins
V
INA
(VA-)-0.3
-
(VA+)+0.3
V
Digital Input Voltage
V
IND
-0.3
-
(VD+)+0.3
V
Ambient Operating Temperature
T
A
-40
-
85
C
Storage Temperature
T
stg
-65
-
150
C
Notes: 21. No pin should go more positive than (VA+)+0.3V.
22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is
50 mA.
25. Total power dissipation, including all input currents and output currents.
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
CS5504
DS126F1
9
CS5504
DS126F2
9
GENERAL DESCRIPTION
The CS5504 is a low power, 20-bit, monolithic
CMOS A/D converter designed specifically for
measurement of dc signals. The CS5504 in-
cludes a delta-sigma charge-balance converter, a
voltage reference, a calibration micro controller
with SRAM, a digital filter and a serial interface.
The CS5504 is optimized to operate from a
32.768 kHz crystal but can be driven by an ex-
ternal clock whose frequency is between 30 kHz
and 330 kHz. When the digital filter is operated
with a 32.768 kHz clock, the filter has zeros pre-
cisely at 50 and 60 Hz line frequencies and
multiples thereof.
The CS5504 uses a "start convert" command to
latch the input channel selection and to start a
convolution cycle on the digital filter. Once the
filter cycle is completed, the output port is up-
dated. When operated with a 32.768 kHz clock
the ADC converts and updates its output port at
20 samples/sec. The output port operates in a
synchronous externally-clocked interface format.
THEORY OF OPERATION
Basic Converter Operation
The CS5504 A/D converter has three operating
states. These are stand-by, calibration, and con-
version. When power is first applied, an internal
power-on reset delay of about 10 ms resets all of
the logic in the device. The oscillator must then
begin oscillating before the device can be con-
sidered functional. After the power-on reset is
applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This
allows the delta-sigma modulator and other cir-
cuitry (which are operating with very low
currents) to reach a stable bias condition prior to
entering into either the calibration or conversion
states. During the 1800 cycle wake-up period,
the device can accept an input command. Execu-
tion of this command will not occur until the
complete wake-up period elapses. If no com-
mand is given, the device enters the standby
state.
Calibration
After the initial application of power, the
CS5504 must enter the calibration state prior to
performing accurate conversions. During calibra-
tion, the chip executes a two-step process. The
device first performs an offset calibration and
then follows this with a gain calibration. The
two calibration steps determine the zero refer-
ence point and the full scale reference point of
the converter's transfer function. From these
points it calibrates the zero point and a gain
slope to be used to properly scale the output
digital codes when doing conversions.
The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power-
on are recognized as commands, but will not be
executed until the end of the 1800 clock cycle
wake-up period.
If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con-
verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately if CAL
and CONV become active. The calibration lasts
for 3246 clock cycles. Calibration coefficients
are then retained in the SRAM (static RAM) for
use during conversion.
The states of A0 and BP/UP are ignored during
calibration but should remain stable throughout
the calibration period to minimize noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
CS5504
10
DS126F1
CS5504
10
DS126F2
output code. The only difference is that in bipo-
lar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H. This means that the bipolar measure-
ment range is not calibrated from full scale
positive to full scale negative. Instead it is cali-
brated from the bipolar zero scale point to full
scale positive. The slope factor is then extended
below bipolar zero to accommodate the negative
input signals. The converter can be used to con-
vert both unipolar and bipolar signals by
changing the BP/UP pin. Recalibration is not re-
quired when switching between unipolar and
bipolar modes.
At the end of the calibration cycle, the on-chip
micro controller checks the logic state of the
CONV signal. If the CONV input is low the de-
vice will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con-
verter will enter the conversion state and
perform a conversion on the input channel. The
CAL signal can be returned low any time after
calibration is initiated. CONV can also be re-
turned low, but it should never be taken low and
then taken back high until the calibration period
has ended and the converter is in the standby
state. If CONV is taken low and then high
again with CAL high while the converter is cali-
brating, the device will interrupt the current
calibration cycle and start a new one. If CAL is
taken low and CONV is taken low and then high
during calibration, the calibration cycle will
continue as the conversion command is disre-
garded. The state of BP/UP is not important
during calibrations.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to in-
dicate the first valid conversion after the
calibration has been completed.
Conversion
The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cy-
cle is completed (CAL is taken low after CONV
transitions high), the converter will begin a con-
version upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by A0 when CONV
transitions high. Table 1 indicates the multi-
plexer channel selection truth table.
The A0 input is latched internal to the CS5504
when CONV rises. A0 has internal pull-down
circuits which default the multiplexer to channel
AIN1.
The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 80000H (see Understanding Converter
Calibration). BP/UP can be changed after a con-
version is started as long as it is stable for 82
clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix meas-
urement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again.
The digital filter in the CS5504 has a Finite Im-
pulse Response and is designed to settle to full
accuracy in one conversion time.
If CONV is left high, the CS5504 will perform
continuous conversions. The conversion time
will be 1622 clock cycles. If conversion is initi-
A0
Channel Addressed
0
AIN1
1
AIN2
Table 1. Multiplexer Truth Table
CS5504
DS126F1
11
CS5504
DS126F2
11
ated from the standby state, there may be up to
two XIN clock cycles of uncertainty as to when
conversion actually begins. This is because the
internal logic operates at one half the external
clock rate and the exact phase of the internal
clock may be 180
out of phase relative to the
XIN clock. When a new conversion is initiated
from the standby state, it will take up to two
XIN clock cycles to begin. Actual conversion
will use 1624 clock cycles before DRDY goes
low to indicate that the serial port has been up-
dated. See the Serial Interface Logic section of
the data sheet for information on reading data
from the serial port.
In the event the A/D conversion command
(CONV going positive) is issued during the con-
version state, the current conversion will be
terminated and a new conversion will be initi-
ated.
Voltage Reference
The CS5504 uses a differential voltage reference
input. The positive input is VREF+ and the
negative input is VREF-. The voltage between
VREF+ and VREF- can range from 1 volt mini-
mum to 3.6 volts maximum. The gain slope will
track changes in the reference without recalibra-
tion, accommodating ratiometric applications.
Analog Input Range
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREF-
pins. In unipolar mode the input range will
equal the magnitude of the voltage reference. In
bipolar mode the input voltage range will equate
to plus and minus the magnitude of the voltage
reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-
ages for the A/D. The differential input voltage
can also have any common mode value as long
as the maximum signal magnitude stays within
the supply voltages.
The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield ac-
curate conversions even with noise exceeding
the input voltage range as long as the spectral
components of this noise will be filtered out by
the digital filter. For example, with a 3.0 volt
reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maxi-
mum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise ampli-
tude stays within the supply voltages.
The CS5504 converters output data in binary
format when converting unipolar signals and in
offset binary format when converting bipolar
signals. Table 2 outlines the output coding for
both unipolar and bipolar measurement modes.
Unipolar Input
Voltage
Output
Codes
Bipolar Input
Voltage
>(VREF - 1.5 LSB)
FFFFF
>(VREF - 1.5 LSB)
VREF - 1.5 LSB
FFFFF
FFFFE
VREF - 1.5 LSB
VREF/2 - 0.5 LSB
80000
7FFFF
-0.5 LSB
+ 0.5 LSB
00001
00000
-VREF + 0.5 LSB
<(+ 0.5 LSB)
00000
<(VREF + 0.5 LSB)
Note: Table excludes common mode voltage on the
signal and reference inputs.
Table 2. Output Coding
CS5504
12
DS126F1
CS5504
12
DS126F2
Converter Performance
The CS5504 A/D converter has excellent linear-
ity performance. Calibration minimizes the
errors in offset and gain. The CS5504 device
has no missing code performance to 20-bits.
The converter achieves Common Mode Rejec-
tion (CMR) at dc of 105 dB typical, and CMR at
50 and 60 Hz of 120 dB typical.
The CS5504 can experience some drift as tem-
p e ra tu r e c ha n g e s . T h e C S 5 5 0 4 us es
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.
Analog Input Impedance Considerations
The analog input of the CS5504 can be modeled
as illustrated in Figure 4 (the model ignores the
multiplexer switch resistance). Capacitors (15 pF
each) are used to dynamically sample each of
the inputs (AIN+ and AIN-). Every half XIN cy-
cle the switch alternately connects the capacitor
to the output of the buffer and then directly to
the AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capaci-
tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capaci-
tor to settle to its final value.
An equation for the maximum acceptable source
resistance is derived.
Rsmax
=
-
1
2XIN
(
15pF
+
C
EXT
)
ln
Ve
Ve
+
15pF
(
100mv
)
(
15pF
+
CEXT
)
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. CEXT is the combination
of any external or stray capacitance.
For a maximum error voltage (Ve) of 600 nV in
the CS5504 (1/4LSB at 20-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to 84 k
in the CS5504 are acceptable in the absence of
external capacitance (CEXT = 0).
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
Digital Filter Characteristics
The digital filter in the CS5504 is the combina-
tion of a comb filter and a low pass filter. The
comb filter has zeros in its transfer function
which are optimally placed to reject line interfer-
ence frequencies (50 and 60 Hz and their
multiples) when the CS5504 is clocked at
+
15 pF
V
os
100 mV
+
V
os
100 mV
Internal
Bias
Voltage
15 pF
AIN+
AIN-
-
-
Figure 4. Analog Input Model
CS5504
DS126F1
13
CS5504
DS126F2
13
32.768 kHz. Figures 5, 6 and 7 illustrate the
magnitude and phase characteristics of the filter.
Figure 5 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Ta-
ble 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fun-
damental line frequency should vary
1% from
its specified frequency. The -3dB corner fre-
quency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 7 illustrates
that the phase characteristics of the filter are pre-
cisely linear phase.
0
0
40
402.83
80
805.66
120
1208.5
160
1611.3
200
2014.2
240
2416.9
Frequency (Hz)
-160
-140
-120
-100
-80
-60
-40
-20
0
A
t
te
nu
a
t
io
n (
d
B
)
XIN = 32.768 kHz
X1
X2
X1 = 32.768kHz
X2 = 330.00kHz
Figure 5. Filter Magnitude Plot to 260 Hz
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz)
-140
-120
-100
-80
-60
-40
-20
0
A
t
t
e
nua
t
i
o
n
(
d
B)
Flatness
dB
-0.010
-0.041
-0.093
-0.166
-0.259
-0.510
-0.667
-0.846
-1.047
-3.093
1
2
3
4
5
6
7
8
9
10
17
XIN = 32.768 kHz
Frequency
-0.374
Figure 6. Filter Magnitude Plot to 50 Hz
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz)
-180
-135
-90
-45
0
45
90
135
180
P
h
ase (De
g
ree
s)
XIN = 32.768 kHz
Figure 7. Filter Phase Plot to 50 Hz
Frequency
(Hz)
Notch
Depth
(dB)
Frequency
(Hz)
Minimum
Attenuation
(dB)
50
125.6
50
1%
55.5
60
126.7
60
1%
58.4
100
145.7
100
1%
62.2
120
136.0
120
1%
68.4
150
118.4
150
1%
74.9
180
132.9
180
1%
87.9
200
102.5
200
1%
94.0
240
108.4
240
1%
104.4
Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
CS5504
14
DS126F1
CS5504
14
DS126F2
If the CS5504 is operated at a clock rate other
than 32.768 kHz, the filter characteristics, in-
cluding the comb filter zeros, will scale with the
operating clock frequency. Therefore, optimum
rejection of line frequency interference will oc-
cur with the CS5504 running at 32.768 kHz.
Anti-Alias Considerations for Spectral
Measurement Applications
Input frequencies greater than one half the out-
put word rate (CONV = 1) may be aliased by
the converter. To prevent this, input signals
should be limited in frequency to no greater than
one half the output word rate of the converter
(when
CONV =1). Frequencies close to the modulator
sample rate (XIN/2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONV = 1) these components
should be removed by means of low-pass filter-
ing prior to the A/D input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral com-
ponents from the reference voltage is desirable.
Crystal Oscillator
The CS5504 is designed to be operated using a
32.768 kHz "tuning fork" type crystal. One end
of the crystal should be connected to the XIN
input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance.
Over the industrial temperature range (-40 to
+85
C) the on-chip gate oscillator will oscillate
with other crystals in the range of 30 kHz to 53
kHz. The chip will operate with external clock
frequencies from 30 kHz to 330 kHz over the in-
dustrial temperature range. The 32.768 kHz
crystal is normally specified as a time-keeping
crystal with tight specifications for both initial
frequency and for drift over temperature. To
maintain excellent frequency stability, these
crystals are specified only over limited operating
temperature ranges (i.e. -10
C to +60
C) by the
manufacturers. Applications of these crystals
with the CS5504 does not require tight initial
tolerance or low tempco drift. Therefore, a lower
cost crystal with looser initial tolerance and tem-
pco will generally be adequate for use with the
CS5504. Also check with the manufacturer
about wide temperature range application of
their standard crystals. Generally, even those
crystals specified for limited temperature range
will operate over much larger ranges if fre-
quency stability over temperature is not a
requirement. The frequency stability can be as
bad as
3000 ppm over the operating tempera-
ture range and still be typically better than the
line frequency (50 Hz or 60 Hz) stability over
cycle-to-cycle during the course of a day.
Serial Interface Logic
The digital filter in the CS5504 takes 1624 clock
cycles to compute an output word once a con-
version begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or unselected (CS = 1). If
the port is empty or unselected, the digital filter
will update the port with a new output word.
When new data is put into the port DRDY will
go low.
Reading Serial Data
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit pre-
sent. SCLK is the input pin for the serial clock.
If the MSB data bit is on the SDATA pin, the
CS5504
DS126F1
15
CS5504
DS126F2
15
first rising edge of SCLK enables the shifting
mechanism. This allows the falling edges of
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and
the SCLK signal is high, the first falling edge of
SCLK will be ignored because the shifting
mechanism has not become activated. After the
first rising edge of SCLK, each subsequent fall-
ing edge will shift out the serial data. Once the
LSB is present, the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).
CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.
Power Supplies and Grounding
The analog and digital supply pins to the
CS5504 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
analog ground pin. No analog ground pin is re-
quired because the inputs for measurement and
for the voltage reference are differential and re-
quire no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5504 requires that the supply voltage on
the VA+ pin always be more positive than the
voltage on any other pin of the device. If this
requirement is not met, the device can latch-up
or be damaged. In all circumstances the VA+
voltage must remain more positive than the VD+
or DGND pins; VD+ must remain more positive
than the DGND pin.
The following power supply options are possi-
ble:
VA+ = +5V to +10V,
VA- = 0V,
VD+ = +5V
VA+ = +5V,
VA- = -5V,
VD+ = +5V
VA+ = +5V,
VA- = 0V to -5V,
VD+ = +3.3V
The CS5504 cannot be operated with a 3.3V
digital supply if VA+ is greater than +5.5V.
Figure 8 illustrates the System Connection Dia-
gram for the CS5504 using a single +5V supply.
Note that all supply pins are bypassed with
0.1
F capacitors and that the VD+ digital sup-
ply is derived from the VA+ supply.
Figure 9 illustrates the CS5504 using dual sup-
plies of +5 and -5V.
Figure 10 illustrates the CS5504 using dual sup-
plies of +10V analog and +5V digital.
When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
should never become more positive than VA+
under any operating condition. Remember to in-
vestigate transient power-up conditions, when
one power supply may have a faster rise time.
CS5504
16
DS126F1
CS5504
16
DS126F2
CS5504
+5V
Analog
Supply
VD+
10
VA+
Control
Logic
VA-
0.1
F
0.1
F
14
15
17
Voltage
Reference
+
-
Optional
Clock
Source
Serial
Data
Interface
*Unused analog inputs should
be tied to signal ground
Unused Logic
inputs must be
connected to
VD+ or DGND
Calibration
Control
Bipolar/
Unipolar
Input Select
Analog*
Signal
Sources
5
6
3
20
2
1
19
18
16
8
10
12
13
4
7
11
9
SCLK
SDATA
XIN
XOUT
DRDY
CS
CONV
A0
DGND
VREF+
VREF-
AIN1+
AIN2-
CAL
BP/UP
AIN1-
AIN2+
32.768 kHz
Figure 8. CS5504 System Connection Diagram Using Single Supply
CS5504
DS126F1
17
CS5504
DS126F2
17
CS5504
+5V
Analog
Supply
VD+
10
VA+
Control
Logic
VA-
0.1
F
0.1
F
14
15
17
Voltage
Reference
+
-
Optional
Clock
Source
Serial
Data
Interface
*Unused analog inputs should
be tied to signal ground
Unused Logic
inputs must be
connected to
VD+ or DGND
Calibration
Control
Bipolar/
Unipolar
Input Select
Analog*
Signal
Sources
5
6
3
20
2
1
19
18
16
8
10
12
13
4
7
11
9
SCLK
SDATA
XIN
XOUT
DRDY
CS
CONV
A0
DGND
VREF+
VREF-
AIN1+
AIN2-
CAL
BP/UP
AIN1-
AIN2+
32.768 kHz
0.1
F
-5V
Analog
Supply
Figure 9. CS5504 System Connection Diagram Using Dual Supplies
CS5504
18
DS126F1
CS5504
18
DS126F2
CS5504
+10V
Analog
Supply
VD+
VA+
Control
Logic
VA-
0.1
F
0.1
F
14
15
17
Voltage
Reference
+
-
Optional
Clock
Source
Serial
Data
Interface
*Unused analog inputs should
be tied to signal ground
Unused Logic
inputs must be
connected to
VD+ or DGND
Calibration
Control
Bipolar/
Unipolar
Input Select
Analog*
Signal
Sources
5
6
3
20
2
1
19
18
16
8
10
12
13
4
7
11
9
SCLK
SDATA
XIN
XOUT
DRDY
CS
CONV
A0
DGND
VREF+
VREF-
AIN1+
AIN2-
CAL
BP/UP
AIN1-
AIN2+
32.768 kHz
Note: VD+ should never be more positive than VA+
+5V
Digital
Supply
Figure 10. CS5504 System Connection Diagram Using Dual Supply,
+10V Analog, +5V Digital
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
CS5504
DS126F1
19
CS5504
DS126F2
19
PIN DESCRIPTIONS*
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O
CS - Chip Select, Pin 2.
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20.
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19.
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.
SCLK - Serial Clock Input, Pin 18.
A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.
1
2
3
4
5
20
15
14
13
12
11
6
7
8
9
10
16
17
18
19
MULTIPLEXER SELECTION INPUT
A0
DRDY
DATA READY
CHIP SELECT
CS
SDATA
SERIAL DATA OUTPUT
CONVERT
CONV
SCLK
SERIAL CLOCK INPUT
CALIBRATE
CAL
VD+
POSITIVE DIGITAL POWER
CRYSTAL IN
XIN
DGND
DIGITAL GROUND
CRYSTAL OUT
XOUT
VA-
NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR
BP/UP
VA+
POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT
AIN1+
VREF-
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
AIN2+
VREF+
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
AIN1-
AIN2-
DIFFERENTIAL ANALOG INPUT
*Pinout applies to both PDIP and SOIC
CS5504
20
DS126F1
CS5504
20
DS126F2
Control Input Pins
CAL - Calibrate, Pin 4.
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONV - Convert, Pin 3.
The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If
CONV is held high (CAL low) the converter will do continuous conversions.
BP/UP - Bipolar/Unipolar, Pin 7.
The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.
A0 - Multiplexer Selection Input, Pin 1.
Selects the input channel for conversion. A0=0=AIN1. A0 is latched when CONV transitions
from low to high. This input has a pull-down resistor internal to the chip.
Measurement and Reference Inputs
AIN1+, AIN2+, AIN1-, AIN2- - Differential Analog Inputs, Pins 8, 9, 10, 11.
Analog differential inputs to the delta-sigma modulator.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 12, 13.
A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.
Power Supply Connections
VA+ - Positive Analog Power, Pin 14.
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, Pin 15.
Negative analog supply voltage. Nominally -5volts.
VD+ - Positive Digital Power, Pin 17.
Positive digital supply voltage. Nominally +5 volts or +3.3 volts.
DGND - Digital Ground, Pin 16.
Digital Ground.
CS5504
DS126F1
21
CS5504
DS126F2
21
SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} -
3
/
2
LSB].
Units are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (
1
/
2
LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (
1
/
2
LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs
CS5504
22
DS126F1
CS5504
22
DS126F2
APPENDIX
The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
IQD Ltd.
North Street
Crewkerne
Somerset TA18 7AK
England
01460 77155
Mr. Pierre Hersberger
Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57
Taiwan X'tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
24/F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm 404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON, 3199
Victoria, Australia
Tel: 61-3-783 9611
Fax: 61-3-783 9703
CS5504
DS126F1
23
CS5504
DS126F2
23
ORDERING INFORMATION
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
REVISION HISTORY
Model
Package
Temperature
CS5504-BP
20-pin Plastic DIP
-40 to +85 C
CS5504-BS
20-pin SOIC
CS5504-BSZ (lead free)
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5504-BP
260 C
1
No Limit
CS5504-BS
240 C
2
365 Days
CS5504-BSZ (lead free)
260 C
3
7 Days
Revision
Date
Changes
F1
MAR 1995
First Final Release
F2
AUG 2005
Updated device ordering info. Updated legal notice. Added MSL data..
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to
www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-
TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Notes
CS5504
24
DS126F2
- NOTES -
PDF 
ZIP