Cirrus Logic, Inc. 1997

Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com

CS5516
CS5520

16-Bit/20-Bit Bridge Transducer A/D Converter

Features

On-chip Instrumentation Amplifier

On-chip Programmable Gain Amplifier

On-Chip 4-Bit D/A For Offset Removal

Dynamic Excitation Options

Linearity Error: ±0.0015% FS

- 20-Bit No Missing Codes

CMRR at 50/60 Hz > 200 dB

System Calibration Capability with calibration
read/write option

3, 4 or 5 wire Serial Communications Port

Low Power Consumption: 40 mW

- 10 µW Standby Mode for Portable applications

Description

The CS5516 and CS5520 are complete solutions for dig-
itizing low level signals from strain gauges, load cells,
and pressure transducers. Any family of mV output
transducers, including those requiring bridge excitation,
can be interfaced directly to the CS5516 or CS5520. The
devices offer an on-chip software programmable instru-
mentation amplifier block, choice of DC or AC bridge
excitation, and software selectable reference and signal
demodulation.

The CS5516 uses delta-sigma modulation to achieve
16-bit resolution at output word rates up to 60 Hz. The
CS5520 achieves 20-bit resolution at word rates up to
60 Hz.

The CS5516 and CS5520 sample at a rate set by the
user in the form of either an external CMOS clock or a
crystal. On-chip digital filtering provides rejection of all
frequencies above 12 Hz for a 4.096 MHz clock.

The CS5516 and CS5520 include system calibration to
null offset and gain errors in the input channel. The digi-
tal values associated with the system calibration can be
written to, or read from, the calibration RAM locations at
any time via the serial communications port. The 4-bit
DC offset D/A converter, in conjunction with digital cor-
rection, is initially used to zero the input offset value.

ORDERING INFORMATION

See page 29.

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DS74F1

CS5516

ANALOG CHARACTERISTICS

= T

MIN

to T

MAX

; VA+, VD+, MDRV+ = 5V; VA-, VD- = -5V;

VREF= 2.5V(external differential voltage across VREF+ and VREF-); f

CLK

= 4.9152 MHz;

AC Excitation 300 Hz; Gain = 25; Bipolar Mode; R

source

= 300

with a 4.7nF to AGND at AIN (see Note 1);

unless otherwise specified.)

Parameter*

Min

Typ

Max

Units

Specified Temperature Range

-40 to +85

Accuracy

Linearity Error

0.0015

0.003

%FS

Differential Nonlinearity

0.25

0.5

LSB

Unipolar Gain Error

(Note 2)

ppm

Bipolar Gain Error

(Note 2)

ppm

Unipolar/Bipolar Gain Drift

ppm/

Unipolar Offset

(Note 2)

LSB

Bipolar Offset

(Note 2)

LSB

Offset Drift

0.005

Noise (Referred to Input)

Gain = 25 (25 x 1)
Gain = 50 (25 x 2)

Gain = 100 (25 x 4)
Gain = 200 (25 x 8)

-
-
-
-

250
200
150
150

-
-
-
-

nVrms
nVrms
nVrms
nVrms

Notes:

1. The AIN and VREF pins present a very high input resistance at dc and a minor dynamic load which

scales to the master clock frequency. Both source resistance and shunt capacitance are therefore
critical in determining the source impedance requirements of the CS5516 and CS5520 at these pins.

2. Applies after system calibration at the temperature of interest.

Specifications are subject to change without notice.

Unipolar Mode

Bipolar Mode

LSB's

% FS

ppm FS

LSB's

% FS

ppm FS

0.4

0.26

0.0004

0.13

0.0002

0.76

0.50

0.0008

0.26

0.0004

1.52

1.00

0.0015

0.50

0.0008

3.04

2.00

0.0030

1.00

0.0015

6.08

4.00

0.0061

2.00

0.0030

VREF = 2.5V

PGA gain = 1

CS5516; 16-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.

DS74F1

CS5520

Unipolar Mode

Bipolar Mode

LSB's

% FS

ppm FS

LSB's

% FS

ppm FS

0.025

0.26

0.0000238

0.25

0.13

0.0000119

0.125

0.047

0.50

0.0000477

0.50

0.26

0.0000238

0.25

0.095

1.00

0.0000954

1.0

0.50

0.0000477

0.50

0.190

2.00

0.0001907

2.0

1.00

0.0000954

1.0

0.380

4.00

0.0003814

4.0

2.00

0.0001907

2.0

VREF = 2.5V

PGA gain = 1

CS5520; 20-Bit Unit Conversion Factors

Specifications are subject to change without notice.

* Refer to the Specification Definitions immediately following the Pin Description Section.

ANALOG CHARACTERISTICS

(continued)

Parameter*

Min

Typ

Max

Units

Specified Temperature Range

-40 to +85

Accuracy

Linearity Error

0.0007

0.0015

%FS

Differential Nonlinearity

(No Missing Codes)

Bits

Unipolar Gain Error

(Note 2)

ppm

Bipolar Gain Error

(Note 2)

ppm

Unipolar/Bipolar Gain Drift

ppm/

Unipolar Offset

(Note 2)

LSB

Bipolar Offset

(Note 2)

LSB

Offset Drift

0.005

Noise (Referred to Input)

Gain = 25 (25 x 1)
Gain = 50 (25 x 2)

Gain = 100 (25 x 4)
Gain = 200 (25 x 8)

-
-
-
-

250
200
150
150

-
-
-
-

nVrms
nVrms
nVrms
nVrms

DS74F1

ANALOG CHARACTERISTICS

(continued)

Parameter

Min

Typ

Max

Units

Specified Temperature Range

-40 to +85

Analog Input

Analog Input Range

Unipolar

Bipolar

12.5, 25, 50, 100

12.5,

25,

50,

100

mV
mV

Common Mode Rejection

50, 60 Hz

-
-

165
200

-
-

dB
dB

Input Capacitance

Input Bias Current

(Note 1)

100

Instrumentation Amplifier

Gain

Bandwidth

200

kHz

Unity Gain Bandwidth

MHz

Output Slew Rate

1.5

sec

Noise @ 10 Hz BW

100

nVrms

Power Supply Rejection @ 50/60 Hz

(Note 3)

120

Common Mode Range

(Note 4)

Chopping Frequency

XIN/128

Programmable Gain Amplifier

Gain Tracking

(Note 5)

4-Bit Offset Trim DAC

Accuracy -

Voltage Reference Input

Range

(Note 6)

2.0

2.5

3.8

Common Mode Rejection:

50, 60 Hz

-
-

200

-
-

Input Capacitance

Input Bias Current

(Note 1)

Notes:

3. This includes the on-chip digital filtering.
4. The maximum magnitude of the differential input voltage, Vdiff(in) is determined by the following:

Vdiff(in) < 300 mV - |Vcm/12.5 | and should never exceed 300mV.
Vcm is the common mode voltage which is applied to the instrumentation amplifier inputs.
The above equation should be used to calculate the allowable common mode voltage for a given
differential voltage applied to the first gain stage inputs. This limit ensures
that the instrumentation amplifier does not saturate.

5. Gain tracking accuracy can be significantly improved by uploading a calibrated gain word to the

gain register for each PGA gain selection.

6. The common mode voltage on the Voltage Reference Input, plus the reference range,

[(VREF+) - (VREF-)]/2, must not exceed

3 volts.

CS5516, CS5520

DS74F1

ANALOG CHARACTERISTICS

(continued)

Parameter

Min

Typ

Max

Units

Modulator Differential Voltage Reference

Nominal Output Voltage

3.75

Initial Output Voltage Tolerance

100

Temperature Coefficient

100

ppm/

Line Regulation

(4.75V < VA < 5.25V)

0.5

mV/V

Output Voltage Noise

0.1 to 15 Hz

p-p

Output Current Drive:

Source Current

Sink Current

-
-

20
20

Power Supplies

DC Power Supply Currents

IA+

IA-

ID+

ID-

-
-
-
-

2.7

-2.7

1.5

-0.6

3.5

-3.5

2.2

-0.8

mA
mA
mA
mA

Power Dissipation:

(Note 7)

Normal Operation

Standby Mode

-
-

37.5

-
-

Power Supply Rejection:

Positive Supplies

Negative Supplies

-
-

100

-
-

dB
dB

System Calibration Specifications

Positive Full Scale Calibration Range

(Note 8)

Unipolar Mode

Bipolar Mode

0.8T
0.8T

-
-

1.2T
1.2T

V
V

Maximum Ratiometric Offset Calibration Range

(Note 8)

Unipolar Mode

Bipolar Mode

-2T
-2T

-
-

+2T
+2T

V
V

Differential Input Voltage Range

(Notes 4, 8, 9, 10)

Unipolar Mode

Bipolar

Voffset + (1.2T)
Voffset

(1.2T)

V
V

Notes:

7. All outputs unloaded. All inputs CMOS levels.
8. T=VREF/(Gx25), where T is the full scale span, where VREF is the differential voltage across

VREF+ and VREF- in volts, and G is the gain setting of the second gain block. G can be set
to 1, 2, 4, 8. This sets the overall gain to 25, 50, 100, 200. The gain can then be fine tuned by
using the calibration of the full scale point.

9. When calibrated.

10. Voffset is the offset corrected by the offset calibration routine. Voffset may be as large as 2T.

CS5516, CS5520

DS74F1

DYNAMIC CHARACTERISTICS

Parameter

Symbol

Ratio

Units

AIN and VREF Input Sampling Frequency

clk

/128

Modulator Sampling Frequency

clk

/256

Output Update Rate

out

clk

/81,920

Filter Corner Frequency

-3dB

clk

/341,334

Settling Time to

0.0007%

(FS Step)

6/f

out

DIGITAL CHARACTERISTICS

= T

MIN

to T

MAX

; VA+, VD+ = 5V

5%; VA-, VD- = -5V

5%;

DGND = 0) All measurements below are performed under static conditions.

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage:

XIN

All Pins Except XIN

4.5
2.0

-
-

V
V

Low-Level Input Voltage

XIN

All Pins Except XIN

-
-

0.5
0.8

V
V

High-Level Output Voltage

(Note 11)

(VD+)-1.0

Low-Level Output Voltage

lout = 1.6mA

0.4

Input Leakage Current

3-State Leakage Current

Digital Output Pin Capacitance

out

Notes: 11. Iout = -100

A. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40

A).

CS5516, CS5520

DS74F1

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0V, see Note 12.)

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

VD+

VD-

VA+

VA-

4.5

-4.5

4.5

-4.5

5.0

-5.0

5.0

-5.0

5.5

-5.5

5.5

-5.5

V
V
V
V

Differential Analog Reference Voltage

(VREF+) - (VREF-)

2.0

2.5

3.8

Analog Input Voltage:

(Note 13)
Unipolar
Bipolar

VAIN
VAIN

-T

-
-

+T
+T

V
V

Notes: 12. All voltages with respect to ground.

13. The CS5516 and CS5520 can accept input voltages up to +T in unipolar mode and -T to +T in bipolar

mode where T=VREF/(Gx25). G is the gain setting at the second gain block. When the inputs exceed
these values, the CS5516 and CS5520 will output positive full scale for any input above T, and
negative full scale for inputs below AGND in unipolar and -T in bipolar mode. This applies when the
analog input does not exceed

2T overrange.

ABSOLUTE MAXIMUM RATINGS*

(AGND, DGND = 0V, all voltages with respect to ground.)

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supplies:

Positive Digital

(Note 14)

Negative Digital
Positive Analog
Negative Analog

VD+

VD-

VA+

VA-

-0.3
-0.3
-0.3

+0.3

-
-
-
-

(VA+)+0.3

-5.5

5.5

-5.5

V
V
V
V

Input Current, Any Pin Except Supplies

(Notes 15, 16)

Analog Input Voltage

AIN and VREF pins

INA

(VA-)-0.3

(VA+)+0.3

Digital Input Voltage

IND

-0.3

(VD+)+0.3

Ambient Operating Temperature

-55

125

Storage Temperature

stg

-65

150

Notes: 14. No pin should go more positive than (VA+)+0.3V. VD+ must always be less than (VA+)+0.3 V,and

can never exceed 6.0V.

15. Applies to all pins including continuous overvoltage conditions at the analog input pins.
16. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power

supply pin is

50 mA.

* WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

CS5516, CS5520

DS74F1

SWITCHING CHARACTERISTICS

= T

MIN

to T

MAX;

VA+, VD+ = 5V

5%;

VA-, VD- = -5V

5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

= 50 pF)

Parameter

Symbol

Min

Typ

Max

Units

Master Clock Frequency: Internal Oscillator / External Clock

XIN

1.0

4.096

5.0

MHz

Master Clock Duty Cycle

Rise Times

Any Digital Input

(Note 18)

Any Digital Output

rise

-
-

1.0

Fall Times

Any Digital Input

(Note 18)

Any Digital Output

fall

-
-

1.0

Startup

Power-on Reset Period

por

100

Oscillator Start-up Time

XTAL = 4.9152 MHz(Note 19)

ost

RST Pulse Width

res

1/XIN

Serial Port Timing

Serial Clock Frequency

SCLK

2.4

MHz

Serial Clock

Pulse Width High
Pulse Width Low

200
200

-
-

ns
ns

SID Write Timing

CS Enable to Valid Latch Clock

150

Data Set-up Time prior to SCLK rising

Data Hold Time After SCLK Rising

SCLK Falling Prior to CS Disable

SOD Read Timing

CS to Data Valid

150

SCLK Falling to New Data Bit

170

SCLK Falling to SOD Hi-Z

200

DRDY Falling to Valid Data

(CS = 0)

150

CS Rising to SOD Hi-Z

150

CS Disable Hold Time

CS Enable Set-up Time

150

CS Enable Hold Time

CS Disable Set-up Time

150

Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using

an external clock source.

CS5516, CS5520

DS74F1

GENERAL DESCRIPTION

The CS5516 and CS5520 are monolithic CMOS
A/D converters which include an instrumentation
amplifier input, an on-chip programmable gain
amplifier, and a DAC for offset trimming.
While the devices are optimized for ratiometric
measurement of Wheatstone bridge applications,
they can be used for general purpose low-level
signal measurement.

Each of the devices includes a two-channel dif-
ferential delta-sigma modulator (the signal
measurement input and the reference input are
digitized independently before a digital output
word is computed), a calibration microcontroller,
a two-channel digital filter, a programmable in-
strumentation amplifier block, a 4-bit DAC for

coarse offset trimming, circuitry for generation
and demodulation of AC (actually switched DC)
bridge excitation, and a serial port. The CS5516
outputs 16-bit words; the CS5520 outputs 20-bit
words.

The CS5516/20 devices can measure either
unipolar or bipolar signals. Self-calibration is
utilized to maximize performance of the meas-
urement system. To better understand the
capabilities of the CS5516/20, it is helpful to ex-
amine some of the error sources in bridge
measurement systems.

XOUT

VD+

VA+

VREF+

VREF-

DGND

VA-

AIN+

AIN-

MDRV-

0.1

BX1

BX2

SCLK

SOD

SID

SMODE

CS5516
CS5520

XIN

0.1

VD-

AGND2

MDRV+

DRDY

+5V

Analog
Supply

-5V

Analog
Supply

Excitation Supply

Synch. Signals

0.1

RST

AGND1

Bridge

Excitation

Supply

Unused logic inputs

must be connected

to DGND or VD+

Optional

Clock

Source

Control

Logic

Serial

Data

Interface

Figure 1. System Connection Diagram: AC Excitation Mode Using External Excitation

CS5516, CS5520

DS74F1

THEORY OF OPERATION

The front page of this data sheet illustrates the
block diagram of the CS5516 and CS5520 A/D
converter. The device includes an instrumenta-
tion amplifier with a fixed gain of 25. This
chopper-stabilized instrumentation amplifier is
followed by a programmable gain stage with
gain settings of 1, 2, 4, and 8. The sensitivity of
the input is a function of the programmable gain
setting and of the reference voltage connected
between the VREF+ and VREF- pins of the de-
vice. The full scale of the converter is VREF/( G
x 25) in unipolar, or

VREF/(G x 25) in bipolar,

where VREF is the reference voltage between
the VREF+ and VREF- pins, G is the gain set-
ting of the programmable gain amplifier, and 25
is the gain of the instrumentation amplifier.

After the programmable gain block, the output
of a 4-bit DAC is combined with the input sig-
nal. The DAC can be used to add or subtract
offset from the analog input signal. Offsets as
large as

200 % of full scale can be trimmed

from the input signal.

The CS5516 and CS5520 are optimized to per-
form ratiometric measurement of bridge-type
transducers. The devices support dc bridge exci-
tation or two modes of ac (switched dc) bridge
excitation. In the switched-dc modes of opera-
tion the converter fully demodulates both the
reference voltage and the analog input signal
from the bridge.

XOUT

VD+

VA+

VREF+

VREF-

DGND

VA-

AIN+

AIN-

MDRV-

0.1

SCLK

SOD

SID

SMODE

CS5516
CS5520

XIN

0.1

VD-

AGND2

MDRV+

DRDY

+5V

Analog
Supply

-5V

Analog
Supply

0.1

RST

AGND1

Unused logic inputs

must be connected

to DGND or VD+

Optional

Clock

Source

Control

Logic

Serial

Data

Interface

Figure 2. System Connection Diagram: DC Excitation Mode (EXC bit = 0), F1 = F0 = 0.

CS5516, CS5520

DS74F1

The CS5516/20 includes a microcontroller which
manages operation of the chip. Included in the
microcontroller are eight different registers asso-
ciated with the operation of the device. An 8-bit
command register is used to interpret instruc-
tions received via the serial port. When power
is applied, and the device has been reset, the se-
rial port is initialized into the command mode.
In this mode it is waiting to receive an 8-bit
command via its serial port. The first 8 bits into
the serial port are placed into the command reg-
ister. Table 1 lists all the valid command words
for reading from or writing to internal registers
of the converter. Once a valid 8-bit command
word has been received and decoded, the serial
port goes into data mode. In data mode the next
24 serial clock pulses shift data either into or out
of the serial port. When writing data to the port,
the data may immediately follow the command
word. When reading data from the port, the user
must pause after clocking in the 8-bit command
word to allow the microcontroller time to decode
the command word, access the appropriate regis-

ter to be read, and present its 24-bit word to the
port. The microcontroller will signal when the
24-bit read data is available by causing the
DRDY pin to go low.

The user must write or read the full 24-bit word
except in the case of reading conversion data. In
read data conversion mode, the user may read
less than 24 bits if CS is then made inactive
(CS = 1). CS going inactive releases user control
over the port and allows new data updates to the
port.

The user can instruct the on-chip microcontroller
to perform certain operations via the configura-
tion register. Whenever a new word is written
to the 24-bit configuration register, the micro-
controller then decodes the word and executes
the configuration register instructions. Table 2
illustrates the bits of the configuration register.
The bits in the configuration register will be dis-
cussed in various sections of this data sheet.

Command Register

RSB2

RSB1

RSB0

R/W

BIT

NAME

VALUE

FUNCTION

Must always be logic 1

RSB2-0

000
001
010
011
100
101
110
111

Selects Register to be Read or Written per R/W bit
CONVERSION DATA (read only)
CONFIGURATION
GAIN
DAC
RATIOMETRIC OFFSET
NON-RATIOMETRIC OFFSET - AIN
NON-RATIOMETRIC OFFSET - VREF
NOT USED

R/W

Read/Write

0
1

Write to the register selected by the RSB2-0 bits
Read from the register selected by the RSB2-0 bits

D2
D1
D0

0
0
0

Not Used
Not Used
Not Used

Table 1. CS5516 and CS5520 Commands

CS5516, CS5520

DS74F1

Configuration Register

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

DAC3

DAC2

DAC1

DAC0

EXC

D16

U/B

D12

Reset (R)

D11

D10

A/S

CC3

CC2

CC1

CC0

Reset (R)

BIT

NAME

VALUE

FUNCTION

DAC3

DAC Sign Bit

0
1

Add Offset
Subtract Offset

This bit is read only

DAC2-0

DAC Bits

000
001
010
011
100
101
110
111

25% Offset
50% Offset
75% Offset
100% Offset

These bits are read only

125% Offset
150% Offset
175% Offset

EXC

Excitation:

Internal
External

0
1

BX1 and BX2 outputs are determined by bits F1 and F0
BX1 is an input which determines the phase of the

demodulation clock and the BX2 output

F1-F0

Select Frequency

00
01
10
11

Excitation on BX1 & BX2 is dc. BX1=0 V, BX2=+5 V
Excitation Frequency on BX1 & BX2 is XIN/8192 Hz
Excitation Frequency on BX1 & BX2 is XIN/16384 Hz
Excitation Frequency on BX1 & BX2 is XIN/4096 Hz

D16

Must always be logic 0

G1-G0

Select PGA Gain

00
10
01
11

Gain = 1 (X25)
Gain = 2 (X25)
Gain = 4 (X25)
Gain = 8 (X25)

U/B

Select Unipolar/Bipo-
lar Mode

0
1

Bipolar Measurement Mode
Unipolar Measurement Mode

D12

Must always be logic 0

A/S

Awake/Sleep

0
1

Awake Mode
Sleep Mode

Execute Calibration

0
1

Calibration not active
Perform calibration selected by CC3-CC0 bits. EC bit

must be written back to "0" after calibration is completed

Must always be logic 0

CC3-CC0

Calibration Control Bits

0000
1000
0100
0010
0001

No calibration to be performed
Calibrate non-ratiometric offset, VREF
Calibrate non-ratiometric offset, AIN
Calibrate ratiometric offset, AIN
Calibrate gain, AIN

Must always be logic 0

Reset Filter

0
1

Normal operation
Reset Filter

Notes: 1.Reset State

2.A write to these bits does not change the register bit values. These bits are just a mirror of the DAC register contents.

Table 2. Configuration Register

CS5516, CS5520

DS74F1

System Initialization

W h e n e v e r p o we r i s ap p l ie d to t he
CS5516/CS5520 A/D converters, the devices
must be reset to a known condition before
proper operation can occur. The internal reset is
applied after power is established and lasts for
approximately 100 ms. The RST pin can also be
used to establish a reset condition. The reset sig-
nal should remain low for at least one XIN clock
cycle to ensure adequate reset time. It is recom-
mended that the RST pin be used to reset the
converter if the power supplies rise very slowly
or with poor startup characteristics. The RST
signal can be generated by a microcontroller out-
put, or by use of an R-C circuit.

The reset function initializes the configuration
register and all five of the calibration registers;
and places the microcontroller in command
mode ready to accept a command from the serial
port. Whenever the device is reset the DRDY
pin will be set to a logic 1 and the on-chip regis-
ters are initialized to the following states:

Configuration

000000(H)

Calibration registers:

DAC

000000(H)

Gain

800000(H)

AIN Ratiometric Offset

000000(H)

AIN Non-ratiometric Offset

000000(H)

VREF Non-ratiometric Offset 000000(H)

CALIBRATION

After the CS5516/20 is reset, the device is func-
tional and can perform measurements without
being calibrated. The converter will utilize the
initialized values of the calibration registers to
calculate output words.

The converter uses the two outputs (AIN &
VREF) of the dual channel converter along with
the contents of the calibration registers to com-
pute the conversion data word. The following
equation indicates the computation.

[

AIN

VREF

]

Where R0 is the output data, D

AIN

and D

VREF

are the digital output words from the AIN and
VREF digital filter channels, and R1, R2, R3
and R4 are the contents of the following calibra-
tion registers:

R1 = AIN non-ratiometric offset
R2 = VREF non-ratiometric offset
R3 = AIN ratiometric offset
R4 = Gain

The computed output word, R0, is a two's com-
plement number.

Calibration minimizes the errors in the converted
output data. If calibration has not been per-
formed, the measurements will include offset
and gain errors of the entire system.

The converter may be calibrated each time it is
powered up, or calibration words from a pre-
vious calibration may be uploaded into the
appropriate calibration registers from some type
of E

PROM by the system microcontroller.

The converter uses five different registers to
store specific calibration information. Each of
the calibration registers stores information perti-
nent to correcting a specific source of error
associated with either the converter or with the
input transducer and its wiring. The method by

CS5516, CS5520

DS74F1

which calibration is initiated is common to each
of the calibration registers. The configuration
register controls the execution of the calibration
process. Bits CC3--CC0 in the configuration
register determine which type of calibration will
be performed and which of the five calibration
registers will be affected. On the falling edge of
the 24th SCLK, the configuration word will be
latched into the configuration register and the se-
lected calibration will be executed. The time
required to perform a calibration is listed in Ta-
ble 3. The DRDY pin will remain a logic 1
during calibration, and will go low when the
calibration step is completed.

The serial port should not be accessed while a
calibration is in progress. The EC bit of the
configuration register remains a logic 1 until it is
overwritten by a new configuration word (EC =
0). Consequently, if EC is left active, any write
(the falling edge of the 24th SCLK) to any regis-
ter inside the converter will cause a re-execution
of the calibration sequence. This occurs because
the internal microcontroller executes the contents
of the configuration register every time the 24th
SCLK falls after writing a 24-bit word to any
internal register. To be certain that calibrations
will not be re-executed each time a new word is
written or read via the serial port, the EC bit of
the configuration register must be written back
to a logic 0 after the final calibration step has
been completed.

The CC3--CC0 bits of the configuration register
determine the type of calibration to be per-

formed. The calibration steps should be per-
formed in the following sequence. If the user
determines that non-ratiometric offset calibra-
tion is important, the non-ratiometric offset
errors of the VREF and AIN input channels
should be calibrated first. Then the ratiometric
offset of the AIN channel should be calibrated.
And finally, the AIN channel gain should be
calibrated.

Non-ratiometric Errors

T o c alibra te out the VREF and AIN
non-ratiometric errors, the input channels to the
VREF path into the converter and the AIN path
into the converter must be grounded (this may
occur at the pins of the IC, or at the bridge exci-
tation as shown in Figure 3.). Then the EC,
CC2 and CC3 bits of the configuration register
must be set to logic 1. The converter will then
perform a non-ratiometric calibration and place

Configuration Register

CAL Type

Calibration Time

CC3

CC2

CC1

CC0

VREF Non-ratiometric Offset

573,440/fclk

AIN Non-ratiometric Offset

573,440/fclk

AIN Ratiometric Offset

2,211,840/fclk

AIN System Gain

573,440/fclk

VREF & AIN Non-ratiometric Offset

573,440/fclk

End Calibration

DRDY remains high through calibration sequence. In all modes, DRDY falls immediately upon completion of the calibration
sequence.

Table 3. CS5516/CS5520 Calibration Control

VREF+

VREF-

AIN+

AIN-

BX1

BX2

1A*

1B*

CS5516
CS5520

*Note: The bridge can be grounded with a

relay or with jumpers to perform
non-ratiometric calibration.

Figure 3. Non-ratiometric System Calibration using

Internal Excitation

CS5516, CS5520

DS74F1

the proper 24 bit calibration words in the VREF
and AIN non-ratiometric registers. Note that the
two non-ratiometric offsets can be calibrated si-
multaneously or independently, but they must be
calibrated prior to the other calibration steps if
non-ratiometric offset calibration is to be used. If
the effects of the non-ratiometric errors are not
significant enough to affect the user application,
they can be left uncalibrated (after a reset, the
non-ratiometric offset registers will contain
000000(H)).

Ratiometric Offset

Once the non-ratiometric errors have been cali-
brated, the ratiometric offset error of the AIN
channel should be calibrated next. To perform
this calibration step, a reference voltage must be
applied to the VREF+ and VREF- pins. Then,
place "zero" weight on the scale platform. This
will result in an offset voltage into the converter
which will represent the offset of the bridge, the
wiring, and the AIN input of the converter itself.
A configuration word with the EC and CC1 bits
set to logic 1 is then written into the configura-
tion register. During the ratiometric offset
calibration of AIN the microcontroller first uses
a successive approximation algorithm to com-
pute the correct values for the DAC3-DAC0 bits
of the DAC register. This accommodates any
large offsets on the AIN input signal. Once the
four DAC bits are computed, this amount of off-
set is removed from the input signal. The
microcontroller then computes the appropriate
24 bit number to place in the AIN ratiometric
offset register to calibrate out the remaining off-
set not removed by the DAC.

Gain

After the AIN ratiometric offset has been cali-
brated, the next step is to perform a gain
calibration. Gain calibration is performed with
"full scale" weight on the scale platform. The
EC and CC0 bits of the configuration register
are set to logic 1. The gain calibration of the
AIN channel is the final calibration step. After

DRDY falls to signal the completion of this cali-
bration step, the EC bit of the configuration
register must be set back to logic 0 to terminate
the calibration mode.

Limitations in Calibration Range

There are five calibration registers in the con-
verter. There are two non-ratiometric offset
calibration registers, one for the AIN input and
one for the VREF input; one 4-bit offset trim
DAC; one ratiometric offset calibration register
for the AIN input; and one gain calibration reg-
ister. After the non-ratiometric offsets are
calibrated, an LSB in either of the 24-bit non-ra-
tiometric calibration registers represents 2

-23

proportion of an internally-scaled MDRV
(Modulator Differential Reference Voltage). At
the MDRV+ and MDRV- pins, the MDRV has a
nominal value of 3.75 volts. This voltage is in-
ternally scaled to a nominal 2.5 volts (never less
than 2.4 volts) for use with the non-ratiometric
calibration. The two non-ratiometric calibration
words are stored in 2's complement form with
one count equal to slightly less than 300 nV at
the input of the internal A/D converter. For the
AIN channel this will be scaled down by the
gain of the instrumentation amplifier (X25) and
the PGA gain. For a PGA gain = 1, one count of
a non-ratiometric register will represent slightly
less than 12 nV. Non-ratiometric offset at the
VREF input cannot exceed

2.4 volts to be

within calibration range of the converter. Non-
ratiometric offset to be calibrated by the AIN
channel cannot exceed

2.4 volts divided by the

channel gain. With a PGA gain = 1, the maxi-
mum non-ratiometric offset which can be
calibrated on the AIN channel cannot exceed

96 mV.

When the ratiometric offset is calibrated, the 4-
bit DAC coarsely trims offset from the analog
signal. The ratiometric offset which remains is
finely trimmed after the signal has been con-
verted; using the contents of the ratiometric
offset register for digital correction. The DAC

CS5516, CS5520

DS74F1

bits can be manipulated by the user to add or
subtract offset up to 200 percent of the nominal
input signal. The AIN ratiometric offset register
can be manipulated to add or subtract offset
equal to the maximum differential input signal
into the X25 amplifier. An LSB in the ratiomet-
ric offset register represents 2

-23

proportion of

the voltage input across the VREF+ and VREF-
pins at the internal input to the AIN channel
A/D converter. This will be scaled down by the
AIN channel gain when calculated relative to the
instrumentation amplifier input. For example,
with a VREF = 2.5 V, the PGA gain = 1, one
count of the ratiometric offset register would
represent about 12 nV at the instrumentation am-
plifier input. The proportion remains ratiometric
even if the VREF voltage should change. The
24-bit register content is stored in 2's comple-
ment form.

Manipulation of the DAC or ratiometric offset
register allows the user to shift the transfer func-
tion to allow for load cell creep or load cell zero
drift.

The gain calibration is performed last. The con-
tents of the gain register spans from 2

-23

to 2 as

shown in Table 4. After gain calibration has
been performed, the numeric value in the gain
register should not exceed the range of 0.8 to
1.2. The gain calibration range is

20 % of the

nominal value of 1.0. The nominal value of 1.0
is for an input span dictated by the VREF volt-
age, the PGA gain, and the X25 instrumentation
gain. The converter may operate with gain slope
factors from 0.5 to 2.0 (decimal), but when the
slope exceeds 1.2 the converter output code
computation may lack adequate resolution and
result in missing codes in the transfer function.
Internal circuitry may saturate for large signals
which would calibrate to a gain factor less than
0.8.

In a typical weigh scale application, the
CS5516/CS5520 will be calibrated in combina-
tion with a load cell at the factory. Once
calibrated, the calibration words are off-loaded
from the converter and stored in E

PROM.

When powered-up in the field the calibration
words are up-loaded into the appropriate regis-
ters. This is viable because the AIN and VREF
input to the converter are "chopper-stabilized"
and maintain excellent stability when subjected
to changes in temperature.

Programmable Gain Amplifier

The programmable gain amplifier inside the
CS5516/20 offers gains of 1, 2, 4, and 8. This is
in addition to the fixed gain of

25 in the input

instrumentation amplifier. The gain tracking of
the PGA is about one percent between ranges.
The user can remove this error by performing a
gain calibration at the factory with a full scale
signal on each range. The gain calibration word
for each gain range can be off-loaded into
E

PROM and uploaded into the gain register

whenever a new gain setting is selected for the
PGA. Gain stability over temperature for the
converter itself is approximately 1 ppm/

C when

the device is used ratiometrically.

Serial Interface Modes

The CS5516/20 support either 5, 4 or 3 pin se-
rial interfacing. The SMODE pin sets the
operating mode of the serial interface. With
SMODE = 0, the device assumes the user is op-
erating with either a 5 or 4 wire interface. The
five wire mode includes SOD, SID, SCLK,
DRDY, and CS. In the four wire mode, CS is
connected to DGND as a logic 0. The user
would then interface to the SOD, SID, SCLK,
and DRDY pins.

CS5516, CS5520

DS74F1

AIN and VREF Non-Ratiometric Offset Registers

MSB

LSB

-1

-2

-3

-4

-5

-18

-19

-20

-21

-22

-23

Reset (R)

One LSB represents 2

-23

proportion of the internal MDRV (

2.5 Volts)

DAC Register

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

DAC3

DAC2

DAC1

DAC0

EXC

D16

U/B

D12

Reset (R)

D11

D10

A/S

CC3

CC2

CC1

CC0

Reset (R)

BIT

NAME

VALUE

FUNCTION

DAC3

DAC Sign Bit

0
1

Add Offset
Subtract Offset

DAC2-0

DAC Bits

000
001
010
011
100
101
110
111

25% Offset
50% Offset
75% Offset
100% Offset
125% Offset
150% Offset
175% Offset

Bits
D19 to D0

These bits mirror the

read only

Configuration Register

Note: 1. Reset State

2. A write to these bits does not change the register bit values.

AIN Ratiometric Offset Register

MSB

LSB

-1

-2

-3

-4

-5

-18

-19

-20

-21

-22

-23

Reset (R)

One LSB represents 2

-23

proportion of the voltage [<(VREF+) - (VREF-)>/GAIN] where GAIN = 25 X PGA Gain

GAIN Register

MSB

LSB

-1

-2

-3

-4

-5

-18

-19

-20

-21

-22

-23

Reset (R)

The gain register span from 0 to (2-2

-23

). After Reset the MSB=1, all other bits are 0.

Table 4. Calibration Registers

CS5516, CS5520

DS74F1

Reading a register in the converter requires a
command word to be written to the SID pin.
For example, to read the conversion data regis-
ter, the following command sequence should be
performed. First, the command word 88(H)
would be issued to the port. In the 5 wire inter-
face mode, this would involve activating CS
low, followed by 8 SCLKs (note that SCLK
must always start low and transition from low to
high to latch the transmit data, and then back
low again) to input the 8-bit command word. CS
must be low for the serial port to recognize
SCLKs during a write or a read, but it is actually
the first rising SCLK during command time that
gives the user control over the port. After writ-
ing the command word, the user must pause and
wait until the CS5520 presents the selected reg-
ister data to the serial port. The DRDY signal
will fall when the data is available. When read-
ing the conversion data register, it may take up
to 112,000 XIN clock cycles for DRDY to fall
after the 88(H) command word is recognized.
See Figure 4 for an illustration of command and
data word timing.

The conversion data register is actually the accu-
mulator of the post-processor which computes
the output data. At the end of each filter convo-
lution cycle, the internal microcontroller checks
to see if a read conversion data register com-
mand has been interpreted. If so, it transfers the
accumulator result to the serial port.

Whenever registers other than the conversion
data register are read, the DRDY pin will fall
within 256 XIN clock cycles (62.5

s with

XIN = 4.096 MHz) after the command word is
recognized. When DRDY falls, 24 SCLKs are
then issued to the port to read the 24-bit output
data word. DRDY will return high after all 24
bits have been clocked out. The SOD pin will be
in a Hi-Z state whenever CS is high, or after all
24 output data bits have been clocked out of the
port.

The CS5516/20 is designed such that it can out-
put conversion data words continuously, without
issuing a new command word prior to each data
read. Under the following circumstances, con-
tinuous conversion data can be read from the
port after issuing only one 88(H) command
word. Once the command to read the conversion
data register is issued, DRDY must be allowed
to go low, after which 24 SCLKs are issued to
read the data. This will cause DRDY to return
high.

The converter will continue to output conversion
words at the update rate as long as a different
command word is not started prior to DRDY
falling again. The user is not required to read
every output word to remain in the continuous
update mode. DRDY will toggle high, and then
low as each new output word becomes available.
If a command word is issued immediately after a
data word is read, the converter will end the read
conversion mode. Figure 5 illustrates the con-
tinuous data mode.

The user should perform all data reads and com-
mand writes within 51,000 XIN clock cycles
after DRDY falls to avoid ambiguity as to who
controls the serial port.

If SMODE = 1 (tied to VD+), the interface oper-
ates as a 3 wire interface using only SOD, SID,
and SCLK. In the 3 wire mode CS must be tied
to DGND. DRDY operates normally but is not
used. Instead, the DRDY signal modifies the
behavior of the SOD signal, allowing it to signal
to the user when data is available. To read data
from the converter requires a command word to
be written to the SID pin. The SOD output is
normally high (never Hi-Z). When output data
is available, the SOD signal will go low. The
user would then issue 8 SCLKs to the SCLK pin
to clear this data ready signal. On the falling
edge of the 8th SCLK the SOD pin will present
the first bit of the 24-bit output word. 24 SCLKs
are then issued to read the data. Then SOD will
go high. SID should remain low whenever the

CS5516, CS5520

DS74F1

SID pin is not being written. When reading
SOD, SCLK cannot be continuous but must
burst one clock cycle per bit.

The continuous read conversion data mode is
also functional in the 3-wire interface mode. Is-
sue one 88(H) command word to the converter.
Then wait for SOD to go low. Issue 8 SCLKs to
clear the data ready function. The MSB data bit
will then appear on the SOD pin. Issue 24
SCLKs to read the conversion word. At the fall-
ing edge of the 24th SCLK SOD will return
high. SOD will go low at the next DRDY falling
time to indicate a new conversion word. Eight
SCLKs must again be issued to clear the data
ready function before clocking out the data con-
version word. The SOD pin will continue to
toggle low each time a word is available even if
the conversion data is not read. To terminate the
continuous conversion mode, input an 8-bit com-
m a n d w o r d i mm ed i at el y aft er r e adi n g a
conversion word.

The user should perform all data reads and com-
mand writes within 51,000 XIN clock cycles
after SOD falls to avoid ambiguity as to who
controls the serial port.

Serial Port Initialization

If for any reason the off-chip microcontroller
fails to know whether the serial port of the
CS5516/20 is in data mode or command mode,
the following initialization procedure can be is-
sued to the port to force the CS5516/20 into the
command mode. Write 128 or more 1's to the
SID pin. Then issue a single 0 to the SID pin.
The port will then be initialized into the com-
mand mode and will be waiting for an 8-bit
command word.

Bridge Excitation Options

The CS5516/CS5520 A/D converters are opti-
mized for Wheatstone bridge applications. The
converters support either dc or ac (switched dc)
bridge excitation.

DC Bridge Excitation

The CS5516/CS5520 can be configured for dc
bridge excitation in either of two ways. The
EXC bit of the configuration register can be set
for either internal or for external excitation. If
set to internally-controlled mode (EXC = 0), the
F1 and F0 bits must be set to logic 0s. In this
condition, the bridge can be excited from a dc
supply with a resistor divider to develop the ap-
propriate reference voltage for the VREF+ and
VREF- pins. Note that the bridge excitation

8 Data Bits

24 Data Bits

SCLK

SID

DRDY

SOD

24 Data Bits

8 SCLKs

24 SCLKs

Port Access Period

Valid 51,000

XIN Clock Cycles

81,920 XIN

Clock Cycles

Figure 5. Continuous Read Conversion Data Mode (4 or 5 Wire)

CS5516, CS5520

DS74F1

s h o u l d n o t b e a p p l i e d p r i o r to t h e
CS5516/CS5520 being powered-up. With EXC,
F1, and F0 set to logic 0, the BX1 output will be
logic 0 (0 volts) and the BX2 output will be a
logic 1 (+5 volts).

A second method for configuring the converter
for dc excitation is by setting EXC = 1, and
pulling up BX1 (pin 12) to VD+ (pin 20)
through a resistor. This sets the converter for
use with external excitation which uses the
BX1 pin as an input to set the excitation fre-
quency. With B X1 = VD + , t h e e x t erna l
excitation frequency is zero, or dc.

AC Bridge Excitation

AC bridge excitation involves using a clock sig-
nal to generate a square wave which repetitively
reverses the excitation polarity on the bridge. To
excite the bridge dynamically requires some type
of bridge driver external to the CS5516/CS5520
converter. This driver is driven by a square wave
clock. The source of this clock depends upon
whether the converter is set for internal excita-
t ion o r for ex tern al excitatio n. Figure 6
illustrates a sample bridge drive circuit when op-
erating in the internal AC excitation mode.

Using internal excitation involves setting the
EXC bit of the configuration register to 0, and
setting the F1 and F0 bits to select the excitation
frequency for the bridge. In this mode the exci-
tation frequency is a sub-multiple of the XIN
clock frequency. The excitation clock is output

from the BX1 and BX2 pins of the converter in
the form of a two-phase non-overlapping clock.
The converter is capable of demodulating this
clocked excitation. But only if the signals into
the AIN+ and VREF+ pins of the converter are
in phase with the demodulation clock inside the
converter (see Figure 7). The non-overlapping
clock signals from BX1 and BX2 are CMOS
level outputs (0 to VD+ volts) and are capable
of driving one TTL load. A buffer amplifier
MUST be used to drive the bridge.

Whenever the internal mode is used for dynamic
bridge excitation the signals are non-overlap-
ping. The non-overlapping time is one XIN
clock cycle.

The converter can also be configured to provide
dynamic bridge excitation when operating in the
external-controlled bridge excitation mode. With
the EXC bit of the configuration register set to
logic 1, the BX1 pin becomes an input which
determines the bridge excitation frequency and
phase. BX1 should be near 50% duty cycle. The
user can select the excitation frequency with the
following restrictions. The excitation frequency
must be synchronous with the XIN frequency of
the converter and must be chosen using the fol-
lowing equation:

exc

(

XIN

)

81,920

where N is an integer and lies in the range in-
cluding 1 to 160. F

exc

is the desired bridge

excitation frequency. Other asynchronous fre-

0.1

-5V

+5V

100 k

-5V

10 k

MICREL
MIC4428 or
MIC4425

BX2

+5V

TP0610

EXC+

EXC-

+5V

-5V

+5V

-5V

Figure 6. Sample AC Bridge Driver

BX1 (Out)

BX2 (Out)

Demod Clock

(Internal)

Note: The signals from the bridge into AIN+ and

VREF+ of the converter must be in phase
with the demodulation clock.
t is 1 cycle of XIN clock.

Figure 7. Internal Excitation Clock Phasing

CS5516, CS5520

DS74F1

quencies are possible but may introduce a jitter
component in the BX output signals. It is de-
sirable not to choose an excitation frequency
where interference components are present,
such as 50 Hz or 60 Hz or their harmonics. The
XIN frequency can be divided down using a
counter IC external to the A/D converter. F

exc

would be input to the BX1 pin of the converter
to synchronize the internal operations of the am-
plifiers and synchronous detection circuitry and
to generate a clock output from the BX2 pin.
The BX2 output is then used to drive the bridge
amplifier with a signal of proper phase for detec-
tion by the converter. Figure 8 indicates the
necessary phase of the signals to ensure proper
demodulation.

Whenever the dynamic excitation clock output
from either the BX1 and BX2 pins (during inter-
nal excitation) or from the BX2 pin (during
external excitation) changes states, the converter
waits 64 XIN cycles before sampling the AIN
and VREF signal inputs. The delay allows some
time for the signal to settle from the modulation
event.

Input Filtering

Some load cells are located a distance from the
input to the converter. Under these conditions,
separate twisted pair cabling is recommended for
the excitation drive to the bridge, the excitation
sense leads (if used), and for the AIN

±/-

signal leads. If the AIN+/AIN- leads to the con-

verter and the VREF+/VREF- leads to the con-
verter are filtered, care should be exercised in
the choice of components. With either dc or ac
excitation, one should limit any input filtering
resistors on AIN to below 1 k

. Values greater

than this will degrade noise performance of the
converter. In ac excitation applications, any fil-
tering must be broadband enough that the
switched dc excitation signal can settle within 10

secs. Failure to meet this settling requirement

will affect measurement accuracy. Figure 9 illus-
trates acceptable filter components for ac
excitation. If only differential filtering is re-
quired, a single capacitor can be placed between
AIN+ and AIN- (and VREF+ and VREF-) in
place of two capacitors to ground.

Voltage Reference Considerations

The CS5516/20 include an on-chip voltage refer-
ence which is output on the MDRV- and
referenced from the MDRV+ pin. The converter
is designed to be operated as a ratiometric meas-
urement device. The 2-channel delta-sigma
converter uses the internal MDVR (Modulator
Differential Voltage Reference) as its reference.
Since the MDVR is used for converting both the
AIN and VREF signals at the same time, the ab-
solute value of the MDVR and its tempco are
not important when the CS5516/20 is used in the
ratiometric measurement mode. The voltage ref-
erence output, MDVR-, should be decoupled
using a 1

F capacitor which is connected to the

MDRV+ supply line. Voltage reference decou-

BX1 (In)

BX2 (Out)

Demod Clock

(Internal)

Note: The signals from the bridge into AIN+ and

VREF+ of the converter must be in phase
with the demodulation clock.
t

64/XIN

Figure 8. External Excitation Clock Phasing

CS5516

CS5520

VREF+

VREF-

AIN+

AIN-

470 pF

7.5k

EXC+

EXC-

0.0047

300

AIN+

AIN-

Figure 9. AIN and VREF Input Filter Components

CS5516, CS5520

DS74F1

pling is shown on the system connection dia-
grams.

If absolute measurements are to be made by the
CS5516/20, then a precision reference should be
input into the VREF+ and VREF- terminals.

Clock Generator

The CS5516/20 includes a gate which can be
connected as a crystal oscillator to provide the
master clock to run the chip. Alternatively, an
external (CMOS compatible) clock can be input
into the XIN pin. Figure 10 illustrates a simple
model for the on-chip gate oscillator. The on-
chip oscillator is designed to typically operate
with crystal frequencies between 4.0 and 5.0
MHz without additional loading capacitors. If
other crystal frequencies, or if ceramic resona-
tors are used, additional loading capacitance may
be necessary.

The XOUT pin can be used to drive one CMOS
gate for system clock requirements. Be sure to
include the gate's input capacitance and stray ca-
pacitance as part of the loading capacitance for
the resonating element.

Digital Filter

The CS5516/20 is optimized to operate with clock
frequencies of 4.096 MHz or 4.9152 MHz. These
result in the filter having a 3dB bandwidth of 12
Hz or 15 Hz, with output word rates of 50 or
60Hz. The rejection at 50Hz

3Hz is 70 dB mini-

mum with a 4.096 MHz clock. Similar rejection is
obtained at 60 Hz with a 4.9152 MHz clock.

The digital filter has a deep notch in its transfer
function at 50 Hz (XIN = 4.096 MHz) or 60 Hz
(XIN = 4.9152 MHz) but other XIN frequencies
can be used. The filter transfer function will
scale proportionally. Figure 11 shows the trans-
fer function of the filter when operated at three
different frequencies. With a 3.579 MHz XIN,
the filter offers greater than 90 dB rejection of
both 50 and 60 Hz.

The output word rate of the converter scales
with the XIN clock rate and is set by the ratio of
XIN/81,920; or 50 Hz for XIN = 4.096 MHz. If
very narrow signal bandwidths, such as 3 Hz,
are desired, averaging of the output words is rec-
ommended.

>1M

To Internal circuitry

400

XOUT

5pF

1pF

400

External XTAL

1pF

5pF

XIN

2000 umhos

Figure 10. On-Chip Gate Oscillator Model

Input Frequency (Hz)

-160

-140

-120

-100

-80

-60

-40

-20

agnit

ude (dB)

(1) XIN = 3.579 MHz
(2) XIN = 4.096 MHz
(3) XIN = 4.915 MHz

0
0
0

21.8

25
30

43.7

50
60

87.3

100
120

131.0

150
180

174.7

200
240

218.5

250
300

Figure 11. Filter Magnitude Response

Input Frequency (Hz)

-180

-150

-120

-90

-60

-30

120

150

180

e (d

egre

)

XIN = 4.096 MHz

Figure 12. Filter Phase Response.

CS5516, CS5520

DS74F1

The digital filter computes a new output data
word every 81,920 XIN clock cycles. If the in-
put experiences a large change in amplitude, the
PGA gain is changed, or the DAC calibration
registers are changed, it may take up to six filter
cycles (81,920 X 6 clock cycles) for the filter to
compute an output word which is fully settled to
the input signal.

Output Coding

The CS5516/20 converters output data in binary
format when operating in unipolar mode and in
two's complement when operating in bipolar
mode. Table 5 illustrates the output coding for
the converters. Note that when reading conver-
sion data from the converter the data word is
output MSB or sign bit first. Falling edges on
SCLK advance the data word to the next lower
bit.

The output conversion words from both the
CS5516 and the CS5520 are 24 bits long. The
CS5516 has 16 data bits followed by 8 flag bits
(all identical). The CS5520 has 20 data bits fol-
lowed by 4 flag bits (all identical). To read the
conversion data, including the error flag infor-
mation will require at least 17 SCLKs for the
CS5516 and at least 21 SCLKs for the CS5520.

Under normal operating conditions, the flag bits
will be zeroes. The flag bits will be set to all
ones whenever an overrange condition exists.
Under large overrange conditions where the in-
put signal exceeds the nominal full scale input
by approximately two times (for example:
50 mV input when the nominal full scale input
is set-up for 25 mV), the converter may be un-
able to compute a proper output code. In this
condition flag bits will be set to all 1s but the
conversion data may be a value other than full
scale plus or minus.

After the converter is first powered-up, a RST is
issued, or the device comes out of the SLEEP
mode, the first conversion data read may
erroneously have its error flag bits set to "1".

Synchronizing Multiple Converters

Multiple converters can be made to output their
conversion words at the same time if they are
operated from the same clock signal at XIN. To
synchronize multiple converters requires that
they all have their RF bit of the configuration
register written to a logic 1 and then back to 0.
The filters will be allowed to start convolutions
after the falling edge of the 24th SCLK used to
write the RF bit to the configuration register.

Unipolar Input

Voltage

Offset

Binary

Bipolar Input

Voltage

Two's

Complement

Unipolar Input

Voltage

Offset

Binary

Bipolar Input

Voltage

Two's

Complement

>(VFS-1.5 LSB) FFFF

>(VFS-1.5 LSB)

7FFF

>(VFS-1.5 LSB) FFFFF >(VFS-1.5 LSB)

7FFFF

VFS-1.5 LSB

FFFF

-----

FFFF

VFS-1.5 LSB

7FFF

-----

7FFE

VFS-1.5 LSB

FFFFF

-----

FFFFE

VFS-1.5 LSB

7FFFF

-----

7FFFE

VFS/2-0.5 LSB

8000

-----

7FFF

-0.5 LSB

0000

-----

FFFF

VFS/2-0.5 LSB

80000

-----

7FFFF

-0.5 LSB

00000

-----

FFFFF

+0.5 LSB

0001

-----

0000

-VFS+0.5 LSB

8001

-----

8000

+0.5 LSB

00001

-----

00000

-VFS+0.5 LSB

80001

-----

80000

<(+0.5 LSB)

0000

<(-VFS+0.5 LSB)

8000

<(+0.5 LSB)

00000 <(-VFS+0.5 LSB)

80000

CS5516 Output Coding

CS5520 Output Coding

Note: VFS in the table equals the full scale voltage between +VREF/(G x 25) and ground for unipolar mode; and

between

VREF/(G x 25) for bipolar mode. The signal input to the A/D section of the converter has been

amplified by the instrumentation amplifier (x25) and the PGA gain, G (1, 2, 4, or 8). See text about error
flags under overrange conditions.

Table 5. Output Coding for the CS5516/20 Converters.

CS5516, CS5520

DS74F1

The filter will start a new convolution on the
next rising edge of the XIN clock after the 24th
SCLK falls.

Sleep Mode

The CS5516/20 configuration register has an
A/S bit which allows the users to put the device
in a sleep condition to lower quiescent power.
Upon reset the A/S bit device is set to a logic 0
which places the device in the 'awake' condi-
tion. Writing a 1 to the A/S bit will shutdown
most of the chip, including the oscillator. It is
desirable to use the following sequence when
coming out of sleep. Write a logic 0 to the A/S
bit of the configuration register. In the same
configuration word write a logic 1 to the RF bit
of the configuration register. Then wait until it is
certain that the oscillator has started. After the
oscillator has started or a clock present on the
XIN pin, set the RF bit back to 0. The user
should then wait at least 6 output word update
periods before expecting a valid output data
word.

Noise Performance

Typical noise performance for the converter is
listed in the specification tables for each PGA
gain. Figure 13 illustrates a noise histogram for
1000 output conversions from the CS5520. The
data for the histogram was collected using the
CDB5520 evaluation board; with VREF at 2.5
volts, PGA = 4, bipolar mode. The data shows
the standard deviation of the data set is 3.2
LSBs. One LSB is equivalent to [VREF X 2(bi-
polar)]/ [Inst amp gain X PGA gain X number
of codes] or (2.5 X 2)/ (25 X 4 X 2E20) = 47.7
nV. One standard deviation is equivalent to rms
if the data is Normal or Gaussian. The rms noise
presented by the plot is 153 nV, which is in
good agreement with the typical noise specifica-
tion of 150 nV for a PGA gain of 4.

Applications

See the Application Notes section of the databook.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

100

120

140

0 1 2 3 4 5 6 7 8

-1

-2

-3

-4

-5

-6

-7

-8

Figure 13. CS5520 Noise Histogram.

CS5516, CS5520

DS74F1

PIN DESCRIPTIONS

Power Supply Connections

VD+ - Positive Digital Power, PIN 20.

Positive digital supply voltage. Nominally +5 volts.

VD- - Negative Digital Power, PIN 21.

Negative digital supply voltage. Nominally -5 volts.

DGND - Digital Ground, PIN 19.

Digital ground.

VA+ - Positive Analog Power, PIN 3.

Positive analog supply voltage. Nominally +5 volts.

VA- - Negative Analog Power, PIN 4.

Negative analog supply voltage. Nominally -5 volts.

AGND1, AGND2 - Analog Ground, PINS 5, 8.

Analog ground.

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 22, 23

An internal gate is connected to these pins enabling the use of either a crystal or a ceramic
resonator to provide the master clock for the device. Alternatively, an external (CMOS
compatible) clock can be input to the XIN pin as the master clock for the device.

Modulator Diff. Voltage Ref +

MDRV+

SMODE

Serial Interface Mode

Modulator Diff. Voltage Ref -

MDRV-

XOUT

Crystal Out

Positive Analog Power

VA+

XIN

Crystal In

Negative Analog Power

VA-

VD-

Negative Digital Power

Analog Ground One

AGND1

VD+

Positive Digital Power

Analog In +

AIN+

DGND

Digital Ground

Analog In -

AIN-

SOD

Serial Output Data

Analog Ground Two

AGND2

SID

Serial Input Data

Voltage Ref In +

VREF+

SCLK

Serial Clock Input

Voltage Ref In -

VREF-

DRDY

Data Ready

Bridge Excite 2

BX2

Chip Select

Bridge Excite 1

BX1

RST

Reset

CS5516, CS5520

DS74F1

Digital Inputs

RST - Reset, PIN 13.

Reset pin initializes all calibration registers to a known condition and places the serial port into
the command mode.

CS - Chip Select, PIN 14.

An input which can be enabled by an external device to gain control over the serial port. When
this pin is high, SOD is in a high impedance state if SMODE = 0.

SCLK - Serial Data Clock, PIN 16.

A clock signal at this pin determines the output rate of the data from the SOD pin and the input
data rate on the SID pin.

SID - Serial Input Data, PIN 17.

This pin is used for inputting command and configuration words or inputting calibration words.
Data is input at a rate determined by SCLK. SID is in a don't care state when no data is being
clocked in.

SMODE - Serial Interface Mode, PIN 24.

Selects the operating mode of the serial port. When low the serial port operates in the 5 or 4
wire interface mode. When high the chip will enter the 3 wire interface mode.

Analog Inputs

AIN+ and AIN- - Analog Inputs, PINS 6, 7.

The analog input signals from the transducer. These are true differential inputs.

VREF+ and VREF- - Voltage Reference Inputs, PINS 9,10.

These are the differential analog reference voltage inputs.

MDRV+ - Modulator Differential Voltage Reference, PIN 1.

Positive terminal of the internal differential voltage reference which can be tied to the positive
supply (VA+) or ground (AGND).

MDRV- - Modulator Differential Voltage Reference, PIN 2.

This is the -3.75V modulator differential voltage reference output and can be used to generate
an analog reference. Note this is with reference to the MDRV+ pin.

CS5516, CS5520

DS74F1

Digital Outputs

BX1 and BX2 - AC Bridge Excitation Signals, PINS 12, 11.

These can be buffered to drive the transducer or used as synchronizing signals for a transducer
drive circuit. BX1 and BX2 are 0 to +5V signals.

DRDY - Data Ready, PIN 15.

DRDY goes low every 81,920 cycles of XIN (when in read conversion data mode) to indicate
that new data has been placed in the output port. DRDY goes high when all the serial port data
is clocked out, when the serial port is being updated with new data, when a calibration is in
progress, or when the device is in SLEEP.

SOD - Serial Output Data, PIN 18.

Data from the serial port will be output from this pin at a rate determined by SCLK . The data
will either be conversion data, or, calibration values, dependent upon the command word that
has been previously input on the SID pin. The SOD pin furnishes a high impedance output
state when not transmitting data (SMODE = 0).

ORDERING GUIDE

Model Number

Linearity Error (Max)

Temperature Range

Package

CS5516-AP

0.003%

-40

C to +85

24-pin 0.3" Plastic DIP

CS5516-AS

0.003%

-40

C to +85

24-pin 0.3" SOIC

CS5520-BP

0.0015%

-40

C to +85

24-pin 0.3" Plastic DIP

CS5520-BS

0.0015%

-40

C to +85

24-pin 0.3" SOIC

CS5516, CS5520

DS74F1

SPECIFICATION DEFINITIONS

Linearity Error

The deviation of a code from a straight line which extends between two fixed points on the
A/D converter transfer function. In unipolar mode, the straight line extends from one point
located

LSB below the first code transition, one count above all zeros; to the second point

located

LSB beyond the code transition to all ones. In bipolar mode, the straight line extends

from one point located

LSB beyond the code transition to all ones, passing through a point

LSB below code 8000(H) (16-bit); 80000(H) (20-bit); extending to beyond negative full

scale. Units are in percent of full-scale.

Differential Nonlinearity

The deviation of a code's width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition form the ideal [{(VREF+)-(VREF-)}-

LSB]. Units

are in LSBs.

Unipolar Offset

The deviation of the first code transition from the ideal (

LSB above AGND) when in

unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset

The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (

LSB below

AGND) when in bipolar mode (BP/UP high). Units are in LSBs.

CS5516, CS5520

DS74F1

Cirrus Logic, Inc. 1998

Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com

CDB5516
CDB5520

CS5516 and CS5520 ADC Evaluation Board

Features

On-board microcontroller

RS232 Serial Communicationswith host PC

Supports either AC or DC bridge drive

On-board bridge driver

Supports ratiometric or absolute
measurements

Evaluation software included

Description

The CDB5516 and CDB5520 provide quick and easy
evaluation of the CS5516 and CS5520 bridge transducer
A/D converters. Direct connection of the bridge to the
evaluation board is provided.

The board also contains a microcontroller, with firmware
which allows the board to be controlled via simple serial
commands, using the RS232 communications port of a
PC.

ORDERING INFORMATION

CDB5516

Evaluation Board

CDB5520

Evaluation Board

VREF+

VREF-

AIN+

AIN-

Clock

Microcontroller

RS232

Driver/

Receiver

RS232

Connector

BX1

BX2

+5V

-5V

+5V

CS5516

CS5520

SCLK

SID

SOD

Load

Cell

Bridge

Excitation

MAR `95

DS74DB#

Introduction

The CDB5516/20 evaluation board provides a
means of testing the CS5516 and CS5520 bridge
transducer A/D converters. The board is de-
signed to be interfaced to a PC-compatible
computer via an RS-232 port. Software is sup-
plied with the board which provides control of
all registers in the CS5516 or the CS5520.

The board is configured to be operated from +5
and -5 volt power supplies. A bridge transducer
or a bridge transducer simulator is required if the
board is to be evaluated in the ratiometric oper-
ating mode.

Evaluation Board Overview

Figure 1 illustrates the schematic of the bridge
driver and A/D converter portion of the circuit
board. The converter operates from a 4 MHz
crystal. This results in the converter outputting
conversion words at a 50 Hz rate. The board
comes configured to be interfaced to a bridge
transducer via the 6-pin transducer terminal
block. The sense lines on the transducer termi-
nal block provide the reference voltage for the
converter.

For absolute measurements, the user can connect
either an external reference voltage (up to 3.8
volts) to the reference terminal block or connect
the on-board 2.5 volt LT1019 reference as the
voltage reference for the converter.

10k

-5VA

0.1

+5VA

301

4.7nF

470pF

MICREL
MIC4428

EXC

C20

C21

R14

R15

TP0610

R12

R11

C18

C19

LT1019-

2.5V

+5VA

5.0k

7.5k

0.1

C29

C14

0.1

VD+

BX1

XIN

XOUT

SMODE

SOD

SID

SCLK

DGND

VD-

0.1

10k

OSCLK

VA+ MDRV+ MDRV-

0.1

+5VA

BX2

VA-

DGND

AGND

-5VA

AIN+

AGND1

AGND2

AIN-

VREF+

VREF-

100k

CS5516/20

100k

4.000

MHz

R13

R17

R16

SMODE

SOD

SCL

DRD

SMODE

SOD

SID

SCLK

RST

DRDY

RST

0.1

C11

0.1

C10

SIG+

SIG-

SENSE+

SENSE-

EXC+

EXC-

4.7nF C15

REF+

REF-

301

Figure 2

EXC

GND

C16

C17

Figure 1. Bridge Driver and A/D Converter

CDB5516/CDB5520

DS74DB3

A bridge driver, composed of a Siliconix TP0610
transistor and a Micrel MIC4428 dual CMOS
driver, is provided which allows the BX2 output
from the CS5516 or CS5520 to provide either dc
or ac excitation to the bridge.

The digital interface pins of the A/D converter
connect to the microcontroller, or alternatively,
these connections can be cut, or the on-board
microcontroller can be removed, and the user's
own microcontroller can be interfaced to J1
header connector.

Figure 2 illustrates the Motorola 68HC705C8
microcontroller which reads or writes data into
the A/D converter and communicates with the

PC-compatible computer via the RS-232 inter-
face. The microcontroller derives its 4 MHz
clock from the A/D converter clock. The micro-
controller is configured to communicate over the
RS-232 link at 4800 baud, no parity, 8-bit data,
and 1 stop bit. A Motorola MC145407 RS-232
interface chip is used to send and recieve data to
the PC-compatible computer via the 25-pin Sub-
D connector.

Table 1 lists the commands sent to the microcon-
troller to write to or to read from the registers in
the A/D converter. If software other than that
provided with the evaluation board is used, the
format of the data transmitted over the RS232
line is as follow: Write commands are com-

Vpp

OSC2

OSC1

PA1

PD2

PD4

PD7

PA0

PA2

VDD

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PD3

0.1

RESET

IRQ

PD0

PD1

PC7 21

PC6 22

PC5 23

PC4 24

PC3 25

PC2 26

PC1 27

PC0 28

PA7

PA6

PA5

PA4

PA3

TCAP

TCMP

PD5

RESET

10k

+5VD

10k

470

Vss

68HC705C8

10k

C24

470

R20

C23

C22

SMODE

SOD

SCLK

DRDY

OSCLK

SID

RST

From
Figure 1

470

+5VD

TXD

RXD

RTS

CTS

DTR

DSR

DCD

10k

Vcc

C2+

VDD

C2-

+5VD

GND

Vss

C1+

C1-

Sub-D
25 Pin

C28

C27

R28

MC145407

C25

C26

RXD

TXD

Figure 2. Microcontroller and RS-232 Interface

CDB5516/CDB5520

DS74DB3

posed of one byte for command which is trans-
mitted with its LSB first. The command is
followed by three data bytes which make up the
24-bit word to be written to the selected register
of the A/D converter. The three bytes are trans-
mitted lowest order byte first (bits 7 - 0) with the
LSB of the byte transmitted first.

Figure 3 illustrates the power supply connections
to the evaluation board. Voltages of +5 and -5
analog and +5 digital are required.

Using the Evaluation Board

Prior to using the board to evaluate the CS5516
or CS5520 A/D converter, a good understanding
of the full potential of the converter is necessary.
It is recommended that the CS5516/CS5520 de-
vice data sheet be thoroughly read prior to
a t t em p t i n g t o u s e t h e ev al u at io n b o ar d .
The CS5516 or CS5520 bridge transducer A/D
converter actually contains two A/D converters.

One of the converters is used to convert the
VREF voltage input, and the other is used to
convert the AIN signal input. Both converters
utilize an on-chip voltage reference to perform
conversions of their respective inputs. Since
both converters use the same reference they
track one another. The digital processing logic
of the A/D converter depends on the presence of
both signals to properly compute a digital output
word. If the evaluation board is configured for
bridge measurement, and no bridge (load cell or
simulator) is connected to the bridge transducer
terminal block, the converter will output a code
of zero because no reference voltage is present
between the VREF+ and VREF- pins.

The span of the AIN input signal is determined
by a combination of the instrumentation ampli-
fier gain (X25), the programmable gain amplifier
(PGA) gain, the magnitude of the voltage be-
tween the VREF+ and VREF- input pins, and
the calibration words for gain and offset. For ex-

Register

Read

Write

Conversion Data Register

50(H)

Configuration Register

51(H)

D1(H)

DAC Register

53(H)

D3(H)

Gain Register

52(H)

D2(H)

AIN Ratiometric Offset Register

54(H)

D4(H)

AIN Nonratiometric Offset Register

55(H)

D5(H)

VREF Nonratiometric Offset Register

56(H)

D6(H)

Table 1. Microcontroller commands via RS-232

+5VD

0.1

+5VA

0.1

-5VA

-5V

+5V

AGND

DGND

Figure 3. Power Supplies

CDB5516/CDB5520

DS74DB3

ample, the board comes with a set of precision
resistors which divide the excitation supply
(nominally 10 volts total) down to 2.5 volts be-
tween the VREF+ and VREF- input pins. This
sets the nominal full scale voltage into the A/D
converter. The input span of the instrumentation
amplifier can be calculated to by knowing the
PGA gain setting, and that the gain of the instru-
mentation amplifier is X25. If the PGA is set for
a gain of 8, then the input span to the instrumen-
tation amplifier will be 2.5 volts (VREF+ -
VREF-) divided by 8 X 25, or 2.5/(200) = 12.5
millivolt nominal in unipolar mode. The device
can be then calibrated with an input voltage
which is as low as 20% less than nominal or up
to 20% greater than nominal. Therefore, with
this VREF+ - VREF- voltage (2.5 volts) and a
PGA gain of 8 the input span can be calibrated
to handle a span from a low of 10 mV to a high
of 15 mV. To modify the input span the user can
either change the PGA gain or modify the resis-
tor divider on the bridge sense voltage to yield
an appropriate value in the range of 2.0 to 3.8
volts. This makes the A/D converter quite flex-

ible in handling load cells with different output
levels. Whenever configured as a bridge
transducer device, the CS5516 or the CS5520
A/D converter operates in ratiometric measure-
ment mode. Figures 4 and 5 illustrate how to
connect 4-wire and 6-wire bridge transducers to
the board.

Alternatively, the CS5516 or CS5520 can be
configured for absolute measurement if a preci-
sion reference voltage is supplied between the
VREF+ and VREF- pins of the A/D converter.
The board can be modified to accept a reference
into the voltage reference terminal block; or the
on-board LT1019-2.5 volt reference can be used
as the reference voltage for the A/D converter.
To use either of these inputs will require that
jumper wires be soldered in either 1A-1B to se-
lect the external voltage reference input, or
2A-2B to select the on-board LT1019-2.5. Fig-
ure 6 illustrates the connection of an external
voltage reference to the evaluation board for ab-
solute voltage measurement applications. To
achieve an accurate reference voltage resistor R6

SIG +

SIG -

SENSE +

SENSE -

EXC +

EXC -

Figure 4. 4-Wire Bridge Connections

SIG +

SIG -

SENSE +

SENSE -

EXC +

EXC -

Figure 5. 6-Wire Bridge Connections

CDB5516/CDB5520

DS74DB3

must be removed from between the +VREF and
-VREF pins. It may be desirable to also remove
R5, R7, C16, and C17 in some applications.

Calibrating the A/D Converter

As explained in the CS5516/CS5520 data sheet,
the order in which the calibration steps are per-
formed are important. If one chooses to use the
non-ratiometric calibration capabilities of the
converter, the non-ratiometric errors of the
VREF and AIN channels should be calibrated
first. The non-ratiometric calibration steps can
be performed at the same time. Before the non-
ratiometric offset calibration is initiated, the
bridge should be grounded. This can be achieved
on the evaluation board by moving the two
jumpers at the output of the MIC4428 driver to
the GND position (see Figure 1). The converter
is then instructed via the configuration register
bits to perform the non-ratiometric calibration
steps. Once the non-ratiometric calibrations are
completed, ju mpers at th e output of the

MIC4428 driver should be returned to the EXC
position.

After the non-ratiometric calibration steps are
performed, the AIN ratiometric offset is then
calibrated. With "zero weight" on the load cell,
the converter is instructed via the configuration
register to perform the AIN ratiometric offset
calibration step. Finally, with "full scale weight"
on the load cell, the converter is instructed to
perform the gain calibration step.

The converter is then ready to perform conver-
sions.

Software

The evaluation board comes with software and a
RS-232 cable to interface the board to a RS-232
port of a PC-compatible computer. The software
diskette contains a README.TXT file which
explains its operation.

+5VD

0.1