Features

Provides Analog Transmission Line
Interface for T1 and E1 Applications

Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions

Fully Compliant with AT&T 62411
Stratum 4 Jitter Requirements

Low Power Consumption
(typically 175 mW)

B8ZS/HDB3/AMI Encoder/Decoder

14 dB of Transmitter Return Loss

General Description

The CS61574A and CS61575 combine the complete
analog transmit and receive line interface for T1 or E1
applications in a low power, 28-pin device operating
from a +5V supply. Both devices support processor-
based or stand-alone operation and interface with
industry standard T1 and E1 framers.

The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The
CS61574A has a receiver jitter attenuator optimized for
minimum delay in switching and transmission applica-
tions, while the CS61575 attenuator is optimized for
CPE applications subject to AT&T 62411 requirements.
The transmitter features internal pulse shaping and a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.

Applications

Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect

Interfacing Customer Premises Equipment to a
CSU

Building Channel Service Units

ORDERING INFORMATION - See page 26.

MAY '96

DS154F2

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

T1/E1 Line Interface

CS61574A

CS61575

TTIP

TCLK

RRING

RTIP

TRING

TGND

CONTROL

LINE RECEIVER

LINE DRIVER

RCLK

LLOOP
(SCLK)

(INT)

LEN0

(SDI)

LEN1

(SDO)

LEN2

(CLKE)

TAOS

MODE

TPOS

[TDATA]

RPOS

[RDATA]

RNEG

[BPV]

TNEG

[TCODE]

MTIP
[RCODE]

DPM
[AIS]

LOS

RV+

RGND

MRING
[PCS]

XTALIN

XTALOUT

ACLKI

( ) = Pin Function in

Host Mode

[ ] = Pin Function in

Extended Hardware Mode

RLOOP

(CS)

M
O

T
E

O
O

P
B
A

AMI,

B8ZS,

HDB3,

CODER

JITTER

ATTENUATOR

PULSE

SHAPER

CLOCK &

DATA

RECOVERY

SIGNAL

QUALITY

MONITOR

DRIVER

MONITOR

TV+

O
C

O
O

P
B
A

Crystal Semiconductor Corporation 1996

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min

Max

Units

DC Supply

(referenced to RGND, TGND=0V)

RV+

TV+

-
-

6.0

(RV+) + 0.3

V
V

Input Voltage, Any Pin

(Note 1)

RGND-0.3

(RV+) + 0.3

Input Current, Any Pin

(Note 2)

-10

Ambient Operating Temperature

-40

Storage Temperature

stg

-65

150

WARNING:Operations at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes:

1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND

can withstand a continuous current of 100 mA.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Units

DC Supply

(Note 3) RV+, TV+

4.75

5.0

5.25

Ambient Operating Temperature

-40

Power Consumption

(Notes 4,5)

290

350

Power Consumption

(Notes 4,6)

175

Notes:

3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.

Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.

5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line length at 5.0V.

DIGITAL CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

(Notes 7, 8)

PINS 1-4, 17, 18, 23-28

2.0

Low-Level Input Voltage

(Notes 7, 8)

PINS 1-4, 17, 18, 23-28

0.8

High-Level Output Voltage

(Notes 7, 8, 9)

IOUT = -40

PINS 6-8, 11, 12, 25

4.0

Low-Level Output Voltage

(Notes 7, 8, 9)

IOUT = 1.6 mA

PINS 6-8, 11, 12, 23, 25

0.4

Input Leakage Current (Except Pin 5)

Low-Level Input Voltage, PIN 5

0.2

High-Level Input Voltage, PIN 5

(RV+) - 0.2

Mid-Level Input Voltage, PIN 5

(Note 10)

2.3

2.7

Notes:

7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is

an open drain output and pin 25 is a tristate output.

8. This specification guarantees TTL compatibility (V

= 2.4V @ I

OUT

= -40

A).

9. Output drivers will drive CMOS logic levels into a CMOS load.

10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.

CS61574A CS61575

DS154F2

ANALOG SPECIFICATIONS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Min

Typ

Max

Units

Transmitter
AMI Output Pulse Amplitudes

(Note 11)

E1, 75

(Note 12)

E1, 120

(Note 13)

T1, FCC Part 68

(Note 14)

T1, DSX-1

(Note 15)

2.14

2.7
2.7
2.4

2.37

3.0
3.0
3.0

2.6
3.3
3.3
3.6

V
V
V
V

E1 Zero (space) level (LEN2/1/0 = 0/0/0)

1:1 transformer and 75

load

1:1.26 transformer and 120

load

-0.237

-0.3

-
-

0.237

0.3

V
V

Recommended Output Load at TTIP and TRING

Jitter Added During Remote Loopback

(Note 16)

10Hz - 8kHz
8kHz - 40kHz
10Hz - 40kHz
Broad Band

-
-
-
-

0.005
0.008
0.010
0.015

0.02

0.025
0.025

0.05

UI
UI
UI
UI

Power in 2kHz band about 772kHz

(Notes 11, 17)

12.6

17.9

dBm

Power in 2kHz band about 1.544MHz

(Notes 11, 17)

(referenced to power in 2kHz band at 772kHz)

-29

-38

Positive to Negative Pulse Imbalance

(Notes 11, 17)

T1, DSX-1
E1 amplitude at center of pulse
E1 pulse width at 50% of nominal amplitude

-5
-5

0.2

-
-

0.5

5
5

%
%

Transmitter Return Loss

(Notes 11, 17, 18)

51 kHz to 102 kHz
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz

14
10

-
-
-

dB
dB
dB

Transmitter Short Circuit Current

(Notes 11, 19)

mA RMS

Driver Performance Monitor
MTIP/MRING Sensitivity:
Differential Voltage Required for Detection

0.6

Notes: 11. Using a 0.47

F capacitor in series with the primary of a transformer recommended

in the Applications section.

12. Pulse amplitude measured at the output of a 1:1 or 1:1.26 transformer across a 75

load for

line length setting LEN2/1/0 = 0/0/0.

13. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120

load for line length

setting LEN2/1/0 = 0/0/0.

14. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100

load for

line length setting LEN2/1/0 = 0/1/0.

15. Pulse amplitude measured at the DSX-1 cross-connect across a 100

load for line length settings

LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0, or 1/1/1 using a 1:1.15 transformer and the length of #22 AWG,
ABAM, or equivalent cable specified in Table 3.

16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
17. Not production tested. Parameters guaranteed by design and characterization.
18. Return loss = 20 log

ABS((z

)/(z

-z

)) where z

= impedance of the transmitter, and

= impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0

and a 1:1 transformer terminated with a 75

load, or a 1:1.26 transformer terminated with a

120

load.

19. Measured broadband through a 0.5

resistor across the secondary of a 1:1.26 transformer

during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.

CS61574A CS61575

DS154F2

ANALOG SPECIFICATIONS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Min

Typ

Max

Units

Receiver
RTIP/RRING Input Impedance

50k

Sensitivity Below DSX (0dB = 2.4V)

-13.6

500

-
-

Data Decision Threshold

T1, DSX-1

(Note 20)

T1, DSX-1

(Note 21)

T1, FCC Part 68 and E1

(Note 22)

60
53
45

65
65
50

70
77
55

% of peak
% of peak
% of peak

Allowable Consecutive Zeros before LOS

160

175

190

bits

Receiver Input Jitter Tolerance

(Note 23)

10kHz - 100kHz
2kHz
10Hz and below

0.4
6.0

300

-
-
-

UI
UI
UI

Loss of Signal Threshold

(Note 24)

0.25

0.30

0.50

Notes: 20. For input amplitude of 1.2 V

to 4.14 V

21. For input amplitude of 0.5 V

to 1.2 V

and from 4.14 V

to RV+.

22. For input amplitude of 1.05 V

to 3.3 V

23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. The analog input squelch circuit shall operate when the input signal amplitude above ground on the

RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in
the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low.

CS61574A CS61575

DS154F2

ANALOG SPECIFICATIONS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%; GND = 0V)

Parameter

Min

Typ

Max

Units

Jitter Attenuator
Jitter Attenuation Curve Corner Frequency

(Notes 17, 25)

CS61574A
CS61575

-
-

6
3

-
-

Hz
Hz

CS61574A T1 Receiver Jitter Transfer

(Notes 25, 26)

Jitter Freq. [Hz]

Amplitude [UIpp]

100

500

10k, 40k

0.3

3.0

20
35
40
40

6.0

30
40
50
50

-
-
-
-
-

dB
dB
dB
dB
dB

CS61575 T1 Receiver Jitter Transfer

(Notes 25, 26)

Jitter Freq. [Hz]

Amplitude [UIpp]

100

500

10k, 40k

0.3

6.0

23
38
40
40

9.0

33
43
50
50

-
-
-
-
-

dB
dB
dB
dB
dB

CS61574A E1 Receiver Jitter Transfer

(Notes 26, 27, 28)

Jitter Freq. [Hz]

Amplitude [UIpp]

1.5

100

1.5

400

1.5

10k, 100k

0.2

3.0
6.0

20
30
35
35

6.0

12
32
40
45
45

-
-
-
-
-
-

dB
dB
dB
dB
dB
dB

CS61575 E1 Receiver Jitter Transfer

(Notes 26, 27, 28)

Jitter Freq. [Hz]

Amplitude [UIpp]

1.5

100

1.5

400

1.5

10k, 100k

0.2

6.0

12
22
30
35
35

12
18
29
39
45
45

-
-
-
-
-
-

dB
dB
dB
dB
dB
dB

Attenuator Input Jitter Tolerance

(Notes 17, 28)

(Before Onset of FIFO Overflow or Underflow Protection)

CS61574A
CS61575

138

-
-

UI
UI

Notes: 25. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of

measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000
Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 2

-1 PRBS data pattern.

26. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
27. Jitter measured at the demodulator output of an HP3785A (or equivalent) using a measurement

bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 2

-1 PRBS data pattern.

28. Jitter below 100 kHz and within the attenuator's input jitter tolerance is not translated or aliased to

other frequencies. Output jitter increases significantly when attenuator input jitter tolerance is
exceeded.

CS61574A CS61575

DS154F2

E1 SWITCHING CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol

Min

Typ

Max

Units

Crystal Frequency

(Note 26)

8.192000

MHz

TCLK Frequency

tclk

2.048

MHz

TCLK Pulse Width

(Note 29)

pwh2

150

340

ACLKI Duty Cycle

pwh3

pw3

ACLKI Frequency

(Note 30)

aclki

2.048

MHz

RCLK Duty Cycle

(Note 31)

pwh1

pw1

Rise Time, All Digital Outputs

(Note 32)

Fall Time, All Digital Outputs

(Note 32)

TPOS/TNEG (TDATA) to TCLK Falling Setup Time

su2

TCLK Falling to TPOS/TNEG (TDATA) Hold Time

RPOS/RNEG Valid Before RCLK Falling

(Note 33)

su1

100

194

RDATA Valid Before RCLK Falling

(Note 34)

su1

100

194

RPOS/RNEG Valid Before RCLK Rising

(Note 35)

su1

100

194

RPOS/RNEG Valid After RCLK Falling

(Note 33)

100

194

RDATA Valid After RCLK Falling

(Note 34)

100

194

RPOS/RNEG Valid After RCLK Rising

(Note 35)

100

194

T1 SWITCHING CHARACTERISTICS

(TA = -40

C to 85

C; TV+, RV+ = 5.0V

5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol

Min

Typ

Max

Units

Crystal Frequency

(Note 26)

6.176000

MHz

TCLK Frequency

tclk

1.544

MHz

TCLK Pulse Width

(Note 29)

pwh2

150

500

ACLKI Duty Cycle

pwh3

pw3

ACLKI Frequency

(Note 30)

aclki

1.544

MHz

RCLK Duty Cycle

(Note 31)

pwh1

pw1

Rise Time, All Digital Outputs

(Note 32)

Fall Time, All Digital Outputs

(Note 32)

TPOS/TNEG (TDATA) to TCLK Falling Setup Time

su2

TCLK Falling to TPOS/TNEG (TDATA) Hold Time

RPOS/RNEG Valid Before RCLK Falling

(Note 33)

su1

150

274

RDATA Valid Before RCLK Falling

(Note 34)

su1

150

274

RPOS/RNEG Valid Before RCLK Rising

(Note 35)

su1

150

274

RPOS/RNEG Valid After RCLK Falling

(Note 33)

150

274

RDATA Valid After RCLK Falling

(Note 34)

150

274

RPOS/RNEG Valid After RCLK Rising

(Note 35)

150

274

Notes: 29. The transmitted pulse width does not depend on the TCLK duty cycle.

30. ACLKI provided by an external source or TCLK.
31. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
32. At max load of 1.6 mA and 50 pF.
33. Host Mode (CLKE = 1).
34. Extended Hardware Mode.
35. Hardware Mode, or Host Mode (CLKE = 0).

CS61574A CS61575

DS154F2

Any Digital Output

t r

t f

10%

90%

Figure 1. Signal Rise and Fall Characteristics

RCLK

tpw1

tpwl1

tpwh1

HOST MODE
(CLKE = 1)

EXTENDED
HARDWARE
MODE OR

HARDWARE

HOST MODE
(CLKE = 0)

MODE OR

RCLK

RPOS
RNEG

su1

RDATA
BPV

Figure 2. Recovered Clock and Data Switching Characteristics

SWITCHING CHARACTERISTICS

(TA = -40

to 85

C; TV+, RV+ =

5%;

Inputs: Logic 0 = 0V, Logic 1 = RV+)

Parameter

Symbol

Min

Typ

Max

Units

SDI to SCLK Setup Time

SCLK to SDI Hold Time

cdh

SCLK Low Time

240

SCLK High Time

240

SCLK Rise and Fall Time

, t

CS to SCLK Setup Time

SCLK to CS Hold Time

cch

CS Inactive Time

cwh

250

SCLK to SDO Valid

(Note 36)

cdv

200

CS to SDO High Z

cdz

100

Input Valid To PCS Falling Setup Time

su4

PCS Rising to Input Invalid Hold Time

PCS Active Low Time

pcsl

250

Notes: 36. Output load capacitance = 50pF.

CS61574A CS61575

DS154F2

THEORY OF OPERATION

Enhancements in CS61575 and CS61574A

The CS61574A and CS61575 provide higher per-
formance and more features than the CS61574
including:

AT&T 62411, Stratum 4 compliant jitter at-
tenuation over the full range of operating
frequency and jitter amplitude (CS61575),

50% lower power consumption,

Internally matched transmitter output im-
pedance for improved signal quality,

Optional AMI, B8ZS, HDB3 encoder/de-
coder or external line coding support,

Receiver AIS (unframed all ones) detection,

ANSI T1.231-1993 compliant receiver
LOS (Loss of Signal) handling,

Transmitter TTIP and TRING outputs are
forced low when TCLK is static,

The Driver Performance Monitor operates
over a wider range of input signal levels.

Existing designs using the CS61574 can be con-
verted to the higher performance, pin-compatible
CS61574A or CS61575 if the transmit trans-
fo rmer is repl ace d by a p in-c ompat ibl e
transformer with a new turns ratio.

Understanding the Difference Between the
CS61575 and CS61574A

The CS61574A and CS61575 provide receiver
jitter attenuation performance optimized for dif-
ferent applications. The CS61575 is optimized to
attenuate large amplitude, low frequency jitter for
T1 Customer Premises Equipment (CPE) applica-
t io n s a s re qu i re d by AT&T 6 24 11 . Th e
CS61574A is optimized to minimize data delay in
T1 and E1 switching or transmission applications.
Refer to the "Jitter Attenuator" section for addi-
tional information.

Introduction to Operating Modes

The CS61574A and CS61575 support three oper-
ating modes which are selected by the level of the
MODE pin as shown in Tables 1 and 2, Figure 7,
and Figures A1-A3 of the Applications section.

The modes are Hardware Mode, Extended Hard-
ware Mode, and Host Mode. In Hardware and
Extended Hardware Modes, discrete pins are used
to configure and monitor the device. The Ex-
tended Hardware Mode provides a parallel chip
select input which latches the control inputs al-
lowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external processor monitors and configures the
device through a serial interface. There are thir-
teen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).

Hardware

Mode

Extended

Hardware

Mode

Host

Mode

Control

Method

Control

Pins

Control Pins

with Parallel

Chip Select

Serial

Interface

MODE

Pin

Level

<0.2 V

Floating or

2.5 V

>(RV+)-0.2

Line

Coding

External

Internal-

AMI, B8ZS,

or HDB3

External

AIS

Detection

Yes

Driver

Performance

Monitor

Yes

Table 1. Differences Between Operating Modes

CS61574A CS61575

DS154F2

TPOS

TNEG

RNEG

RPOS

TRANSMIT

TRANSFORMER

RRING

RECEIVE

TRANSFORMER

CONTROL

CS62180B

FRAMER

CIRCUIT

TTIP

TDATA

RDATA

TRING

LINE DRIVER

AMI

B8ZS,

HDB3,

CODER

TRANSMIT

TRANSFORMER

RLOOP

PCS

LEN0/1/2

LLOOP

TAOS

CONTROL

HARDWARE MODE

EXTENDED HARDWARE MODE

HOST MODE

CONTROL

P SERIAL PORT

RCODE

TCODE

CLKE

BPV

AIS

JITTER

ATTENUATOR

DRIVER MONITOR

LINE DRIVER

LINE RECEIVER

MTIP

MRING

DPM

RTIP

TTIP

TRING

T1 or E1

REPEATER

MUX

CS61575
CS61574A

TTIP

TPOS

TNEG

RNEG

TRING

RPOS

RRING

RTIP

RLOOP

LEN0/1/2

LLOOP

TAOS

CONTROL

DPM

DRIVER MONITOR

LINE DRIVER

LINE RECEIVER

MTIP

MRING

CS61575
CS61574A

CS62180B

FRAMER

CIRCUIT

JITTER

ATTENUATOR

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

RECEIVE

TRANSFORMER

RRING

RTIP

AIS

DETECT

JITTER

ATTENUATOR

LINE

RECEIVER

Figure 7. Overview of Operating Modes

CS61574A CS61575

DS154F2

Transmitter

The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line. The transmit data (TPOS
& TNEG or TDATA) is supplied synchronously
and sampled on the falling edge of the input
clock, TCLK.

Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inputs as shown in Table 3.

The CS61575 and CS61574A line drivers are de-
signed to drive a 75

equivalent load.

For E1 applications, the CS61574A and CS61575
drivers provide 14 dB of return loss during the
transmission of both marks and spaces. This im-
proves signal quality by minimizing reflections
off the transmitter. Similar levels of return loss
are provided for T1 applications.

For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102 and AT&T CB-119 requirements when
using #22 ABAM cable. A typical output pulse is
shown in Figure 8. These pulse settings can also
be used to meet CCITT pulse shape requirements
for 1.544 MHz operation.

For T1 Network Interface applications, two addi-
tional options are provided. Note that the optimal
pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61575 and CS61574A automatically adjusts
the pulse width based upon the "line length" se-
lection made.

500

1.0

0.5

-0.5

250

750

1000

TIME (nanoseconds)

OUTPUT

PULSE SHAPE

NORMALIZED
AMPLITUDE

ANSI TI.102,
AT&T CB 119
SPECIFICATIONS

Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

MODE

FUNCTION

PIN HARDWARE

EXTENDED

HARDWARE

HOST

TRANSMITTER

TPOS

TDATA

TPOS

TNEG

TCODE

TNEG

RECEIVER/DPM

RNEG

BPV

RNEG

RPOS

RDATA

RPOS

DPM

AIS

DPM

MTIP

RCODE

MTIP

MRING

CONTROL

PCS

LEN0

INT

LEN1

SDI

LEN2

SDO

RLOOP

LLOOP

SCLK

TAOS

CLKE

Table 2. Pin Definitions

LEN2 LEN1 LEN0

Option Selected

Application

0-133 FEET

DSX-1

ABAM

(AT&T 600B

or 600C)

133-266 FEET

266-399 FEET

399-533 FEET

533-655 FEET

120

(1:1.26)

(1:1)

CCITT G.703

AT&T CB113

Repeater

FCC PART 68, OPT. A

Network

Interface

ANSI T1.403

Table 3. Line Length Selection

CS61574A CS61575

DS154F2

The E1 G.703 pulse shape is supported with line
length selection LEN2/1/0=0/0/0. The pulse
width will meet the G.703 pulse shape template
shown in Figure 9, and specified in Table 4.

The CS61574A and CS61575 will detect a static
TCLK, and will force TTIP and TRING low to
prevent transmission when data is not present.
When any transmit control pin (TAOS, LEN0-2
or LLOOP) is toggled, the transmitter outputs
will require approximately 22 bit periods to stabi-
lize. The transmitter will take longer to stabilize

when RLOOP is selected because the timing cir-
cuitry must adjust to the new frequency.

Transmit All Ones Select

The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.

Receiver

The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.

269 ns

244 ns

194 ns

219 ns

488 ns

Nominal Pulse

100

110

120

-10

-20

Percent of
nominal
peak
voltage

Figure 9. Mask of the Pulse at the 2048 kbps Interface

For c oax ia l c abl e,
75

l oa d a nd

transformer specified
in Application Section.

For shielded twisted
pair, 120

load and

transformer specified
in Application Section.

Nominal peak voltage of a mark (pulse)

2.37 V

3 V

Peak voltage of a space (no pulse)

0.237 V

0.30 V

Nominal pulse width

244 ns

Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval

0.95 to 1.05*

Ratio of the widths of positive and negative
pulses at the nominal half amplitude

0.95 to 1.05*

* When configured with a 0.47

F nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 Specifications

CS61574A CS61575

DS154F2

A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).

The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data.

Data sampling will continue at the periods se-
lected by the phase selector until an incoming
pulse deviates enough to cause a new phase to be
selected for data sampling. The phases of the de-
lay line are selected and updated to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, with-
out error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method of clock and data recovery is tolerant
of long strings of consecutive zeros. The data

sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.

The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for each cycle of the ref-
erence clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
clock is 1.544 MHz. This implementation utilizes
the benefits of a 20 MHz clock for clock recovery
without actually having the clock present to im-
pede analog circuit performance.

10k

100

100k

700

100

300

PEAK-TO-PEAK

JITTER

(unit intervals)

JITTER FREQUENCY

(Hz)

AT&T 62411

Performance

138

Minimum

Figure 11. Minimum Input Jitter Tolerance of Receiver

1 : 2

RTIP

RRING

RPOS

RNEG

RCLK

Data

Level

Slicer

Data

Sampling

& Clock

Extraction

Jitter

Attenuator

Edge

Detector

Clock

Phase

Selector

Continuously

Calibrated

Delay Line

Figure 10. Receiver Block Diagram

CS61574A CS61575

DS154F2

In the Hardware Mode, data at RPOS and RNEG
should be sampled on the rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA should be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sampled as shown in Table 5.

Loss of Signal

The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecu-
tive zeros. A digital counter counts received
zeros, based on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level estab-
lished by the peak detector. After the signal is
removed for a period of time the data slicing
t hr esh o ld l eve l de c ay s to ap p roxi ma tel y
300 mV

peak

If ACLKI is present during the LOS state, ACLKI
is switched into the input of the jitter attenuator,
resulting in RCLK matching the frequency of
ACLKI. The jitter attenuator buffers any instanta-
ne ous ch ang es in p hase between the last
recovered clock and the ACLKI reference clock.
This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crystal oscillator of the jitter attenuator is

forced to its center frequency. Table 6 shows the
status of RCLK upon LOS.

Jitter Attenuator

The jitter attenuator reduces wander and jitter in
the recovered clock signal. It consists of a 32 or
192-bit FIFO, a crystal oscillator, a set of load
capacitors for the crystal, and control logic. The
jitter attenuator exceeds the jitter attenuation re-
quirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 12. The CS61575 fully meets AT&T
62411 jitter attenuation requirements. The
CS61574A will have a discontinuity in the jitter
transfer function when the incoming jitter ampli-
tude exceeds approximately 23 UIs.

The jitter attenuator works in the following man-
ner. The recovered clock and data are input to the
FIFO with the recovered clock controlling the
FIFO's write pointer. The crystal oscillator con-
trols the FIFO's read pointer which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). RCLK is equivalent to the oscilla-
tor's output. By changing the load capacitance
that the IC presents to the crystal, the oscillatior
frequency (and RCLK) is adjusted to the average
frequency of the recovered signal. Logic deter-
mines the phase relationship between the read and
write pointers and decides how to adjust the load
capacitance of the crystal. Jitter is absorbed in the
FIFO according to the jitter transfer characteristic
shown in Figure 12.

Crystal

present?

ACLKI

present?

Source of RCLK

Yes

ACLKI

Yes

Centered Crystal

Yes

ACLKI via the
Jitter Attenuator

Table 6. RCLK Status at LOS

MODE

(pin 5)

CLKE

(pin 28)

DATA

CLOCK

Clock Edge

for Valid Data

LOW

(<0.2V)

RPOS
RNEG

RCLK
RCLK

Rising
Rising

HIGH

(>(V+) - 0.2V)

LOW

RPOS
RNEG

SDO

RCLK
RCLK

SCLK

Rising
Rising

Falling

HIGH

(>(V+) - 0.2V)

HIGH

RPOS
RNEG

SDO

RCLK
RCLK

SCLK

Falling
Falling

Rising

MIDDLE

(2.5V)

RDATA

RCLK

Falling

X = Don't care

Table 5. Data Output/Clock Relationship

CS61574A CS61575

DS154F2

The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should they
attempt to cross, the oscillator's divide by four
circuit adjusts by performing a divide by 3 1/2 or
divide by 4 1/2 to prevent the overflow or under-
flow. During this activity, data will never be lost.

The difference between the CS61575 and
CS61574A is the depth of the FIFO in the jitter
attenuator. The CS61575 has a 192-bit FIFO
which allows it to attenuate large amplitude, low
frequency jitter as required by AT&T 62411 (e.g.,
28 UIpp @ 300 Hz). This makes the CS61575
ideal for use in T1 Customer Premises Equipment
which must be compatible with AT&T 62411 re-
quirements. In single-line Stratum 4, Type II
systems which are loop-timed, he CS61575 re-
covered clock can be used as the transmit clock
eliminating the need for an external system clock
synchronizer. In Stratum 4, Type I systems which
transfer timing and require a clock synchronizer,
the CS61575 simplifies the design of the synchro-
nizer by absorbing large amplitude low frequency
jitter before it reaches the synchronizer.

The CS61574A has a 32-bit FIFO which allows it
to absorb jitter with minimum data delay in T1
and E1 switching or transmission applications.
The CS61574A will tolerate large amplitude jitter
by tracking rather than attenuating it, preventing
data errors so that the jitter may be absorbed in
external frame buffers. With large amplitude input
jitter, the CS61574A jitter transfer function may
exhibit some jitter peaking, but will offer per-
formance comparable to the CS61574.

The jitter attenuator may be bypassed by pulling
XTALIN to RV+ through a 1 k

resistor and pro-

viding a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantization jitter of
approximately 1/13 UIpp and a duty cycle of ap-
proximately 30% (70%) when the attenuator is
disabled.

Local Loopback

Local loopback is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.

The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it through the jitter attenuator and
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the transmitter are still trans-
mitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-coded continu-
ous ones are transmitted at the TCLK frequency.
The receiver RTIP and RRING inputs are ignored
when local loopback is in effect.

t
t
enu

i
on in dB

Frequency in Hz

100

1 k

10 k

b) Maximum
Attenuation
Limit

62411 Requirements

a) Minimum Attenuation Limit

Measured Performance

Figure 12. Typical Jitter Transfer Function

CS61574A CS61575

DS154F2

Remote Loopback

Remote loopback is selected by taking RLOOP,
pin 26, high or by setting the RLOOP register bit
via the serial interface.

In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. Selecting remote loopback overrides
any TAOS request (see Table 7). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). Simultaneous selection
of local and remote loopback modes is not valid
(see Reset).

In the Extended Hardware Mode the transmitted
data is looped before the AMI/B8ZS/HDB3 en-
coder/decoder during remote loopback so that the
transmitted signal matches the received signal,
even in the presence of received bipolar viola-
tions. Data output on RDATA is decoded,
however, if RCODE is low.

Driver Performance Monitor

To aid in early detection and easy isolation of
non-functioning links, the IC is able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device's perform-
ance or the performance of a neighboring driver.
The driver performance monitor indicator is nor-

mally low, and goes high upon detecting a driver
failure.

The driver performance monitor consists of an ac-
tivity detector that monitors the transmitted signal
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period. In the Host Mode,
DPM is available from both the register and pin
11.

Whenever more than one line interface IC resides
on the same circuit board, the effectiveness of the
driver performance monitor can be maximized by
having each IC monitor performance of a neigh-
boring IC, rather than having it monitor its own
performance. Note that a CS61574A or CS61575
can not be used to monitor a CS61574 due to out-
put stage differences.

Line Code Encoder/Decoder

In the Extended Hardware Mode, three line codes
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.

LEN 2/1/0

000

010-111

TCODE

(Transmit

Encoder

Selection)

LOW

HDB3

Encoder

B8ZS

Encoder

HIGH

AMI

Encoder

RCODE

(Receiver

Decoder

Selection)

LOW

HDB3

Decoder

B8ZS

Decoder

HIGH

AMI

Decoder

Table 8. Encoder/Decoder Selection

RLOOP

Input

Signal

TAOS

Input

Signal

Source of

Data for

TTIP & TRING

Source of

Clock for

TTIP & TRING

TDATA

TCLK

all 1s

TCLK

RTIP & RRING RTIP & RRING (RCLK)

Notes: 1. X = Don't care. The identified All Ones Select

input is ignored when the indicated loopback
is in effect.

2. Logic 1 indicates that Loopback or All Ones

option is selected.

Table 7. Interaction of RLOOP with TAOS

CS61574A CS61575

DS154F2

Alarm Indication Signal

In the Extended Hardware Mode, the receiver sets
the output pin AIS high when less than 9 zeros
are detected out of 8192 bit periods. AIS returns
low when 9 or more zeros are detected out of
8192 bit periods.

Parallel Chip Select

In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the en-
tire PCS low period. The digital control inputs are
ignored when PCS is high.

Power On Reset / Reset

Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by the crystal oscillator, or
ACLKI if the oscillator is disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.

In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
forgoes any requirement to reset the line interface
when in operation. However, a reset function is
available which will clear all registers.

In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all reg-
isters to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.

Serial Interface

In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.

Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are ter-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.

Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes High-Z after CS goes high or at the end of
the hold period of data bit D7.

CS61574A CS61575

DS154F2

An address/command byte, shown in Table 9, pre-
cedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.

The data register, shown in Table 10, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.

Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:

1) The current interrupt on the serial interface

will be cleared. (Note that simply reading
the register bits will not clear the inter-
rupt).

2) Output data bits 5, 6 and 7 will be reset as

appropriate.

3) Future interrupts for the corresponding LOS

or DPM will be prevented from occurring.

Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.

Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent loss of sig-
nal and/or driver problems.

SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
c a ti on s whe re the h os t proc esso r h as a
bi-directional I/O port.

LSB, first bit

clr LOS Clear Loss Of Signal

clr DPM Clear Driver Performance

LEN0

Bit 0 - Line Length Select

LEN1

Bit 1 - Line Length Select

LEN2

Bit 2 - Line Length Select

RLOOP Remote Loopback

LLOOP Local Loopback

MSB, last bit

TAOS

Transmit All Ones Select

Table 10. Input Data Register

SCLK

SDO

SDI

Address/Command Byte

Data Input/Output

R/W

Figure 13. Input/Output Timing

LSB, first bit

LOS

Loss Of Signal

DPM

Driver Performance

LEN0

Bit 0 - Line Length Select

LEN1

Bit 1 - Line Length Select

LEN2

Bit 2 - Line Length Select

Table 11. Output Data Bits 0 - 4

LSB, first bit

R/W

Read/Write Select; 0 = write, 1 = read

ADDP

LSB of address, Must be 0

ADD1

Must be 0

ADD2

Must be 0

ADD3

Must be 0

ADD4

Must be 1

Reserved - Must be 0

MSB, last bit

Don't Care

Table 9. Address/Command Byte

CS61574A CS61575

DS154F2

Power Supply

The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies
provide internal isolation. These pins should be
connected externally near the device and decou-
pled to their respective grounds. TV+ must not
exceed RV+ by more than 0.3V.

Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog cir-
cuits in both the transmit and receive paths. A 1.0

F capacitor should be connected between TV+

and TGND, and a 0.1

F capacitor should be con-

nected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68

F tantalum capacitor should be added close

to the RV+/RGND supply. Wire-wrap bread-
boarding of the line interface is not recommended
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

Bits

Status

Reset has occurred or no program input.

TAOS in effect.

LLOOP in effect

TAOS/LLOOP in effect.

RLOOP in effect.

DPM changed state since last "clear DPM"
occurred.

LOS changed state since last "clear LOS"
occurred.

LOS and DPM have changed state since
last "clear LOS" and "clear DPM".

Table 12. Coding for Serial Output bits 5,6,7

CS61574A CS61575

DS154F2

PIN DESCRIPTIONS

Hardware Mode

top

view

ACLKI

TCLK

TAOS

TPOS

LLOOP

TNEG

RLOOP

MODE

LEN2

RNEG

LEN1

RPOS

LEN0

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

DPM

RTIP

LOS

MRING

TTIP

MTIP

TGND

TRING

TV+

ACLKI

TAOS

TCLK

LLOOP

TPOS

RLOOP

TNEG

LEN2

MODE

LEN1

RNEG

LEN0

RPOS

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

DPM

MRING

LOS

MTIP

TTIP

TRING

TGND

TV+

CS61574A CS61575

DS154F2

Extended Hardware Mode

ACLKI

TAOS

TCLK

LLOOP

TDATA

RLOOP

TCODE

LEN2

MODE

LEN1

BPV

LEN0

RDATA

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

AIS

PCS

LOS

RCODE

TTIP

TRING

TGND

TV+

top

view

ACLKI

TCLK

TAOS

TDATA

LLOOP

TCODE

RLOOP

MODE

LEN2

BPV

LEN1

RDATA

LEN0

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

AIS

RTIP

LOS

PCS

TTIP

RCODE

TGND

TRING

TV+

CS61574A CS61575

DS154F2

Host Mode

ACLKI

CLKE

TCLK

SCLK

TPOS

TNEG

SDO

MODE

SDI

RNEG

INT

RPOS

RGND

RCLK

RV+

XTALIN

RRING

XTALOUT

RTIP

DPM

MRING

LOS

MTIP

TTIP

TRING

TGND

TV+

top

view

ACLKI

TCLK

CLKE

TPOS

SCLK

TNEG

MODE

SDO

RNEG

SDI

RPOS

INT

RCLK

RGND

XTALIN

RV+

XTALOUT

RRING

DPM

RTIP

LOS

MRING

TTIP

MTIP

TGND

TRING

TV+

CS61574A CS61575

DS154F2

Power Supplies

RGND - Ground, Pin 22.

Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.

RV+ - Power Supply, Pin 21.

Power supply for all subcircuits except the transmit driver; typically +5 Volts.

TGND - Ground, Transmit Driver, Pin 14.

Power supply ground for the transmit driver; typically 0 Volts.

TV+ - Power Supply, Transmit Driver, Pin 15.

Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.

Oscillator

XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.

A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 k

resistor, and floating XTALOUT, Pin 10.

Overdriving the oscillator with an external clock is not supported.

Control

ACLKI - Alternate External Clock Input, Pin 1.

A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground.
During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator.

CLKE - Clock Edge, Pin 28. (Host Mode)

Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.

CS - Chip Select, Pin 26. (Host Mode)

This pin must transition from high to low to read or write the serial port.

INT - Receive Alarm Interrupt, Pin 23. (Host Mode)

Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the
power supply through a resistor.

CS61574A CS61575

DS154F2

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)

Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.

LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)

Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the
receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless
overridden by a TAOS request. Inputs on RTIP and RRING are ignored.

MODE - Mode Select, Pin 5.

Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin puts the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware
Mode, where configuration and status are controlled by discrete pins. When floating MODE,
there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2).

PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)

Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2,
RLOOP, LLOOP and TAOS inputs.

RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)

Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).

RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)

Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored.

Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.

SCLK - Serial Clock, Pin 27. (Host Mode)

Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.

SDI - Serial Data Input, Pin 24. (Host Mode)

Data for the on-chip register. Sampled on the rising edge of SCLK.

SDO - Serial Data Output, Pin 25. (Host Mode)

Status and control information from the on-chip register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to or after bit D7 is output.

CS61574A CS61575

DS154F2

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)

Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by TCLK.

TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)

Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting
TCODE high enables the AMI transmitter encoder .

Data

RCLK - Recovered Clock, Pin 8.

The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the
loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is
not present during LOS, RCLK is forced to the center frequency of the crystal oscillator..

RDATA - Receive Data - Pin 7. (Extended Hardware Mode)

Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the
line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK.

RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host
Modes)

The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS
and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines
the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse
(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive
pulse received on the RRING pin generates a logic 1 on RNEG.

RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.

The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data
and clock are recovered and output on RCLK and RPOS/RNEG or RDATA.

TCLK - Transmit Clock, Pin 2.

The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are
sampled on the falling edge of TCLK.

TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)

Transmitter NRZ input data which passes through the line code encoder, and is then driven on to
the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK.

TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)

Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and
TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a
positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.

CS61574A CS61575

DS154F2

TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.

The AMI signal is driven to the line through these pins. The transmitter output is designed to
drive a 75

load between TTIP and TRING. A transformer is required as shown in Table A1.

Status

AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)

AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.

BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)

BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.

DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)

DPM goes high if no activity is detected on MTIP and MRING.

LOS - Loss of Signal, Pin 12.

LOS goes high when 175 consecutive zeros have been received. LOS returns low when the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than
100 consectutive zeros) as prescribed in ANSI T1.231-1993. When in the loss of signal state
RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter
attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the
crystal oscillator.

MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)

These pins are normally connected to TTIP and TRING and monitor the output of a line interface
IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to
the serial interface will prevent an interrupt from the driver performance monitor.

Ordering Guide

Model

Frequency

FIFO Depth (Bits)

Package

CS61575-IP1

T1 & E1

192

28-pin Plastic DIP

CS61575-IL1

T1 & E1

192

28-pin PLCC

CS61574A-IP1

T1 & E1

28-pin Plastic DIP

CS61574A-IL1

T1 & E1

28-pin PLCC

CS61574A CS61575

DS154F2

28 pin
Plastic DIP

MILLIMETERS

INCHES

DIM

MIN

MAX

MIN

MAX

13.72

14.22 0.540

0.560

36.45

1.02

0.36

0.51

3.94

3.18

0.20

0°

15.24

37.21

1.65

0.56

1.02

5.08

3.81

0.38

15°

1.435

0.040

0.014

0.020

0.155

0.125

0.600

0.008

0°

1.465

0.065

0.022

0.040

0.200

0.150

0.015

15°

15.87

0.625

2.41

2.67 0.095

0.105

SEATING
PLANE

NOTES:

1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

NOM

13.97

36.83

1.27

0.46

0.76

4.32

0.25

2.54

NOM

0.550

1.450

0.050

0.018

0.030

0.170

0.010

0.100

E1
e1
eA

D2/E2

28-pin PLCC

D2/E2

MAX

MIN

MAX

MIN

MILLIMETERS

INCHES

DIM

4.57

4.20

0.180

0.165

D/E

12.32

12.57 0.485

0.495

0.53

0.33

0.021

0.013

2.29

0.090

11.43

11.58 0.450

0.456

9.91

10.92 0.390

0.430

1.19

1.35 0.047

0.053

NOM

4.45

12.45

0.41

2.79

11.51

10.41

1.27

NOM

0.175

0.490

0.016

0.110

0.453

0.410

0.050

3.04

0.120

D1/E1

CS61574A CS61575

DS154F2

APPLICATIONS

Line Interface

Figures A1-A3 show typical T1 and E1 line inter-
face application circuits. Table A1 shows the
external components which are specific to each
application. Figure A1 illustrates a T1 interface in
the Host Mode. Figure A2 illustrates a 120

interface in the Hardware Mode. Figure A3 illus-
trates a 75

E1 interface in the Extended

Hardware Mode

The receiver transformer has a grounded center
tap on the IC side. Resistors between the RTIP

and RRING pins to ground provide the termina-
tion for the receive line.

The transmitter transformer matches the 75

transmitter output impedance to the line imped-
ance. Figures A1-A3 show a 0.47

F capacitor in

series with the transmit transformer primary. This
capacitor is needed to prevent any output stage
imbalance from resulting in a DC current through
the transformer primary. This current might satu-
rate the transformer producing an output offset
level shift.

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61574A

CS61575

HOST

MODE

RECEIVE
LINE

TRANSMIT
LINE

XTL

RV+

RGND

0.1

+5V

1.0

TGND

RV+

TV+

CLKE

ACLKI

LOS

DPM

MODE

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

XTALIN

XTALOUT

RGND

TGND

SCLK

INT

SDI

SDO

RTIP

RRING

MTIP

MRING

TRING

TTIP

0.47

1:1.15

PE-65388

2CT:1

PE-65351

Serial

Port

+5V

100 k

Figure A1. T1 Host Mode Configuration

Frequency

MHz

Cable

R1 and R2

Transmit

Transformer

Crystal

XTL

1.544 (T1)

100

200

1:1.15

CXT6176

2.048 (E1)

120

240

1:1.26

CXT8192

150

1:1

Table A1. External Component Values

CS61574A CS61575

DS154F2

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61574A

CS61575

HARDWARE

MODE

Line

Length
Setting

RECEIVE
LINE

TRANSMIT
LINE

XTL

RGND

0.1

+5V

1.0

TGND

RV+

TV+

TAOS

ACLKI

RLOOP

LLOOP

MODE

RPOS

RNEG

RCLK

TPOS

TNEG

TCLK

XTALIN

XTALOUT

RGND

TGND

LEN0

LEN1

LEN2

RTIP

RRING

MTIP

MRING

TRING

TTIP

0.47

1:1.26

PE-65389

2CT:1

PE-65351

LOS

DPM

Figure A2. 120

E1 Hardware Mode Configuration

Control

Monitor

Frame

Format

Encoder/

Decoder

CS61574A

CS61575

EXTENDED

HARDWARE

MODE

Line

Length
Setting

RECEIVE
LINE

TRANSMIT
LINE

XTL

RGND

0.1

+5V

1.0

TGND

RV+

TV+

RCODE

PCS

BPV

TAOS

MODE

RDATA

RCLK

TDATA

TCLK

XTALIN

XTALOUT

RGND

TGND

LEN0

LEN1

LEN2

RTIP

RRING

TRING

TTIP

0.47

1:1

PE-65389

2CT:1

PE-65351

ACLKI

RLOOP

LLOOP

LOS

AIS

TCODE

Figure A3. 75

E1 Extended Hardware Mode Configuration

CS61574A CS61575

DS154F2

Transformers

Recommended transmitter and receiver trans-
former specifications are shown in Table A2. The
transformers in Table A3 have been tested and
recommended for use with the CS61574A and
CS61575. Refer to the "Telecom Transformer Se-
lection Guide" for detailed schematics which
show how to connect the line interface IC with a
particular transformer.

In applications where it is advantageous to use a
single transmitter transformer for 75

and 120

E1 applications, a 1:1.26 transformer may be
used. Although transmitter return loss will be re-
duced for 75

applications, the pulse amplitude

will be correct across a 75

load.

Selecting an Oscillator Crystal

Specific crystal parameters are required for
proper operation of the jitter attenuator. It is rec-
ommended that the Crystal Semiconductor
CXT6176 crystal be used for T1 applications and
the CXT8192 crystal be used for E1 applications.

Designing for AT&T 62411

For additional information on the requirements of
AT&T 62411 and the design of an appropriate
system synchronizer, please refer to the Crystal
Semiconductor Application Notes: "AT&T 62411
Design Considerations Jitter and Synchroniza-
t i on " a nd "Ji tt er Te st ing Proc edu res for
Compliance with AT&T 62411".

Transmit Side Jitter Attenuation

In some applications it is desirable to attenuate
jitter from the signal to be transmitted. A
CS61575 in local loopback mode can be used as a
jitter attenuator. The inputs to the jitter attenuator
are TPOS, TNEG, TCLK. The outputs from the
jitter attenuator are RPOS, RNEG and RCLK.

Line Protection

Secondary protection components can be added
to provide lightning surge and AC power-cross
immunity. Refer to the application note "Secon-
dary Line Protection for T1 and E1 Line Cards"
for detailed information on the different electrical
safety standards and specific application circuit
recommendations.

Parameter

Receiver

Transmitter

Turns Ratio

1:2 CT

1:1

1.5 % for 75

1:1.15

5 % for 100

1:1.26

1.5 % for 120

Primary Inductance

600

H min. @ 772 kHz

1.5 mH min. @ 772 kHz

Primary Leakage Inductance

1.3

H max. @ 772 kHz

0.3

H max. @ 772 kHz

Secondary Leakage Inductance

0.4

H max. @ 772 kHz

0.4

H max. @ 772 kHz

Interwinding Capacitance

23 pF max.

18 pF max.

ET-constant

16 V-

s min. for T1

12 V-

s min. for E1

16 V-

s min. for T1

12 V-

s min. for E1

Table A2. Transformer Specifications

CS61574A CS61575

DS154F2

Interfacing The CS61575 and CS61574A With
the CS62180B T1 Transceiver

To interface with the CS62180B, connect the de-
vices as shown in Figure A4. In this case, the line
interface and CS62180B are in Host Mode con-
trolled by a microprocessor serial interface. If the
line interface is used in Hardware Mode, then the
line interface RCLK output must be inverted be-
fore being input to the CS62180B. If the
CS61575 or CS61574A is used in Extended
Hardware Mode, the RCLK output does not have
t o b e i nve rt ed be fo re be ing in put to th e
CS62180B.

Application

Turns

Ratio(s)

Manufacturer

Part Number

Package Type

RX:

T1 & E1

1:2CT

Pulse Engineering

PE-65351

1.5 kV through-hole, single

Schott

67129300

Bel Fuse

0553-0013-HC

TX:

1:1.15

Pulse Engineering

PE-65388

1.5 kV through-hole, single

Schott

67129310

Bel Fuse

0553-0013-RC

TX:

E1 (75 & 120

)

1:1.26

1:1

Pulse Engineering

PE-65389

1.5 kV through-hole, single

Schott

67129320

Bel Fuse

0553-0013-SC

RX &TX:

1:2CT
1:1.15

Pulse Engineering

PE-65565

1.5 kV through-hole, dual

Bel Fuse

0553-0013-7J

RX &TX:

E1 (75 & 120

)

1:2CT
1:1.26

1:1

Pulse Engineering

PE-65566

1.5 kV through-hole, dual

Bel Fuse

0553-0013-8J

RX &TX:

1:2CT
1:1.15

Pulse Engineering

PE-65765

1.5 kVsurface-mount, dual

Bel Fuse

S553-0013-06

RX &TX:

E1 (75 & 120

)

1:2CT
1:1.26

1:1

Pulse Engineering

PE-65766

1.5 kV surface-mount, dual

Bel Fuse

S553-0013-07

RX :

T1 & E1

1:2CT

Pulse Engineering

PE-65835

3 kV through-hole, single

EN60950, EN41003 approved

TX:

E1 (75 & 120

)

1:1.26

1:1

Pulse Engineering

PE-65839

3 kV through-hole, single

EN60950, EN41003 approved

Table A3. Recommended Transformers

ACLK

TCLK

RCLK

RPOS

RNEG

TPOS

TNEG

CS62180B

CLKE

SCLK

INT

SDO

SDI

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

SCLK

SDO

SDI

TO HOST CONTROLLER

V+

100k

1.544 MHz

CLOCK

SIGNAL

CS61574A OR
CS61575

V+

22k

MODE

Figure A4. Interfacing the CS61574A or CS61575

with a CS62180B (Host Mode)

CS61574A CS61575

DS154F2

Features

Socketed Line Interface Device

All Required Components for Complete
Line Interface Evaluation

Configuration by DIP Switch or Serial
Interface

LED Status Indicators for Alarm
Conditions

Support for Host, Hardware, and
Extended Hardware Modes

General Description

The evaluation board includes a socketed line interface
device and all support components necessary for
evaluation. The board is powered by an external 5 Volt
supply.

The board may be configured for 100

twisted-pair

T1, 75

coax E1, or 120

twisted-pair E1 operation.

Binding posts are provided for line connections. Sev-
eral BNC connectors are available to provide system
clocks and data I/O. Two LED indicators monitor de-
vice alarm conditions. The board supports all line
interface operating modes.

ORDERING INFORMATION:

CDB61534, CDB61535.

CDB61535A,

CDB6158, CDB6158A,

CDB61574,

CDB61574A, CDB61575, CDB61577,
CDB61304A, CDB61305A

SEP '95

DS40DB3

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

Line Interface Evaluation Board

CDB61534, CDB61535, CDB61535A, CDB6158,
CDB6158A, CDB61574, CDB61574A, CDB61575,
CDB61577, CDB615304A, & CDB61305A

ACLKI

TCLK

TPOS
(TDATA)

TNEG

RNEG
(BPV)

RPOS
(RDATA)

RCLK

CS61534,
CS61535,

CS61535A,

CS6158,

CS6158A,

CS61574,

CS61574A,

CS61575,
CS61577,

CS61304A

CS61305A

Reset

Circuit

Mode Select

Circuit

(TCODE)

+5V

LED Status

Indicators

Hardware

Control Circuit

Serial Interface
Control Circuit

TTIP

TRING

RTIP

RRING

XTL

POWER SUPPLY

As shown on the evaluation board schematic in
Figure 1, power is supplied to the evaluation
board from an external +5 Volt supply connected
to the two binding posts labeled +5V and GND.
Transient suppressor D10 protects the compo-
nents on the board from over-voltage damage and
reversed supply connections. The recommended
power supply decoupling is provided by C1, C2
and C3. Ceramic capacitor C1 and electrolytic ca-
pacitor C2 are used to decouple RV+ to RGND.
Capacitor C3 decouples TV+ to TGND. The TV+
and RV+ power supply traces are connected at the
device socket U1. A ground plane on the compo-
nent side of the evaluation board insures optimum
performance.

BOARD CONFIGURATION

Pins on line interface device U1 with more than
one pin name have different functions depending
on the operating mode selected. Pin names not
enclosed in parenthesis or square brackets de-
scribe the Hardware mode pin function. Pin
names enclosed in parenthesis describe the Ex-
tended Hardware mode pin function. Pin names
enclosed in square brackets describe the Host
mode pin function.

Table 1 explains how to configure the evaluation
board jumpers depending on the device installed
and the desired operating mode. Mode selection
is accomplished with slide switch SW1 and jump-
e rs JP2 , JP6, and JP7 . The CS61 535 A,
CS61574A, CS61575, CS61577, CS61304A, and
CS61305A support the Hardware, Extended
Hardware, and Host operating modes. The
CS61534, CS61535, and CS61574 support the
Hardware and Host operating modes. The
CS6158 and CS6158A only support the Hardware
operating mode.

Hardware Mode

In the Hardware operating mode, the line inter-
face is configured using DIP switch S2. The digi-
tal control inputs to the device selected by S2 in-
clude: transmit all ones (TAOS), local loopback
(LLOOP), remote loopback (RLOOP), and trans-
mit line length selection (LEN2,LEN1,LEN0).
Closing a DIP switch on S2 towards the label sets
the device control pin of the same name to logic 1
(+5 Volts). Note that S2 switch positions TCODE
and RCODE have no function in Hardware mode.
In addition, the host processor interface connector
JP1 should not be used in the Hardware mode.

Two LED status indicators are provided in Hard-
ware mode. The LED labeled DPM (AIS) illumi-
nates when the line interface asserts the Driver

JUMPER

POSITION

FUNCTION SELECTED

JP1

Connector for external processor in Host operating mode.

JP2, JP6, JP7

A-A

Extended Hardware operating mode.

B-B

Hardware or Host operating modes.

JP3

Hardware or Extended Hardware operating modes.

OUT

Host operating mode.

JP4

C-C

Connects the ACLKI BNC input to pin 1 of device.

D-D

Grounds the ACLKI BNC input through 51

resistor R1.

JP5

E-E

Transmit line connection for all applications except those listed for "F-F" on the next line.

F-F

coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1.

JP8

Shorts resistor R2 for all applications except those listed for "OUT" on the next line.

OUT

Inserts resistor R2 for 75

coax E1 applications using the CS61534, 35, 58, 74, or 77.

Table 1. Evaluation Board Jumper Settings

LINE INTERFACE EVALUATION BOARD

DS40DB3

R16
1k

RCLK

TCLK

TPOS

(TDATA)

RNEG

(BPV)

Pin 3

TCLK

RCLK

Pin 6

TNEG

RPOS

(RDATA)

ACLKI

Pin 7

ACLKI

R1 51.1

Pin 4

R15

100

RV+

2N2222

470

LED

RV+

2N2222

470

LED

JP1

1N914

R14
4.7k

SIP

RV+

LOS

DPM
(AIS)

MODE

R18

10k

R17

10k

LEN1/SDI

LEN2/SD0

LLOOP/SCLK

TAOS/CLKE

TCODE

RLOOP/CS

SDI

SDO

SCLK

INT

LEN0/INT

RESET

MODE
SW1

221k

JP4

JP2

RCODE

C4 0.047

HOST:3-1,6-8
EXT HW: 3-2, 6-7
HW: 3-4, 6-5

TRING

TTIP

0.47

TRING

TTIP

+5V

RV+

TV+

TGND

RGND

D10
P6KE

T1
(see Table 2)

0.1

RTIP

RRING

RTIP

JP8

4.4

RV+

RCLK

TCLK

RNEG (BPV)

ACLKI

LEN1 [SDI]

LEN2 [SD0]

LLOOP [SCLK]

TAOS [CKLE]

XTALIN

{CS6158/58A: RT}

XTALOUT

{CS6158/58A: NC}

LOS

DPM (AIS)

MODE

RTIP

RRING

TRING

Pin 17

Pin 18

TTIP

RV+

R13 (only included for CS6158/58A)
1k

(Used only for E1 75

applications with the CS61534,
CS61535, CS6158, CS61574,
OR CS61577)

CS61534, CS61535,
CS61535A, CS6158,
CS6158A, CS61574,
CS61574A, CS61575,
CS61577, CS61304A,
OR CS61305A

U1:

Prototyping

Area

RV+

LEN0 [INT]

RLOOP [CS]

MRING (PCS)

RPOS (RDATA)

TPOS (TDATA)

MTIP (RCODE)

JP6

JP7

JP5

E1: CXT8192
T1: CXT6176
(not included for CS6158/58A)

TNEG (TCODE)

R9
200

R10
200

(see Table 2)

2:1

GND

(0V)

Change R9 and R10 for E1 operation

Figure 1. Evaluation Board Schematic

LINE INTERFACE EVALUATION BOARD

DS40DB3

Performance Monitor alarm. The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.

Extended Hardware Mode

In the Extended Hardware operating mode, the
line interface is configured using DIP switch S2.
The digital control inputs to the device selected
by S2 include: transmit all ones (TAOS), local
loopback (LLOOP), remote loopback (RLOOP),
transmit line length selection (LEN2, LEN1,
LEN0), transmit line code (TCODE), and receive
line code (RCODE). Closing a DIP switch (mov-
ing it towards the S2 label) sets the device control
pin of the same name to logic 1 (+5 Volts). Note
that the TCODE and RCODE options are active
low and are enabled when the switch is moved
away from the S2 label. The parallel chip select
input PCS is tied to ground in Extended Hard-
ware mode to enable the device to be reconfig-
ured when S2 is changed. In addition, the host
processor interface connector JP1 should not be
used in Extended Hardware mode.

Two LED status indicators are provided in Ex-
tended Hardware mode. The LED labeled DPM
(AIS) illuminates when the line interface detects
the receive blue alarm (AIS). The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.

Host Mode

In the Host operating mode, the line interface is
configured using a host processor connected to
the serial interface port JP1. The S2 switch posi-
tion labeled CLKE selects the active edge of
SCLK and RCLK. Closing the CLKE switch se-
lects RPOS and RNEG to be valid on the falling
edge of RCLK and SDO to be valid on the rising
edge of SCLK as required by the CS2180B T1
framer.

All other DIP switch positions on S2 should be
open (logic 0) to prevent shorting of the serial in-

terface signals. Resistor R15 is a current limiting
resistor that prevents the serial interface signals
from being shorted directly to the +5 Volt supply
if any S2 switch, other than CLKE, is closed.
Jumper JP3 should be out so the INT pin may be
externally pulled-up at the host processor inter-
rupt pin.

Two LED status indicators are provided in Host
mode. The LED labeled DPM (AIS) illuminates
when the line interface asserts the Driver Per-
formance Monitor alarm. The LED labeled LOS
illuminates when the line interface receiver has
detected a loss of signal.

Manual Reset

A manual reset circuit is provided that can be
used in Hardware and Extended Hardware
modes. The reset circuit consists of S1, R4, R16,
C4, D8, and D9. Pressing switch S1 forces both
LLOOP and RLOOP to a logic 1 and causes a
reset. A reset is only necessary for the CS61534
device to calibrate the center frequency of the re-
ceiver clock recovery circuit. All other line inter-
face units use a continuously calibrated clock re-
covery circuit that eliminates the reset require-
ment.

TRANSMIT CIRCUIT

The transmit clock and data signals are supplied
on BNC inputs labeled TCLK, TPOS(TDATA),
and TNEG. In the Hardware and Host operating
modes, data is supplied on the TPOS(TDATA)
and TNEG connectors in dual NRZ format. In the
Extended Hardware operating mode, data is sup-
plied in NRZ format on the TPOS(TDATA) con-
nector and TNEG is not used.

The transmitter output is transformer coupled to
the line through a transformer denoted as T1 in
Figure 1. The signal is available at the TTIP and
TRING binding posts. Capacitor C5 is the recom-
mended 0.47

F DC blocking capacitor.

LINE INTERFACE EVALUATION BOARD

DS40DB3

The evaluation board supports 100

twisted-pair

T1, 75

coax E1, and 120

twisted-pair E1 op-

eration. The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 are supplied from
the factory with a 1:2 transmit transformer that
may be used for all T1 and E1 applications. The
C DB 61 5 35 A, C DB 6 15 8A, CDB 615 74A,
CDB61575, CDB61304A, and CDB61305A are
supplied with a 1:1.15 transmit transformer in-
stalled for T1 applications. An additional 1:1:1.26
transformer for E1 applications is provided with
the board. This transformer requires JP5 to be
jumpered across F-F for 75

coax E1 applica-

tions.

T h e C DB 61 5 34 , C DB 6 15 3 5, C DB61 58,
CDB61574, and CDB61577 require the JP8
jumper to be out for 75

coax E1 applications.

This inserts resistor R2 to reduce the transmit
pulse amplitude and meet the 2.37 V nominal
pulse amplitude requirement in CCITT G.703. In
addition, R2 increases the equivalent load imped-
ance across TTIP and TRING.

RECEIVE CIRCUIT

The receive line interface signal is input at the
RTIP and RRING binding posts. The receive sig-
nal is transformer coupled to the line interface de-
vice through a center-tapped 1:2 transformer. The
transformer produces ground referenced pulses of
equal amplitude and opposite polarity on RTIP
and RRING.

The receive line interface is terminated by resis-
tors R9 and R10. The evaluation boards are sup-
plied from the factory with 200

resistors for ter-

minating 100

T1 twisted-pair lines. Resistors

R9 and R10 should be replaced with 240

resis-

tors for terminating 120

E1 twisted-pair lines or

150

resistors for terminating 75

E1 coaxial

lines. Two 243

resistors and two 150

resistors

are included with the evaluation board for this
purpose.

The recovered clock and data signals are avail-
a b le on B NC o u tp u ts la b el e d RC L K,
RPOS(RDATA), and RNEG(BPV). In the Hard-
ware and Host operating modes, data is output on
the RPOS(RDATA) and RNEG(BPV) connectors
in dual NRZ format. In the Extended Hardware
operating mode, data is output in NRZ format on
the RPOS(RDATA) connector and bipolar viola-
tions are reported on the RNEG(BPV) connector.

QUARTZ CRYSTAL

A quartz crystal must be installed in socket Y1 for
all devices except the CS6158 and CS6158A. A
Crystal Semiconductor CXT6176 crystal is rec-
ommended for T1 operation and a CXT8192 is
recommended for E1 operation. The evaluation
board has a CXT6176 installed at the factory and
a CXT8192 is also provided with the board.

The CDB6158 and CDB6158A have resistor R13
installed instead of a crystal. This connects the RT
pin of the device to the +5 Volt supply.

ALTERNATE CLOCK INPUT

The ACLKI BNC input provides the alternate
clock reference for the line interface device
(ACLK for the CS61534) when JP4 is jumpered
across C-C. This clock is required for the
CS61534, CS61535, CS6158, and CS6158A op-
eration but is optional for all other line interface
devices. If ACLKI is provided, it may be desir-
able to connect both C-C and D-D positions on
JP4 to terminate the external clock source provid-
ing ACLKI with the 51

resistor R1. If ACLKI is

optional and not used, connector JP4 should be
jumpered across D-D to ground pin 1 of the de-
vice through resistor R1.

TRANSFORMER SELECTION

To permit the evaluation of other transformers,
Table 2 lists the transformer and line interface de-
vice combinations that can be used in T1 and E1

LINE INTERFACE EVALUATION BOARD

DS40DB3

applications. A letter at the intersection of a row
and column in Table 2 indicates that the selected
transformer is supported for use with the device.
The transformer is installed in the evaluation
board with pin 1 positioned to match the letter
illustrated on the drawing in Table 2. For exam-
ple, the Pulse Engineering PE-65388 transformer
may be used with the transmitter of the CS61575
device for 100

T1 applications only (as indi-

cated by note 3) when installed in transformer
socket T1 with pin 1 at position D (upper right).

PROTOTYPING AREA

A prototyping area with power supply and ground
connections is provided on the evaluation board.
This area can be used to develop and test a vari-
ety of additional circuits like a data pattern gener-
ator, CS2180B framer, system synchronizer PLL,
or specialized interface logic.

EVALUATION HINTS

1. Properly terminate TTIP/TRING when evaluat-
ing the transmit output signal. For more informa-
tion concerning pulse shape evaluation, refer to
the Crystal application note entitled "Measure-
ment and Evaluation of Pulse Shapes in T1/E1
Transmission Systems."

2. Change the receiver terminating resistors R9
and R10 when evaluating E1 applications. Resis-
tors R9 and R10 should be replaced with 240

resistors for terminating 120

E1 twisted-pair

lines or 150

resistors for terminating 75

coaxial lines. Two 243

resistors and two 150

resistors are included with the evaluation board
for this purpose.

3. Closing a DIP switch on S2 towards the label
sets the device control pin of the same name to
logic 1 (+5 Volts).

4. To avoid damage to the external host controller
connected to JP1, all S2 switch positions (except
CLKE) should be open. In the Host operating
mode, the CLKE switch selects the active edge of
SCLK and RCLK.

LINE INTERFACE EVALUATION BOARD

DS40DB3

NOTES:

1. A letter at the intersection of a row and column in Table 2 indicates

that the selected transformer is supported for use with the device.
The transformer is installed in the evaluation board with pin 1 po-
sitioned to match the letter illustrated in the drawing to the left.

2. The receive transformer (RX) is soldered at location T2 on the

evaluation board and is used for all applications. The transmit
transformer (TX) is socketed at location T1 on the evaluation
board and may be changed according to the application.

3. For use in 100

T1 twisted-pair applications only.

4. For use in 75

and 120

E1 applications only. Place jumper JP5

in position F-F for 75

E1 applications requiring a 1:1 turns ratio.

5. Transmitter return loss improves when using a 1:2 turns ratio trans-

former with the appropriate transmit resistors.

Table 2. Transformer Applications

TRANSFORMER

(Turns Ratio)

1,2

LINE INTERFACE UNIT

'34

'35

'35A

'58

'58A

'74,'77

'74A

'75

'304A,

'305A

RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX

PE-65351 (1:2CT)

Schott 12930 (1:2CT)

PE-65388 (1:1.15)

3,5

Schott 12931 (1:1.15)

3,5

PE-65389 (1:1:1.26)

4,5

Schott 12932 (1:1:1.26)

4,5

PE-64951 (dual 1:2CT)

Schott 11509 (dual 1:2CT)

PE-65565 (dual 1:1.15 & 1:2CT)

3,5

Schott 12531 (dual 1:1.15 & 1:2CT)

3,5

PE-65566 (dual 1:1:1.26 & 1:2CT)

4,5

Schott 12532 (dual 1:1:1.26 & 1:2CT)

4,5

LINE INTERFACE EVALUATION BOARD

DS40DB3

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS61575-IL1

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS61575-IL1