DATA SHEET
HFC - S 2BDS0
ISDN HDLC FIFO controller
with S/T interface
Copyright 1994 - 1997 Cologne Chip Designs
All Rights Reserved
The information presented can not be considered as
assured characteristics. Data can change without notice.
Parts of the information presented may be protected by
patent or other rights.
March 1997
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Contents
1 General description ..........................................................................................................................................4
1.1 Applications .................................................................................................................................................... 4
1.2 Mode description.............................................................................................................................................5
1.2.1 ISA-PC mode ...........................................................................................................................................5
1.2.2 Processor interface modes ........................................................................................................................ 5
2 Pin description ..................................................................................................................................................6
2.1 ISA-PC bus and microprocessor interface .......................................................................................................6
2.2 S/T interface transmit signals .......................................................................................................................... 8
2.3 S/T interface receive signals ............................................................................................................................ 8
2.4 SRAM Interface ..............................................................................................................................................8
2.5 Oscillator ......................................................................................................................................................... 9
2.6 PCM30 bus interface .......................................................................................................................................9
2.7 PCM30 Timeslot enable signals ...................................................................................................................... 9
2.8 Interrupt outputs ............................................................................................................................................10
2.9 Miscellaneous pins ........................................................................................................................................10
2.10 Power supply ...............................................................................................................................................10
2.11 RESET characteristics .................................................................................................................................11
3 Functional description....................................................................................................................................12
3.1 ISA-PC mode ................................................................................................................................................12
3.1.1 Programming of I/O addresses ...............................................................................................................12
3.1.2 ISA-PC bus interface ............................................................................................................................. 13
3.2 Processor mode .............................................................................................................................................14
3.2.1 DMA access in processor mode .............................................................................................................15
3.3 Register description .......................................................................................................................................16
3.3.1 FIFO control registers ............................................................................................................................ 16
3.3.2 Registers of the S/T section ................................................................................................................... 17
3.3.3 Registers of the PCM30 bus section ......................................................................................................18
3.3.4 Interrupt and status register .................................................................................................................... 19
3.4 Watchdog / timer ...........................................................................................................................................19
3.5 FIFOs ............................................................................................................................................................ 20
3.5.1 FIFO channel operation ......................................................................................................................... 21
3.5.1.1 Send channels (B1, B2 and D transmit) ......................................................................................... 21
3.5.1.2 FIFO full condition in send channels ............................................................................................. 22
3.5.1.3 Receive Channels (B1, B2 and D reiceive) .................................................................................... 22
3.5.1.4 FIFO full condition in receive channels ......................................................................................... 23
3.5.1.5 FIFO initialisation .......................................................................................................................... 24
3.5.2 Transparent mode of HFC-S .................................................................................................................. 24
3.6 External SRAM .............................................................................................................................................25
3.7 Busy synchronisation ....................................................................................................................................26
3.7.1 Busy synchronisation with status read ...................................................................................................26
3.7.2 Busy synchronisation with IOCHRDY ..................................................................................................27
4 Register bit description ..................................................................................................................................28
4.1 Register bit description of S/T section ...........................................................................................................28
4.2 Register bit description of PCM30 bus section ............................................................................................. 31
4.3 Register bit description of CONNECT register ............................................................................................. 33
4.4 Register bit description of interrupt, status and control registers ...................................................................34
5 Electrical characteristics ................................................................................................................................38
6 Timing characteristics....................................................................................................................................40
6.1 ISA-PC bus or processor access .................................................................................................................... 40
6.2 SRAM access ................................................................................................................................................41
6.3 PCM30 bus clock and data alignment for Mitel ST
TM
bus ............................................................................42
6.4 PCM30 timing ...............................................................................................................................................42
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7 S/T interface circuitry ....................................................................................................................................44
7.1 External receiver circuitry ............................................................................................................................. 44
7.2 External transmitter circuitry ......................................................................................................................... 45
7.3 Oscillator circuitry .........................................................................................................................................47
8 State matrices for NT and TE........................................................................................................................48
8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT ................................................... 48
8.2 Activation/deactivation layer 1 for finite state matrix for TE ........................................................................49
9 Binary organisation of the frame ..................................................................................................................50
10 Clock synchronisation ..................................................................................................................................51
10.1 Clock synchronisation in NT-mode .............................................................................................................51
10.2 Clock synchronisation in TE-mode .............................................................................................................52
11 HFC-S package dimensions .........................................................................................................................53
12 ISDN PC card sample circuitry with HFC-S ..............................................................................................54
Figures
Figure 1: HFC-S block diagram ........................................................................................................................... 5
Figure 2: Pin Connection......................................................................................................................................6
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) .................................................... 21
Figure 4: FIFO Data Organisation..................................................................................................................... 22
Figure 5: Timing relations and delayed BUSY....................................................................................................26
Figure 6: Function of IOCHRDY ........................................................................................................................ 27
Figure 7: Function of the CONNECT register bits 0..2 ...................................................................................... 33
Figure 8: PCM30 bus clock and data alignment ................................................................................................ 42
Figure 9: External receiver circuitry................................................................................................................... 44
Figure 10: External transmitter circuitry............................................................................................................45
Figure 11: Oscillator Circuitry ........................................................................................................................... 47
Figure 12: Frame structure at reference point S and T ...................................................................................... 50
Figure 13: Clock synchronisation in NT-mode ...................................................................................................51
Figure 14: Clock synchronisation in TE-mode ...................................................................................................52
Figure 15: HFC-S package dimensions ..............................................................................................................53
Tables
Table 1: Selected I/O address after reset ............................................................................................................12
Table 2: DMA access in processor mode ............................................................................................................15
Table 3: SRAM size and FIFO depth................................................................................................................... 25
Table 4: S/T module part numbers and manufacturer ........................................................................................ 46
Table 5: Activation/deactivation layer 1 for finite state matrix for NT ............................................................... 48
Table 6: Activation/deactivation layer 1 for finite state matrix for TE................................................................ 49
Timing Diagrams
Timing Diagram 1: ISA-PC bus or processor access.......................................................................................... 40
Timing Diagram 2: SRAM access ....................................................................................................................... 41
Timing Diagram 3: PCM30 timing ..................................................................................................................... 42
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Features
Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-
channel
B1 and B2 transparent mode independently selectable
FIFO-depth: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel)
max. 31 HDLC frames (B-channel) and 15 HDLC fra mes (D-channel) per channel and
direction in FIFO
56 kbit/s restricted mode for U.S. ISDN lines selectable
full I.430 ITU S/T ISDN support in TE and NT mode
PCM30 interface configurable to interface MITEL ST
TM
bus (MVIP
TM
), Siemens IOM2
TM
or
GCI
TM
for external codecs
direct 8 bit ISA-PC bus interface with buffers for ISA-databus
One of 6 interrupt channels on ISA-PC bus selectable by software
Only 2 I/O-addresses used on ISA-PC bus
programmable ISA-I/O-addresses
microprocessor int erface compatible to Motorala bus and Siemens/Intel bus
simple DMA access to PCM30 interface for tone synthetisation
Timer with interrupt and watchdog capability in processor mode
3-5V supply voltage
rectangular QFP 100 case
1 General description
The HFC-S is an ISDN S/T HDLC basic rate controller for so called ,,passive" ISDN PC cards with
integrated S/T interface and PCM30 highway interface. It only needs an external SRAM to form a
high performance ISDN PC card. Most problems with passive ISDN PC cards as small FIFOs and
massive interrupt load for the host CPU are overcome by the HFC-S. So we call ISDN cards with the
HFC-S ,,semi-active".
Additionally the HFC-S can be used as a microprocessor peripheral in non-PC applications.
The FIFOs of the HFC-S are realized with an external SRAM. Also an industrial standard serial
interface for telecom peripheral ICs is implemented. Codecs are normally connected to this interface.
1.1 Applications
ISDN PC card
ISDN terminal adapter
ISDN PABX
ISDN modems
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1.2 Mode description
The HFC-S has 4 different bus modes, which can be selected by the lines ALE and IIOSEL0-
IIOSEL3. Depending on the selected mode the function of several pins is different (see:
Pin
description
).
1.2.1 ISA-PC mode
Mode 1:
ALE to GND, IIOSEL3-0 from 0001 to 1111
In mode 1 the HFC-S is addressed by two successive port addresses on the ISA-PC bus. The port
address is selected by the lines SA0 - SA9.
The address with SA0='1' is for register selection and the address with SA0='0' is used for data
read/write (see also: 3.1).
1.2.2 Processor interface modes
The processor modes are selected by IIOSEL3-0 = '0000' (see also 3.2).
Mode 2:
Motorola bus with control signals /CS, R/W, /DS is s elected by setting ALE to VDD.
Mode 3:
Siemens/Intel bus with seperated address bus and databus and control signals /CS,
/WR, /RD is selected by setting ALE to GND.
Mode 4:
Intel bus with multiplexed address and databus with control signals /CS, /WR, /RD,
ALE.
ALE latches the address. The address lines SA0-SA7 must be connected to the data
lines BD0-BD7.
The lines SA0-SA7 are used for direct addressing the internal registers of the HFC-S.
Figure 1: HFC-S block diagram
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