## Электронный компонент: CS3110X2 | Скачать: PDF ZIP |

- ENCODER FEATURES
- KEY METRICS AND SPECIFICATIONS
- APPLICATIONS
- BLOCK CODES FOR ERROR CORRECTION
- CS3110/CS3112 OPERATION
- Pin/Port Description
- Processor Interface
- RESET AND CLOCKING STRATEGY
- iNPUT dATA iNTERFACE
- OUTPUT DATA INTERFACE
- Definition of RS Code Implemented in the CS3110/CS3112
- Timing Characteristics
- Availability and Implementation Information

range of applications requiring forward error correction. These application specific cores are developed for high

data rate digital video and audio, satellite broadcast or data storage and retrieval applications and are fully

compliant with the European DVB (CS3110) and IntelSat (CS3112) Standards. The cores are configurable Reed-

Solomon encoders featuring user-selectable codeword length (50-255 symbols) and number of parity symbols

(0-20 symbols) providing up to 1.6 Gigabits per second data throughput. The CS3110 and CS3112 are available in

both ASIC and programmable logic versions that have been handcrafted by Amphion for optimal performance

while minimizing power consumption and silicon area.

Number of Parity Symbols (T)

block length and parity length

Reed Solomon Encoding

Intelsat IESS 308/309, European DVB

Telecommunication Standards ETS 300-421

and ETS 300-429

Byte-Wide Input and Output, Clocked by a

Single Symbol Rate Clock

Ease of Integration

larger systems

per Second Throughput

CS3110 (DVB compliant)

g(x)=(x+1)(x+a)(x+a

f(x)=x

g(x)=(x+a

f(x)=x

Digital Satellite Broadcast

Data Storage and Retrieval Systems

(e.g. Hard Disk Drives, CD-ROM, DVD, etc.

introduce controlled redundancy into a data sequence on the

transmission (encode) side of a communications channel. The

redundant information is then exploited by the receiver

(decoder) to overcome the effects of data corrupting channel

distortions and noise. Block codes are a type of channel coding

scheme characterized by the independent coding of successive

discrete blocks or groups of information bits with no

dependencies between successive blocks of data. Binary codes

operate on sequences of bits, whereas non-binary codes

encode data as multi-bit symbols 8 bits per symbol for most

applications. Reed-Solomon codes are a particularly powerful

type of non-binary, linear block code.

performance forward error correction (FEC) compliant with

digital video broadcast (DVB) standards and other

applications using Reed-Solomon. The cores are capable of

processing both burst and continuous data streams and input

and output will be symbol wide, clocked by a single symbol

rate clock. The implementation is low latency (2 symbol clock

into larger systems.

unaltered input data block followed by parity symbols at the

end of the code block; i.e., the encoders produce systematic

codes. As shown in Figure 1, the length of the input data

stream "K" ranges between 30 and 255 symbols with the out-

put data stream "N" a function of the input stream and the

number of parity symbols "T". N ranges between 50 to 255

symbols.

A section of storage is reserved for the generator polynomial

coefficients, the total number of symbols in the codeword

(codeword length), and the number of appended check

symbols (parity length). The codeword length and parity

length registers are written and read via standard processor

interface signals, as are the generator polynomial coefficients,

a series of stored constants covering the range of 0 to 20

appended parity symbols. The parity symbol calculation

block is responsible for producing the parity values from the

input data sequence and the generator polynomial

coefficients. The count and control circuitry performs internal

control operations and switches the output data stream

between the input information data stream and the generated

parity values.

stated, all signals are active high and bit (0) is the least significant bit.

sequence

valid information

valid information

length must be loaded into their appropriate registers via the processor interface. The addresses of the respective registers are

changes, its value and the values of the appropriate generator

coefficients must be loaded into their registers before error-

free encoding can commence. Values are loaded into their

respective registers by applying the correct address signal to

write enable signal. The inputs

on the write signal

registers can be read by applying the correct address signal to

Add and asserting the read enable signal

loaded to

the rising edge of the

registers holding the generator polynomial coefficients,

codeword length and parity length. These are written and

read using strobe signals present in the processor interface.

Additionally, all I/O signals are registered on the rising edge

of Clk, with the exception of Reset. When the reset signal

Reset is asserted, all registers will be set to zero value. The

codeword length register will be loaded with the value FF

parity length. The default code rate is therefore (255, 239).

data is present on

a clock enable and if de-asserted, the encoder will not sample

the signals at

requirement for the information sequence to be input in a

continuous stream. If

complete information sequence has been input, the encoder

will continue to clock out the output parity values, despite the

fact that the input data flow has stalled.

time as the first information symbol in a new sequence is

applied to

read. After

encoder,

cycle, to allow the parity symbols to be output. The only

exception to this scheme occurs if

at any time before a complete codeword has been output. In

current value on

sequence; and, output data values for the previous coded

block that have not yet emerged from the encoder will be lost.

If the values held in the generator polynomial coefficients,

codeword length and parity length registers are updated, the

updated register values are not applied until the next

assertion of

can be updated while the encoder is still processing the

previous block. All programmable parameters must be stable

one clock cycle before the beginning of the new information

sequence to which the updated parameters should be applied.

time as the first codeword symbol appears on

When valid information symbols are present on

output

ENCODER FEATURES
KEY METRICS AND SPECIFICATIONS
APPLICATIONS
BLOCK CODES FOR ERROR CORRECTION
CS3110/CS3112 OPERATION
Pin/Port Description
Processor Interface
RESET AND CLOCKING STRATEGY
iNPUT dATA iNTERFACE
OUTPUT DATA INTERFACE
Definition of RS Code Implemented in the CS3110/CS3112
Timing Characteristics
Availability and Implementation Information