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Электронный компонент: CS5210RQ

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TM
Virtual Components for the Converging World
Amphion continues to expand its family of application-specific cores
1
See http://www.amphion.com for a current list of products
CS5210-40
High Performance AES Encryption Cores
The CS5210-40 series of encryption cores
1
are designed to achieve data privacy and authenticity in digital
broadband, wireless, and multimedia systems. These high performance application specific silicon cores support
the AES (Rijndael) algorithm as described in the NIST Federal Information Processing Standard. They can be
used in conjunction with the CS5250-80 series of Amphion AES decryption cores to rapidly construct complete
security solutions. The CS5200 family of cores are available in both ASIC and programmable logic versions that
have been handcrafted by Amphion to deliver high performance while minimizing power consumption and
silicon area.
Figure 1: Example of a Secure Mobile Financial Transactions Using AES
1. Patent Pending
PDA
Virtual Private Network VPN)
Financial Institution
Compact AES
Ultra High Speed AES
High Speed AES
ENCRYPTION CORE FEATURES
Table 1: CS5210-40 Features at a Glance
CS5210
Standard
CS5220
Compact
CS5230
High Speed
CS5240
Ultra High
Speed
Fully compliant with AES NIST FIPS
128-bit data block
128-, 192-, 256-bit keys on-line selectable
128-bit keys only
32-bit I/O
128-bit I/O
Electronic Codebook mode (ECB)
Output Feedback mode (OFB)
Cipher Block Chaining mode (CBC)
Cipher Feedback mode (CFB)
2
CS5210-40
High Performance AES Encryption Cores
APPLICATIONS
Electronic financial transactions
-
eCommerce
-
Banking
-
Securities exchange
-
Point-of-Sale
Secure corporate communications
-
Storage Area Networks (SAN)
-
Virtual private networks (VPN)
-
Video conferencing
-
Voice services
Personal mobile communications
-
Video phones
-
PDA
-
Point-to-Point Wireless
-
Wearable computers
Secure environments
-
Satellite communications
-
Surveillance systems
-
Network appliances
CS5210-40 SYMBOL AND
PIN DESCRIPTION
Table 2 gives the descriptions of the input and output ports
(shown graphically in Figure 2) of the CS5210-40 series of AES
encryption cores. Unless otherwise stated, all signals are
active high and bit(0) is the least significant bit.
Figure 2: CS5210-40 Symbol
CS5210-40
CLK
RST
NKS
(CS5210 only)
LDKY
KADDR
KEY
LOAD
DADDR
D
KSTAT
DSTAT
QSTRB
QADDR
Q
3
TM
Table 2: CS5210-40 Standard Rijndael Encryption Interface Signal Definitions
Signal
I/O
Width (Bits)
Description
D
I
32 (128)
Plaintext data (128-bit width for CS5240)
DADDR
I
2
Plaintext data address, 0: the lowest 32-bit word
LDKEY
I
1
Load key enable
KEY
I
32 (128)
Cipher Key (128-bit width for CS5240)
KADDR
I
3
a
Cipher Key address, 0: the lowest 32-bit word
NKS
I
2
Cipher Key size select (CS5210 only)
When 00: Selects a 128-bit Key
When 01: Selects a 192-bit Key
When 1X: Selects a 256-bit Key
LOAD
I
1
Load Plaintext enable
CLK
I
1
System clock, rising edge active
RST
I
1
Asynchronous reset
KSTAT
O
1
Key port status. When Asserted, loading of cipher keys is not allowed
DSTAT
O
1
Input port status
The next cycle after text D[3] (the highest word of 128-bit clock) is loaded,
DSTAT will be De-asserted to indicate encryption is in progress. It will be
Asserted when the core is ready for loading the highest word of the next
128-bit text. The lower three words can be loaded at anytime in the
period when DSTAT is LOW depending on the key-size selection.
QSTRB
O
1
Output strobe indicating the Cipher text word Q is valid
QADDR
O
2
Cipher text data address, 0: the lowest 32-bit word
Q
O
32 (128)
Cipher text data (128-bit width for CS5240)
a. 3 bits wide for the standard; 2 bits wide for compact/high speed cores; not applicable for ultra high speed core
4
CS5210-40
High Performance AES Encryption Cores
FUNCTIONAL DESCRIPTION
The Rijndael algorithm is an iterated block cipher that
encrypts and decrypts data in 128-bit data blocks using a
128-bit, 192-bit, or 256-bit key. The algorithm consists of:
An initial data/key addition
Nine, eleven or thirteen rounds when the length is
128-bits, 192-bits, or 256-bits respectively
A final round which is a variation of the typical round
Figure 3 represents a block diagram of the Rijndael encryption
algorithm. A Rijndael round transforms the data using
permutations, non-linear substitutions, additions and Galois
field multiplications. The Rijndael key schedule consists of
two parts:
1.
Key Expansion - expands the cipher key into a linear
array of 4-byte words
2.
Round Key Selection - selection of the required number of
Round Keys from the expanded key array
All four versions of the Amphion AES encryption cores follow
the block diagram shown in Figure 3.
The CS5200 AES encryption cores are excellent complements
to other Amphion cores. For instance they can be combined
with the CS6100 Motion JPEG Encoder to rapidly construct a
secure surveillance system, and they can be combined with
the CS4191 ADPCM codec to achieve secure, high speed, high
channel-count speech processing in Voice-over-Packet (VoP)
systems.
The Amphion encryption/decryption cores are also an
excellent choice for VPN security ICs incorporated into
broadband switches, routers, firewalls and remote access
concentrators. Likewise, the cores are an ideal fit for the
Secure Socket Layer (SSL) channel ICs used in Web servers,
WAP gateways and other access applications requiring a high
number of parallel SSL channels to carry out eCommerce.
Figure 3: Block Diagram of CS5210-40 Series of Encryption Cores
Ciphertext
Control Logic
Input
Buffer
Key
Scheduler
Key
Buffer
Key
Plaintext
Round
Transformations
Output
Buffer
5
TM
AVAILABILITY AND IMPLEMENTATION INFORMATION
Hardware accelerated AES technology is governed internationally by export regulations. The Amphion AES cores listed in this
datasheet have been officially reviewed and classified by the UK Department of Trade and Industry and US Bureau of Export
Administration. These cores are licensed for immediate export to the following countries:
Austria
Australia
Belgium
Canada
Czech Republic
Denmark
Finland
France
Germany
Greece
Hungary
Ireland
Italy
Japan
Luxembourg
New Zealand
The Netherlands
Norway
Poland
Portugal
Spain
Sweden
Switzerland
United Kingdom
United States
For delivery to other destinations, please contact Amphion. Approval is subject to applicable export regulations. Licensees of the
Amphion AES cores are responsible for complying with applicable requirements for the re-export of electronics containing AES
technology.
ASIC CORES
For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers application
specific silicon cores that are pre-optimized to a targeted ASIC technology by Amphion experts.
Consult your local Amphion representative for product specific performance information, current availability of individual
products, and lead times on ASIC core porting.
Table 3: CS5210-40 Family of ASIC Cores Using TSMC 180 nm Process and Standard Cell Libraries
PRODUCT ID
LOGIC
GATES
CYCLES PER OPERATION
TIMING CONSTRAINT (MHz)
DATA RATE
(MBITS/SEC)
CS5210TK
18.2K
44
a
52
b
60
c
200
581
a
492
b
426
c
CS5220TK
14.8K
44
200
581
CS5230TK
27K
11
200
2327
CS5240TK
203K
1
200
25600
a. Implementation of 128-bit key length
b. Implementation of 192-bit key length
c. Implementation of 256-bit key length
6
CS5210-40
High Performance AES Encryption Cores
PROGRAMMABLE LOGIC CORES
For ASIC prototyping or for projects requiring the fast time-to-market of a programmable logic solution, Amphion delivers
programmable logic core solutions that offer the silicon-aware performance tuning found in all Amphion products, combined
with the rapid design times offered by today's leading programmable logic solutions.
Table 4: CS5210-40 Family of Programmable Logic Cores using Altera APEX20KE-1
PRODUCT ID
LOGIC USED
(LE)
MEMORY USED
(ESB)
CYCLES PER
OPERATION
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5210AA
1452
8
44
a
52
b
60
c
77.8
226
a
191
b
166
c
CS5220AA
869
8
44
105
305
CS5230AA
1167
20
11
85.9
999
Table 5: CS5210-40 Family of Programmable Logic Cores using Xilinx VirtexE-8
PRODUCT ID
SLICES
MEMORY USED
(BRAM)
CYCLES PER
OPERATION
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5210XE
696
4
44
a
52
b
60
c
94.7
275
a
233
b
202
c
CS5220XE
421
4
44
101
294
CS5230XE
573
10
11
91.2
1061
CS5240XE
2397
100
1
77.2
9882
a. Implementation of 128-bit key length
b. Implementation of 192-bit key length
c. Implementation of 256-bit key length
Table 6: CS5210-40 Family of Programmable Logic Cores using Xilinx Virtex2-5
PRODUCT ID
SLICES
MEMORY USED
(BRAM)
CYCLES PER
OPERATION
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5210X2
696
4
44
a
52
b
60
c
117.3
341
a
289
b
250
c
CS5220X2
403
4
44
120.2
350
CS5230X2
573
10
11
113.7
1323
CS5240X2
2181
100
1
85
10880
a. Implementation of 128-bit key length
b. Implementation of 192-bit key length
c. Implementation of 256-bit key length
Table 7: CS5210-40 Family of Programmable Logic Cores using Actel ProASICPlus
PRODUCT ID
DEVICE
CORE CELLS
MEMORY USED
(CELLS)
CYCLES PER
OPERATION
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5210RQ
APA150
3169
8
44
a
52
b
60
c
29.48
85
a
108
b
125
c
CS5220RQ
APA150
6144
8
44
43.43
128
a
CS5230RQ
APA300
2570
20
11
40.19
467
a
CS5240RQ
N/A
NM/A
N/A
N/A
N/A
N/A
a. Implementation of 128-bit key length
b. Implementation of 192-bit key length
c. Implementation of 256-bit key length
7
TM
Figure 4: Design Data Formats Supplied by Amphion
ASVC Data Formats
Supplied by AMPHION
Typical ASIC or FPGA Design Flow
(Conceptual)
Bit Accurate
C Model
RTL Simulation
Models
Testbench
(VHDL & Verilog)
Netlists
(Verilog, VHDL, EDIF, .bd)
FPGA Programming
Files
System-Level "C" Code simulation
Hardware RTL Development
RTL Simulation
Logic Synthesis
Gate-level analysis
(timing & functional)
Physical Design
CS5210-40
High Performance AES Encryption Cores
TM
Virtual Components for the Converging World
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441
1239
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Quebec
Canada
Tel:
(450) 455 5544
Fax: (450)
455
5543
Web: www.amphion.com
Email: info@amphion.com
ABOUT AMPHION
Amphion (formerly Integrated
Silicon Systems) is the leading
supplier of speech coding, video/
image processing and channel
coding application specific silicon
cores for system-on-a-chip (SoC)
solutions in the broadband,
wireless, and mulitmedia markets
2001-02 Amphion Semiconductor Ltd. All rights reserved.
Amphion, the Amphion logo and "Virtual Components for the Converging World" are trademarks of Amphion Semiconductor Ltd. All others are the property of
their respective owners.
8
07/02 Publication #: DS5210/40 v1.2
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