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Электронный компонент: CS5321X2

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TM
Virtual Components for the Converging World
Amphion continues to expand its family of application-specific cores
1
See http://www.amphion.com for a current list of products
CS5321-22
High Performance OCB-AES Encryption Cores
The CS5321 and CS5322 OCB-AES Encryption cores
1
are designed to provide simultaneous data privacy and
authenticity in digital broadband, wireless, and multimedia systems. These high performance application
specific silicon cores combine the efficiency of OCB authentication with the high security of Rijndael encryption
algorithms, offering a state-of-the-art authenticated-encryption scheme. The CS5321 and CS5322 cores provide
the high security functionality of OCB-AES for different applications based on the importance of required speed
and size. The CS5321 is a Compact OCB-AES and is suitable for applications like PDAs and Wireless LANs
where small size is crucial. The CS5322 is a High Speed OCB-AES and is appropriate for applications such as
Wireless LAN high speed network servers where speed of operation critical. The Amphion CS5321 and CS5322
cores are available in both ASIC and programmable logic versions that have been hand crafted by Amphion to
deliver high performance while minimizing power consumption and silicon area.
Figure 1: Example of a Secure Video Conferencing System Using OCB-AES Cores
1. Patent Pending
Physical
Layer
WLAN
802.11
WLAN Base
LAN Access
Control
OCB-AES
CS5321/22
Display
Motion
JPEG
ADPCM
Motion
JPEG
ADPCM
Camera
Physical
Layer
WLAN Remote
LAN Access
Control
OCB-AES
CS5331/32
CS5321/CS5322 FEATURES
Fully compliant with Rijndael AES NIST
FIPS 197
Offset Codebook mode (OCB)
On-the-fly key generation
128-bit data block
128-bit keys only
32-bit I/O
APPLICATIONS
Secure electronic transactions
-
Medical files
-
E-Commerce
-
Financial files
-
Securities exchange
-
Point-of-Sale
Secure corporate communications
-
Virtual Private Networks (VPN)
-
Video conferencing
-
Voice services
Personal mobile communications
-
Video phones
-
PDA
-
Point-to-Point Wireless
Secure distance learning
-
Corporate training
-
Universities
2
CS5321-22
High Performance OCB-AES Encryption Cores
CS5320 SYMBOL AND PIN
DESCRIPTION
Table 1 describes the input and output ports (shown
graphically in Figure 2) of the CS5321 and CS5322 Encryption
cores. Unless otherwise stated, all signals are active high and
bit (0) is the least significant bit.
Figure 2: CS5321-22 Symbol
CS5321/22
QSTRB
QNUMB
QTYPE
Q
QADDR
DSTAT
DNUMB
D
GTAG
DTYPE
DADDR
LOAD
CLK
RST
Table 1: CS5321-22 OCB-AES Encryption Interface Signal Definitions
Signal
I/O
Width
(Bits)
Description
LOAD
I
1
Load OCB data enable
DADDR
I
2
OCB data block address
DTYPE
I
2
OCB data block type; 0: Key, 1: Nonce, 2: Plaintext, 3: Last Plaintext
GTAG
I
1
Generate Tag
D
I
32
OCB input data Key, Nonce or Plaintext
DNUMB
I
4
Number of valid bytes, 0 for 16, applied to the last plaintext block only
CLK
I
1
System clock, rising edge active
RST
I
1
Asynchronous reset
DSTAT
O
2
OCB input data port status; DSTAT[1]: Core loading indicator, DSTAT[0]: Core ready
indicator. The data port status indicator has a 2 cycle latency
QSTRB
O
1
OCB output strobe indicating the ciphertext/tag word Q is valid
QADDR
O
2
OCB output data address; 0: the lowest 32-bit word
QTYPE
O
2
OCB output block type; 0: Ciphertext, 1: Last Ciphertext, 2: Tag
Q
O
32
OCB output data Ciphertext or Tag
QNUMB
O
4
Number of valid output bytes, 0 for 16, applied to the last ciphertext block only
3
TM
FUNCTIONAL DESCRIPTION
Offset Codebook Mode (OCB) is a parallelizable block cipher
mode of operation that provides both authenticity and
privacy when combined with encryption algorithms. OCB is
contained in the draft NIST FIPS for the modes of operation
for symmetric key block ciphers and OCB-AES has been
implemented in the IEEE wireless LAN standard 802.11i. The
Amphion CS5321 and CS5322 combine the OCB mode with
the Rijndael AES algorithm to provide efficient high security
functionality for a wide range of operations. These cores
integrate the Amphion CS5220/CS5230 AES Encryption cores
with the CS5320 OCB Controller core.
The CS5321 and CS5322 OCB-AES Encryption cores are
excellent compliments to other Amphion cores. For example,
they can be combined with the CS6750 MPEG-4 decoder to
rapidly construct a private broadcast system, or they can be
combined with the CS4190 ADPCM codec to achieve secure,
high speed, high channel-count speech processing in Voice-
over-Packet (VoP) systems. Figure 2 represents an overview
diagram of the CS5321/CS5322.
Figure 3: Block Diagram of the CS5321/CS5322 OCB-AES Encryption Cores
Input
Buffer
Amphion AES
Core
Output
Buffer
Control
Logic
Checksum
Generator
Offset
Scheduler
Ciphertext
or Tag
Key, Nonce
or Plaintext
Control Signals
4
TM
AVAILABILITY AND IMPLEMENTATION INFORMATION
Hardware accelerated AES technology is governed internationally by export regulations. The Amphion OCB-AES cores listed in
this datasheet have been officially reviewed and classified by the UK Department of Trade and Industry and US Bureau of Export
Administration. These cores are licensed for immediate export to the following countries:
Austria
Denmark
Hungary
New Zealand
Spain
Australia
Finland
Ireland
The Netherlands
Sweden
Belgium
France
Italy
Norway
Switzerland
Canada
Germany
Japan
Poland
United Kingdom
Czech Republic
Greece
Luxembourg
Portugal
United States
For delivery to other destinations, please contact Amphion. Approval is subject to applicable export regulations. Licensees of the
Amphion AES cores are responsible for complying with applicable requirements for the re-export of electronics containing AES
technology.
OCB cores contain technology that is patent pending to Philip Rogaway of the University of California, Davis. Vendors are
obliged to contact Mr. Rogaway in order to license the technology.
ASIC CORES
For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers application
specific silicon cores that are pre-optimized to a targeted ASIC technology by Amphion experts.
Consult your local Amphion representative for product specific performance information, current availability of individual
products, and lead times on ASIC core porting.
Table 2: CS5321-CS5322 ASIC Cores Using TMSC 180 nm Process and Standard Cell Libraries
PRODUCT ID
LOGIC GATES
CYCLES PER
OPERATION
TIMING
CONSTRAINT (MHz)
DATA RATE
(MBITS/Sec)
a
a. Sustained data rate refers to the maximum throughput of plaintext/ciphertext
CS5321TK
24K
44
200
581
CS5322TK
37K
11
200
2327
Table 3: CS5321-CS5322 ASIC Cores Using TMSC 130 nm Process and Standard Cell Libraries
PRODUCT ID
LOGIC GATES
CYCLES PER
OPERATION
TIMING
CONSTRAINT (MHz)
DATA RATE
(MBITS/Sec)
a
a. Sustained data rate refers to the maximum throughput of plaintext/ciphertext
CS5321TM
28K
44
300
572
CS5322TM
44K
11
300
3490
5
TM
PROGRAMMABLE LOGIC CORES
For ASIC prototyping or for projects requiring fast time-to-market of a programmable logic solution, Amphion programmable
logic cores offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design times
offered by today's leading programmable logic solutions.
Table 4: CS5321-CS5322 Programmable Logic Cores Using Xilinx Virtex2-5
PRODUCT ID
LOGIC USED
(LUT)
MEMORY USED
(BRAM)
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5321X2
1376
4
82
238
CS5322X2
1543
10
82
954
Table 5: CS5321-CS5322 Programmable Logic Cores Using Altera APEX20KE-1
PRODUCT ID
LOGIC USED
(LE)
MEMORY USED
(ESB)
CLOCK SPEED
(MHz)
DATA RATE
(MBITS/Sec)
CS5321AA
3322
8
46
136
CS5322AA
3605
20
44
519
CS5321-22
High Performance OCB-AES Encryption Cores
TM
Virtual Components for the Converging World
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ABOUT AMPHION
Amphion (formerly Integrated
Silicon Systems) is the leading
supplier of speech coding, video/
image processing and channel
coding application specific silicon
cores for system-on-a-chip (SoC)
solutions in the broadband,
wireless, and mulitmedia markets.
2002 Amphion Semiconductor Ltd. All rights reserved.
Amphion, the Amphion logo, and "Virtual Components for the Converging World" are trademarks of Amphion Semiconductor Ltd. All others are the property of
their respective owners.
6
04/02 Publication #: DS55321-22 V1.0
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