TM
Virtual Components for the Converging World
Amphion continues to expand its family of application-specific cores
1
See http://www.amphion.com for a current list of products
MPEG-4 Video Decoder
Accelerators
CS676x Series Preliminary Product Brief
The CS676x family of accelerators enable high performance solutions for a wide range of MPEG-4 multimedia
applications requiring fast, reliable and efficient video decoding. These highly optimized hardware accelerators
(with associated software drivers) are designed to liberate the system of traditionally processor and bus intensive
tasks associated with real-time video decompression.
Figure 1: Example System Implementation
Input Video
Streams
Bridge
Options
Motion Data
(MV,Diff)
Pixel
Generation
Input
Bitstream
Processor
Bus
Controller
IQ Tables
ACDC Pred.
Frame
Memory
Memory IP
Amphion IP
Processor IP
KEY
Option:
Texture Coeffs.
passed directly
Option:
Shortcut for
texture info.
Final MV
Control Param
Display Out
Controller
Output
Video
RAM
Interface
Option: AMBA APB or AHB
AMBA AHB
Co-Processor
Interface
System
Controller
Option:
Direct Co-Processor Interface
FEATURES
Full compliance with ISO/IEC14496-2 simple
profile tools
-
Accelerator function set based on profiled
software decoder for optimum system parti-
tioning
-
Each accelerator can deal with absolute worst
case conditions for level definitions or more
Enhancements for full compliance with new
Advanced Simple Profile decoding profiles
and in some cases the MPEG-2 decoding
requirements
Motion compensation and pixel reconstruc-
tion controller
Flexible input bitstream processor
Pixel generation accelerator for Inverse DCT,
Quantization, ACDC and Scan processes
AMBA Bus compliant modules, most with
only peripheral mode requirements
ANSI C software API tasks for ease of integra-
tion into existing applications
Low power modes incorporated through
clock gating and sleep modes
Application example available through
Amphion's CS6750 full MPEG-4 decoder
Bit-accurate software models available for
integration and verification work
BENEFITS
Ease of integration
Low input clock rate requirements
Silicon efficient (All modules under 40K
gates)
Ultra Low power
ASIC and FPGA support
2
CS676x
MPEG-4 Video Decoder Accelerators
APPLICATIONS
3G mobile phones
PDAs
Personal Video Recorders
IP cameras
Digital cameras
Hard-disk camcorders
Surveillance & monitoring
Automotive
Set-top-box
Existing MPEG-4 applications requiring acceleration.
AVAILABILITY
The CS676x family of MPEG-4 decoder accelerators is
available with standard options from Q1 2002. Please contact
an Amphion representative for further information.
ACCELERATOR FUNCTION OVERVIEW
CS6760 MOTION COMPENSATION AND
PIXEL RECONSTRUCTION
This module has been primarily designed to cope with the
extra requirements of the new Advanced Simple Profile,
which the Simple Profile tools are a sub-set of. This core is not
part of the Amphion CS6750 Simple Profile decoder, but could
be added as a further speed-up option if required:
Activation and parameter setting via simple message
queue RAM
Direct link for Intra and Inter blocks of data from Pixel
generation unit
Motion compensation compliance with ISO/IEC1449-2
Simple profile and Advanced Simple profiles up to level 5
-
and PEL interpolation for non-integer motion vec-
tors
-
Forward, Backward, Bi-directional and direct modes
motion compensation
-
Up to four motion vectors per Macroblock
-
Unrestricted motion vectors
-
Interlaced motion compensation
Final motion vector calculation completed via optimized
software task
Pixel reconstruction
-
Including clipping, Intra block write-through and not-
coded block copies
Bus mastering capability to request predicted blocks and
to write-back reconstructed blocks
Enhanced Options:
Motion compensation compliance with ISO/IEC13818-2
(MPEG-2) MP@ML and MP@HL profiles
Global motion compensation
-
Available as optimized software task with accelerated
hardware filters for affine transforms
CS6761 PIXEL GENERATION
Full compliance with ISO/IEC14496 section 7.4.2 Inverse
Scan, 7.4.4 Inverse Quantization and 7.4.5 IDCT (simple
profile)
Inverse Scan patterns for Zig-Zag, Alternate-Horizontal
and Alternate-Vertical are selected on a per block basis
and automatically completed by writing coefficients to the
Coeff_In port of the block
-
Early termination possible to avoid storing complete
block
ACDC prediction accelerated through hardware opera-
tions for key cycle consuming parts and optimized soft-
ware tasks for remaining, compliant to ISO/IEC14496
section 7.4.3
-
Prediction direction calculation and predictor buffer
management completed in optimized software task
-
Hardware to complete DC and AC coefficient updates
with QP scaling
-
DC Quantized value returned from accelerator to
enable prediction direction calculation
Inverse Quantization
-
Method 2 with individual Quantization parameters,
Intra, Inter and Short header types methods.
-
Automatic Luminance and Chrominance block han-
dling
Inverse Discrete Cosine Transform
-
Compatible with IEEE Std 1180-1990
-
Single cycle per coefficient IDCT
Busy flag to determine when pixels are available for
downstream processes
Enhanced Options:
Shortcut path to Pixel Reconstruction unit if acceleration
unit used
MPEG-4 method 1 and MPEG-2 type Quantization
-
Multiple Quantization tables for individual object
streams. Constant default table loaded automatically
from initialisation
3
TM
CS6762 FLEXIBLE INPUT BIT STREAM
DECODER
De-multiplexor interface with capability for multiple
streams, up to four objects feasible within Simple profile.
Huffman table decode for all ISO/IEC14496 appendix B
Simple Profile relevant tables.
Get, Show and Jump bit handling for headers, and object
layer decoding.
Configurable wake-up level for the number of bytes within
the input buffer
Error State held until manually cleared to enable logging
of problems while completing a block decode.
Software task support delivers the full macroblock to the
downstream process.
-
Software tasks deliver full compliance with ISO/
IEC14496-2 sections 6 visual bitstream syntax and
7.4.1 variable length decoding simple profile
Enhanced Options:
Huffman tables for MPEG-2 streams
Bolt-on hardware macroblock decoder for minimum exe-
cution variance in decoding.
-
Decodes and sends texture data directly to suitable
Pixel generation core, including run length decoding
and escape code handling.
-
Queues control parameters and Motion Vectors for
software tasks to pass to suitable processes.
-
Full compliance with ISO/IEC14496-2 sections 6.2.6
and 6.2.7 with 7.4.1 variable length decoding.
CS676x
MPEG-4 Video Decoder Accelerators
TM
Virtual Components for the Converging World
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2002 Amphion Semiconductor Ltd. All rights reserved.
Amphion, the Amphion logo,"Virtual Components for the Converging World", are trademarks of Amphion Semiconductor Ltd. All others are the property of their
respective owners.
4
04/02 Publication #: PB676x v1.0
ABOUT AMPHION
Amphion (formerly Integrated
Silicon Systems) is the leading
supplier of speech coding, video/
image processing and channel
coding application specific silicon
cores for system-on-a-chip (SoC)
solutions in the broadband,
wireless, and mulitmedia markets
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