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Электронный компонент: CX11656

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Doc. No. 102069A
August 19, 2002
CX11656
CX11656
CX11656
CX11656
HomePlug 1.0 PHY
HomePlug 1.0 PHY
HomePlug 1.0 PHY
HomePlug 1.0 PHY
Home Networking Physical
Home Networking Physical
Home Networking Physical
Home Networking Physical
Layer Device with Integrated
Layer Device with Integrated
Layer Device with Integrated
Layer Device with Integrated
Analog Front End Circuitry
Analog Front End Circuitry
Analog Front End Circuitry
Analog Front End Circuitry
Data Sheet (Preliminary)
Data Sheet (Preliminary)
Data Sheet (Preliminary)
Data Sheet (Preliminary)
Conexant Proprietary Information
Conexant Confidential Information
Dissemination, disclosure, or use of this information is not permitted
without the written permission of Conexant Systems, Inc.
CX11656 HomePlug 1.0 PHY Data Sheet
ii
Conexant Proprietary and Confidential Information
102069A
Revision Notice
Revision
Date
Comments
A
8/19/2002
Initial release.
2002 Conexant Systems, Inc.
All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are
provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
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CX11656 HomePlug 1.0 PHY Data Sheet
102069A
Conexant Proprietary and Confidential Information
iii
Contents
1. Introduction ......................................................................................................................................... 1-1
1.1
Overview .....................................................................................................................................................................1-1
1.2
Features ......................................................................................................................................................................1-3
1.3
Applications ................................................................................................................................................................1-3
2. Hardware Interface .............................................................................................................................. 2-1
2.1
CX11656 PHY Hardware Interface Signals...................................................................................................................2-1
2.2
CX11656 PHY Electrical and Environmental Specifications..........................................................................................2-9
3. CX11656 Functional Description.......................................................................................................... 3-1
3.1
MII Data Interface with MDI Control ............................................................................................................................3-2
3.1.1
MII Interface................................................................................................................................................3-3
3.1.1.1
MII Timing Diagram .................................................................................................................3-3
3.1.1.2
MII Signal Descriptions............................................................................................................3-6
3.1.1.3
MII Frame Structure.................................................................................................................3-8
3.1.2
MDI Control Interface ..................................................................................................................................3-9
3.1.2.1
MDI Signal Descriptions ........................................................................................................3-10
3.1.3
MII Management Register Set ...................................................................................................................3-10
3.1.3.1
PRE (Preamble) .....................................................................................................................3-10
3.1.3.2
ST (Start of Frame) ................................................................................................................3-10
3.1.3.3
OP (Operation Code) ..............................................................................................................3-11
3.1.3.4
PHYAD (PHY Address)...........................................................................................................3-11
3.1.3.5
REGAD (Register Address).....................................................................................................3-11
3.1.3.6
TA (Turnaround) ....................................................................................................................3-11
3.1.3.7
Data .......................................................................................................................................3-11
3.2
GPSI Interface with SPI Control.................................................................................................................................3-12
3.2.1
GSPI Interface ...........................................................................................................................................3-12
3.2.1.1
GPSI Timing Diagrams...........................................................................................................3-12
3.2.1.2
GPSI DC Characteristics.........................................................................................................3-14
3.2.1.3
GPSI Signal Descriptions .......................................................................................................3-14
3.2.2
SPI Slave Port Interface.............................................................................................................................3-15
3.2.2.1
SPI Slave Port Signal Timing .................................................................................................3-15
3.2.2.2
SPI Slave Port DC Characteristics ..........................................................................................3-16
CX11656 HomePlug 1.0 PHY Data Sheet
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Conexant Proprietary and Confidential Information
102069A
3.3
Clocks .......................................................................................................................................................................3-16
3.4
AFE Interface .............................................................................................................................................................3-17
3.4.1
ADC/DAC Interface ....................................................................................................................................3-17
3.4.1.1
ADC/DAC Timing Diagrams....................................................................................................3-17
3.4.1.2
DAC DC Characteristics..........................................................................................................3-19
3.4.1.3
ADC DC Characteristics..........................................................................................................3-19
3.4.2
AGC Circuitry.............................................................................................................................................3-20
3.4.2.1
AGC DC Characteristics..........................................................................................................3-20
3.5
SPI Master Interface..................................................................................................................................................3-21
3.5.1
SPI Master Interface Timing ......................................................................................................................3-21
3.5.2
SPI Master Interface DC Characteristics ....................................................................................................3-21
3.6
LED Interface.............................................................................................................................................................3-22
4. Package Dimensions............................................................................................................................ 4-1
5. Application Designs ............................................................................................................................. 5-1
5.1
Ethernet Router Application.........................................................................................................................................5-1
5.2
USB Application ..........................................................................................................................................................5-2
5.3
Embedded Application.................................................................................................................................................5-3
5.4
ADI-Related Components ............................................................................................................................................5-3
CX11656 HomePlug 1.0 PHY Data Sheet
102069A
Conexant Proprietary and Confidential Information
v
Figures
Figure 1-1. CX11656 HomePlug 1.0 PHY Simplified Hardware Interface..........................................................................1-1
Figure 1-2. CX11656 HomePlug 1.0 PHY Functional Block Diagram................................................................................1-2
Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP ............................................................................2-2
Figure 2-2. CX11656 PHY Pin Signals - 144-Pin LQFP ....................................................................................................2-3
Figure 3-1. CX11656 PHY Block Diagram ........................................................................................................................3-1
Figure 3-2. MII Data Interface with MDI Control ..............................................................................................................3-2
Figure 3-3. MII TX Waveform ..........................................................................................................................................3-3
Figure 3-4. MII RX Waveform..........................................................................................................................................3-4
Figure 3-5. MII TX with Collision Based on RX Activity ....................................................................................................3-4
Figure 3-6. MII Receive Timing........................................................................................................................................3-5
Figure 3-7. MII Transmit Timing ......................................................................................................................................3-5
Figure 3-8. MII Flow Control Overview, Part 1 .................................................................................................................3-7
Figure 3-9. MII Flow Control Overview, Part 2 .................................................................................................................3-7
Figure 3-10. Partition of Serial Bit Stream to Nibble Stream ............................................................................................3-8
Figure 3-11. MDI Receive Timing ....................................................................................................................................3-9
Figure 3-12. MDI Transmit Timing...................................................................................................................................3-9
Figure 3-13. MDI Frame Structure .................................................................................................................................3-10
Figure 3-14. GPSI Data Interface with SPI Control.........................................................................................................3-12
Figure 3-15. GPSI Flow Control .....................................................................................................................................3-13
Figure 3-16. GPSI Transmit Timing ...............................................................................................................................3-13
Figure 3-17. GPSI Receive Timing .................................................................................................................................3-13
Figure 3-18. SPI Slave Port Timing................................................................................................................................3-16
Figure 3-19. AFE TX and RX Activity ..............................................................................................................................3-17
Figure 3-20. AFE Clock Waveforms................................................................................................................................3-17
Figure 3-21. AFE Transmit Timing Diagram ...................................................................................................................3-18
Figure 3-22. AFE Receive Timing Diagram .....................................................................................................................3-18
Figure 3-23. SPI Master Interface Signal Timing Diagram .............................................................................................3-21
Figure 4-1. Package Dimensions - 144-Pin LQFP.............................................................................................................4-1
Figure 5-1. Ethernet Router Application Block Diagram ...................................................................................................5-1
Figure 5-2. USB Application Block Diagram .....................................................................................................................5-2
Figure 5-3. Embedded Application Block Diagram ...........................................................................................................5-3