CX82100 Home Network Processor Data Sheet

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101306C

Revision Record

Revision

Date

Comments

4/18/2002

Revision C release.

3/14/2002

Revision B release.

8/31/2001

Initial release.

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Contents

Revision History .......................................................................................................................................... xiv

Introduction ......................................................................................................................................... 1-1

1.1

Scope..........................................................................................................................................................................1-2

1.2

Features ......................................................................................................................................................................1-2

1.3

General Hardware Overview.........................................................................................................................................1-3

1.3.1

Advanced Microcontroller Bus Architecture .................................................................................................1-6

1.3.2

ARM940T Processor ...................................................................................................................................1-6

1.3.3

ASB Decoder ...............................................................................................................................................1-6

1.3.4

ASB Arbiter..................................................................................................................................................1-7

1.3.5

ASB Masters................................................................................................................................................1-7

ARM940T Master.................................................................................................................................1-7

DMAC Master ......................................................................................................................................1-7

Host Interface Master ..........................................................................................................................1-7

1.3.6

ASB Slaves ..................................................................................................................................................1-8

ARM940T Slave ...................................................................................................................................1-8

External Memory Controller Slave........................................................................................................1-8

ASB-to-APB Bridge/DMAC ...................................................................................................................1-8

Internal ROM .......................................................................................................................................1-8

Internal RAM .......................................................................................................................................1-8

1.3.7

APB Functions .............................................................................................................................................1-9

EMAC Interface ....................................................................................................................................1-9

USB Interface.......................................................................................................................................1-9

General Purpose Input/Output Interface ...............................................................................................1-9

Clock Generation..................................................................................................................................1-9

Interrupt Controller ..............................................................................................................................1-9

1.4

Development Kits ........................................................................................................................................................1-9

1.5

Typical Applications...................................................................................................................................................1-10

1.5.1

Typical Home Networking Architecture ......................................................................................................1-10

1.6

References ................................................................................................................................................................1-13

1.7

Key Words.................................................................................................................................................................1-14

1.8

Conventions ..............................................................................................................................................................1-15

1.8.1

Data Lengths .............................................................................................................................................1-15

1.8.2

Register Descriptions ................................................................................................................................1-15

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CX82100 HNP Hardware Interface ....................................................................................................... 2-1

2.1

CX82100 HNP Hardware Interface Signals ..................................................................................................................2-1

2.1.1

CX82100-11/-12/-51/-52 Signal Interface and Pin Assignments ..................................................................2-1

2.1.2

CX82100-41/-42 Signal Interface and Pin Assignments...............................................................................2-1

2.1.3

CX82100 HNP Signal Definitions .................................................................................................................2-1

2.2

CX82100 HNP Electrical and Environmental Specifications........................................................................................2-17

2.2.1

DC Electrical Characteristics ......................................................................................................................2-17

2.2.2

Operating Conditions, Absolute Maximum Ratings, and Power Consumption............................................2-18

2.3

Optional GPIO and Host Signal Usage .......................................................................................................................2-19

2.4

Interface Timing and Waveforms...............................................................................................................................2-21

2.4.1

External Memory Interface (SDRAM).........................................................................................................2-21

2.4.2

Host Interface Timing ................................................................................................................................2-21

2.4.3

EMAC Interface Timing ..............................................................................................................................2-21

2.4.4

USB Interface Timing.................................................................................................................................2-21

2.4.5

GPIO Interface Timing ...............................................................................................................................2-21

2.4.6

Interrupt Timing ........................................................................................................................................2-22

2.4.7

Clock Reset Timing....................................................................................................................................2-22

2.4.8

Reset Timing .............................................................................................................................................2-22

2.5

Package Dimensions .................................................................................................................................................2-23

HNP Memory Architecture ................................................................................................................... 3-1

3.1

HNP Memory Map.......................................................................................................................................................3-1

3.2

Starting Addresses ......................................................................................................................................................3-3

3.2.1

ARM Vector Table........................................................................................................................................3-3

3.3

Endianness..................................................................................................................................................................3-4

3.4

Boot Procedure ...........................................................................................................................................................3-4

DMAC Interface Description................................................................................................................. 4-1

4.1

DMA Channel Definition ..............................................................................................................................................4-1

4.2

DMA Requests and Data Transfer................................................................................................................................4-1

4.3

Control Registers ........................................................................................................................................................4-2

4.4

DMAC Register Memory Map ......................................................................................................................................4-3

4.5

Control Register Formats.............................................................................................................................................4-4

4.5.1

DMAC x Current Pointer 1 (DMAC_{x}_Ptr1) ...............................................................................................4-4

4.5.2

DMAC x Indirect/Return Pointer 1 (DMAC_{x}_Ptr2)....................................................................................4-4

4.5.3

DMAC x Buffer Size Counter 1 (DMAC_{x}_Cnt1).........................................................................................4-4

4.5.4

DMAC x Buffer Size Counter 2 (DMAC_{x}_Cnt2).........................................................................................4-4

4.5.5

DMAC x Buffer Size Counter 3 (DMAC_{x}_Cnt3).........................................................................................4-5

4.6

Three Basic Modes of Address Generation ..................................................................................................................4-6

4.6.1

Source or Destination Mode ........................................................................................................................4-6

4.6.2

Circular Buffer Modes..................................................................................................................................4-6

Direct Circular Buffer ...........................................................................................................................4-6

Indirect Circular Pointer Table..............................................................................................................4-7

4.6.3

Linked List Mode .........................................................................................................................................4-9

Embedded Tail Linked List Descriptor Mode ........................................................................................4-9

Indirect/Table Linked List Descriptor Mode........................................................................................4-12

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Host Interface Description ................................................................................................................... 5-1

5.1

Master Mode ...............................................................................................................................................................5-1

5.1.1

Host Master Mode Interface Signals ............................................................................................................5-1

5.1.2

Flash Memory Interface ...............................................................................................................................5-3

5.1.3

Interfacing to Other Slave Devices ...............................................................................................................5-3

5.1.4

Host Master Mode DMA Engine...................................................................................................................5-3

Asynchronous DMA Transfer Mode .....................................................................................................5-3

Isochronous DMA Transfer Mode ........................................................................................................5-3

General DMA Information ....................................................................................................................5-4

5.1.5

Host Master Mode Timing (CX82100-11/-12/-51/-52) .................................................................................5-5

Host Master Mode Read Operation (Accessing an External Device) .....................................................5-5

Host Master Mode Write Operation (Accessing an External Device) .....................................................5-5

5.1.6

Host Master Mode Timing (CX82100-41/-42)..............................................................................................5-8

Host Master Mode Read Operation (Accessing an External Device) .....................................................5-8

Host Master Mode Write Operation (Accessing an External Device) .....................................................5-8

HRDY# Description (CX82100-41/-42) ................................................................................................5-9

5.2

Host Master Mode Register Memory Map .................................................................................................................5-12

5.3

Host Master Mode Registers .....................................................................................................................................5-13

5.3.1

Host Control Register (HST_CTRL: 0x002D0000)......................................................................................5-13

5.3.2

Host Master Mode Read-Wait-State Control Register (HST_RWST: 0x002D0004) ....................................5-14

5.3.3

Host Master Mode Write-Wait-State Control Register) (HST_WWST: 0x002D0008)..................................5-14

5.3.4

Host Master Mode Transfer Control Register (HST_XFER_CNTL: 0x002D000C)........................................5-14

5.3.5

Host Master Mode Read Control Register 1 (HST_READ_CNTL1: 0x002D0010) .......................................5-14

5.3.6

Host Master Mode Read Control Register 2 (HST_READ_CNTL2: 0x002D0014) .......................................5-15

5.3.7

Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018) .....................................5-15

5.3.8

Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C).....................................5-15

5.3.9

Host Master Mode Peripheral Size (MSTR_INTF_WIDTH: 0x002D0020) ...................................................5-15

5.3.10

Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024) (CX82100-41/-42) ...........5-16

5.3.11

Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)...........................................5-16

5.3.12

Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C) ....................................5-16

5.3.13

Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030) ............................................................5-16

5.3.14

Host Master Mode DMA Timers (HDMA_TIMERS: 0x002D0034) ..............................................................5-16

External Memory Controller Interface Description ............................................................................... 6-1

6.1

PC100 Compliant SDRAM Interface.............................................................................................................................6-1

6.2

Available Vendor SDRAM ICs and Features .................................................................................................................6-3

6.3

Supported Configurations............................................................................................................................................6-4

6.4

Access Cycles .............................................................................................................................................................6-4

6.5

Initialization.................................................................................................................................................................6-4

6.6

Refresh .......................................................................................................................................................................6-4

6.7

Read............................................................................................................................................................................6-5

6.8

Write ...........................................................................................................................................................................6-5

6.9

Throughput .................................................................................................................................................................6-5

6.10

EMC I/O Clock Interface and Timing ............................................................................................................................6-6

6.11

SRAM Interface ...........................................................................................................................................................6-7

6.12

EMC Register ..............................................................................................................................................................6-8

6.12.1

External Memory Control Register (EMCR: 0x00350010) ............................................................................6-8

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Ethernet Media Access Control Interface Description .......................................................................... 7-1

7.1

MAC Frame Format .....................................................................................................................................................7-2

7.2

Parameterized Values Used in Implementation ............................................................................................................7-3

7.3

EMAC Functional Features ...........................................................................................................................................7-4

7.4

EMAC Architecture ......................................................................................................................................................7-6

7.5

Media Independent Interface (MII) ..............................................................................................................................7-7

7.6

EMAC Interrupts..........................................................................................................................................................7-8

7.7

TMAC Architecture ......................................................................................................................................................7-9

7.7.1

Transmit Frame Structure............................................................................................................................7-9

7.7.2

Transmit Descriptor...................................................................................................................................7-11

7.7.3

Transmit Status (TSTAT) ...........................................................................................................................7-12

7.7.4

Sequence of Transmitter DMA Operation...................................................................................................7-14

7.8

RMAC Architecture....................................................................................................................................................7-15

7.8.1

Support for the Detection of Invalid MAC Frames ......................................................................................7-15

Condition 1 ........................................................................................................................................7-15

Condition 2 ........................................................................................................................................7-15

Condition 3 ........................................................................................................................................7-15

7.8.2

Support for the Reception Without Contention ..........................................................................................7-15

7.8.3

Support for the Reception With Contention ...............................................................................................7-16

7.8.4

Address Filtering........................................................................................................................................7-16

Setup Frame ......................................................................................................................................7-16

Perfect Address Filtering....................................................................................................................7-16

Example of a Perfect Address Filtering Setup Frame ..........................................................................7-17

Imperfect Address Filtering................................................................................................................7-18

Example of an Imperfect Address Filtering Setup Frame ....................................................................7-20

Address Filtering Modes ....................................................................................................................7-22

7.8.5

Receive Status Handling ............................................................................................................................7-23

7.8.6

Sequence of Receiver DMA Operation .......................................................................................................7-26

7.9

7-Wire Serial Interface (7-WS) ..................................................................................................................................7-27

7.10

EMAC Register Memory Map ....................................................................................................................................7-28

7.11

EMAC Registers ........................................................................................................................................................7-29

7.11.1

EMAC x Source/Destination DMA Data Register (E_DMA_1: 0x00310000 and E_DMA_2:
0x00320000).............................................................................................................................................7-29

7.11.2

EMAC x Destination DMA Data Register (ET_DMA_1: 0x00310020 and ET_DMA_2: 0x00320020) ...........7-29

7.11.3

EMAC x Network Access Register (E_NA_1: 0x00310004 and E_NA_2: 0x00320004) ..............................7-30

7.11.4

EMAC x Status Register (E_Stat_1: 0x00310008 and E_Stat_2: 0x00320008) ..........................................7-33

7.11.5

EMAC x Receiver Last Packet Register (E_LP_1: 0x00310010 and E_LP_2: 0x00320010) ........................7-34

7.11.6

EMAC x Interrupt Enable Register (E_IE_1: 0x0031000C and E_IE_2: 0x0032000C) .................................7-35

7.11.7

EMAC x MII Management Interface Register (E_MII_1: 0x00310018 and E_MII_2: 0x00320018) .............7-36

USB Interface Description.................................................................................................................... 8-1

8.1

UDC Data Path ............................................................................................................................................................8-3

8.1.1

USB Transmit Data Path (Endpoint IN Channel)...........................................................................................8-3

8.1.2

USB Receive Data Path (Endpoint OUT Channel) .........................................................................................8-4

8.2

USB Data Flow ............................................................................................................................................................8-5

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8.3

UDC Core ....................................................................................................................................................................8-6

8.3.1

Endpoint Buffer Format................................................................................................................................8-6

8.3.2

Example of Endpoint Buffer Encoding..........................................................................................................8-7

8.3.3

Loading of the EndPtBuf Configurations ......................................................................................................8-8

8.3.4

USB Command Handling .............................................................................................................................8-9

8.4

USB DMA Interface ...................................................................................................................................................8-10

8.4.1

DMA Receive Channel................................................................................................................................8-10

8.4.2

DMA Transmit Channel..............................................................................................................................8-12

8.5

Interrupt Endpoint .....................................................................................................................................................8-14

8.6

Summary of the Endpoints ........................................................................................................................................8-14

8.7

USB Register Memory Map .......................................................................................................................................8-15

8.8

USB Registers ...........................................................................................................................................................8-16

8.8.1

USB Source/Destination DMA Data Register 0 (U0_DMA: 0x00330000)....................................................8-16

8.8.2

USB Source/Destination DMA Data Register 1 (U1_DMA: 0x00330008)....................................................8-16

8.8.3

USB Source/Destination DMA Data Register 2 (U2_DMA: 0x00330010)....................................................8-16

8.8.4

USB Source/Destination DMA Data Register 3 (U3_DMA: 0x00330018)....................................................8-16

8.8.5

USB Destination DMA Data Register (UT_DMA: 0x00330020)...................................................................8-17

8.8.6

USB Configuration Data Register (U_CFG: 0x00330024) ...........................................................................8-17

8.8.7

USB Interrupt Data Register (U_IDAT: 0x00330028) .................................................................................8-17

8.8.8

USB Control Register 1 (U_CTR1: 0x0033002C) .......................................................................................8-18

8.8.9

USB Control Register 2 (U_CTR2: 0x00330030)........................................................................................8-20

8.8.10

USB Control Register 3 (U_CTR3: 0x00330034)........................................................................................8-21

8.8.11

USB Status (U_STAT: 0x00330038) ..........................................................................................................8-22

8.8.12

USB Interrupt Enable Register (U_IER: 0x0033003C) ................................................................................8-25

8.8.13

USB Status Register 2 (U_STAT2: 0x00330040) .......................................................................................8-26

8.8.14

USB Interrupt Enable Register 2 (U_IER2: 0x00330044) ...........................................................................8-28

8.8.15

UDC Time Stamp Register (UDC_TSR: 0x0033008C) ................................................................................8-29

8.8.16

UDC Status Register (UDC_STAT: 0x00330090)........................................................................................8-29

8.9

USB DMA Control Registers ......................................................................................................................................8-30

8.9.1

EP0_IN Transmit Increment Register (EP0_IN_TX_INC: 0x00330048) ......................................................8-30

8.9.2

EP0_IN Transmit Pending Register (EP0_IN_TX_PEND: 0x0033004C)......................................................8-30

8.9.3

EP0_IN Transmit qword Count Register (EP0_IN_TX_QWCNT: 0x00330050) ...........................................8-30

8.9.4

EP1_IN Transmit Increment Register (EP1_IN_TX_INC: 0x00330054) ......................................................8-30

8.9.5

EP1_IN Transmit Pending Register (EP1_IN_TX_PEND: 0x00330058)......................................................8-31

8.9.6

EP1_IN Transmit qword Count Register (EP1_IN_TX_QWCNT).................................................................8-31

8.9.7

EP2_IN Transmit Increment Register (EP2_IN_TX_INC: 0x00330060) ......................................................8-31

8.9.8

EP2_IN Transmit Pending Register (EP2_IN_TX_PEND: 0x00330064)......................................................8-31

8.9.9

EP2_IN Transmit qword Count Register (EP2_IN_TX_QWCNT).................................................................8-32

8.9.10

EP3_IN Transmit Increment Register (EP1_IN_TX_INC: 0x0033006C)......................................................8-32

8.9.11

EP3_IN Transmit Pending Register (EP3_IN_TX_PEND: 0x00330070)......................................................8-32

8.9.12

EP3_IN Transmit qword Count Register (EP3_IN_TX_QWCNT: 0x00330074) ...........................................8-32

8.9.13

EP_OUT Receive Decrement Register (EP_OUT_RX_DEC: 0x00330078)...................................................8-33

8.9.14

EP_OUT Receive Pending Register (EP_OUT_RX_PEND: 0x0033007C) ....................................................8-33

8.9.15

EP_OUT Receive Buffer Size Register (EP_OUT_RX_BUFSIZE: 0x00330084)............................................8-33

8.9.16

EP_OUT Receive qword Count Register (EP_OUT_RX_QWCNT: 0x00330080)..........................................8-33

8.9.17

USB Receive DMA Watchdog Timer Register (USB_RXTIMER: 0x00330094)............................................8-34

8.9.18

USB Receive DMA Watchdog Timer Counter Register (USB_RXTIMERCNT: 0x00330098)........................8-34

8.9.19

EP_OUT Receive Pending Interrupt Level Register (EP_OUT_RX_PENDLEVEL: 0x0033009C)...................8-34

8.9.20

USB Control-Status Register (U_CSR: 0x00330088) .................................................................................8-35

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General Purpose Input/Output Interface Description............................................................................ 9-1

9.1

GPIO Pin Description...................................................................................................................................................9-1

9.2

GPIO Register Memory Map........................................................................................................................................9-2

9.3

GPIO Registers............................................................................................................................................................9-3

9.3.1

GPIO Option Register for GPIO[39:37; 32] (GPIO_OPT: 0x003500B0) ........................................................9-3

9.3.2

GPIO Output Enable Register 1 for GPIO[15:14; 8:5] (GPIO_OE1: 0x003500B4) .........................................9-4

9.3.3

GPIO Output Enable Register 2 for GPIO[31; 27:16] (GPIO_OE2: 0x003500B8) ..........................................9-4

9.3.4

GPIO Output Enable Register 3 for GPIO[39:37; 32] (GPIO_OE3: 0x003500BC) ..........................................9-5

9.3.5

GPIO Data Input Register 1 for GPIO[15:14; 8:5] (GPIO_DATA_IN1: 0x003500C0) .....................................9-5

9.3.6

GPIO Data Input Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_IN2: 0x003500C4) ...........................9-6

9.3.7

GPIO Data Input Register 3 for GPIO[39:37; 32] (GPIO_DATA_IN3: 0x003500C8) ......................................9-6

9.3.8

GPIO Data Output Register 1 for GPIO[15:14; 8:5] (GPIO_DATA_OUT1: 0x003500CC) ...............................9-7

9.3.9

GPIO Data Output Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_OUT2: 0x003500D0) .....................9-8

9.3.10

GPIO Data Output Register 3 for GPIO[39:37; 32] (GPIO_DATA_OUT3: 0x003500D4) ................................9-9

9.3.11

GPIO Interrupt Status Register 1 for GPIO[15:14; 8:5] (GPIO_ISR1: 0x003500D8) ...................................9-10

9.3.12

GPIO Interrupt Status Register 2 for GPIO[31; 27:24; 22:16] (GPIO_ISR2: 0x003500DC) .........................9-10

9.3.13

GPIO Interrupt Status Register 3 for GPIO[39:37; 32] (GPIO_ISR3: 0x003500E0).....................................9-12

9.3.14

GPIO Interrupt Enable Register 1 for GPIO[15:14; 8:5] (GPIO_IER1: 0x003500E4) ...................................9-13

9.3.15

GPIO Interrupt Enable Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IER2: 0x003500E8) .........................9-14

9.3.16

GPIO Interrupt Enable Register 3 for GPIO[39:37; 32] (GPIO_IER3: 0x003500EC) ....................................9-15

9.3.17

GPIO Interrupt Polarity Control Register 1 for GPIO[15:14; 8:5] (GPIO_IPC1: 0x003500F0)......................9-16

9.3.18

GPIO Interrupt Polarity Control Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IPC2: 0x003500F4)............9-17

9.3.19

GPIO Interrupt Polarity Control Register 3 for GPIO[39:37; 32] (GPIO_IPC3: 0x003500F8).......................9-18

9.3.20

GPIO Interrupt Sensitivity Mode Register 1 for GPIO[15:14; 8:5] (GPIO_ISM1: 0x003500A0)...................9-19

9.3.21

GPIO Interrupt Sensitivity Mode Register 2 for GPIO[31; 27:24; 22:16] (GPIO_ISM2: 0x003500A4).........9-20

9.3.22

GPIO Interrupt Sensitivity Mode Register 3 for GPIO[39:37; 32] (GPIO_ISM3: 0x003500A8)....................9-21

10 Memory to Memory Transfer Input/Output ........................................................................................ 10-1

10.1

Operation ..................................................................................................................................................................10-1

10.2

M2M Register Memory Map......................................................................................................................................10-3

10.3

M2M Registers..........................................................................................................................................................10-3

10.3.1

Memory to Memory DMA Data Register (M2M_DMA: 0x00350000) .........................................................10-3

10.3.2

Memory to Memory DMA Transfer Control/Counter (M2M_Cntl: 0x00350004) .........................................10-3

11 Interrupt Controller Interface Description .......................................................................................... 11-1

11.1

INTC Register Memory Map ......................................................................................................................................11-1

11.2

INTC Registers ..........................................................................................................................................................11-1

11.2.1

Interrupt Level Assignment Register (INT_LA: 0x00350040) .....................................................................11-1

11.2.2

Interrupt Status Register (INT_Stat: 0x00350044).....................................................................................11-2

11.2.3

Interrupt Set Status Register (INT_SetStat: 0x00350048)..........................................................................11-4

11.2.4

Interrupt Mask Register (INT_Msk: 0x0035004C)......................................................................................11-4

11.2.5

Interrupt Mask Status Register (INT_Mstat: 0x00350090).........................................................................11-4

12 Timers Interface Description.............................................................................................................. 12-1

12.1

Programmable Periodic Timers .................................................................................................................................12-1

12.2

Watchdog Timer........................................................................................................................................................12-1

12.3

Timer Usage/SDRAM Refresh with Other Frequencies...............................................................................................12-2

12.4

Timer Registers Memory Map ...................................................................................................................................12-3

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12.5

Timer Registers.........................................................................................................................................................12-3

12.5.1

Timer 1 Counter Register (TM_Cnt1: 0x00350020) ...................................................................................12-3

12.5.2

Timer 2 Counter Register (TM_Cnt2: 0x00350024) ...................................................................................12-3

12.5.3

Timer 3 Counter Register (TM_Cnt3: 0x00350028) ...................................................................................12-4

12.5.4

Timer 4 Counter Register (TM_Cnt4: 0x0035002C) ...................................................................................12-4

12.5.5

Timer 1 Limit Register (TM_Lmt1: 0x00350030).......................................................................................12-4

12.5.6

Timer 2 Limit Register (TM_Lmt2: 0x00350034).......................................................................................12-4

12.5.7

Timer 3 Limit Register (TM_Lmt3: 0x00350038).......................................................................................12-5

12.5.8

Timer 4 Limit Register (TM_Lmt4: 0x0035003C).......................................................................................12-5

13 Clock Generation Interface Description .............................................................................................. 13-1

13.1

PLL Normal Mode .....................................................................................................................................................13-3

13.2

Generated Clocks ......................................................................................................................................................13-3

13.3

PLL Register Memory Map........................................................................................................................................13-5

13.4

PLL Registers............................................................................................................................................................13-5

13.4.1

FCLK PLL Register (PLL_F: 0x00350068)..................................................................................................13-5

13.4.2

BCLK PLL Register (PLL_B: 0x0035006C) ................................................................................................13-6

13.4.3

Low Power Mode Register (LPMR: 0x00350014)......................................................................................13-7

13.5

PLL Programming.....................................................................................................................................................13-8

13.6

Watchdog Timer Mode ..............................................................................................................................................13-9

13.7

PLL Bypass Mode .....................................................................................................................................................13-9

14 Register Map Summary ..................................................................................................................... 14-1

14.1

Register Type Definition ............................................................................................................................................14-1

14.2

Interface Registers Sorted by Supported Function.....................................................................................................14-2

14.3

Interface Registers Sorted by Address.......................................................................................................................14-6

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Figures

Figure 1-1. CX82100 HNP Major System Interface ..........................................................................................................1-3

Figure 1-2. CX82100 HNP Typical System Interface Residential Gateway Firewall plus Router Application ...................1-4

Figure 1-3. CX82100 HNP Typical System Interface Ethernet/HomePNA 2.0 Bridge Application ...................................1-4

Figure 1-4. CX82100 HNP Block Diagram........................................................................................................................1-5

Figure 1-5. Example of a Residential Gateway Firewall plus Router Application .............................................................1-11

Figure 1-6. Example of a HomePNA 2.0 Bridge Application............................................................................................1-12

Figure 2-1. CX82100-11/-12/-51/-52 HNP Hardware Interface Signals ............................................................................2-2

Figure 2-2. CX82100-11/-12/-51/-52 HNP Pin Signals-196-Pin FPBGA ...........................................................................2-3

Figure 2-3. CX82100-41/-42 HNP Hardware Interface Signals .........................................................................................2-5

Figure 2-4. CX82100-41/-42 HNP Pin Signals-196-Pin FPBGA ........................................................................................2-6

Figure 2-5. External Memory Interface Timing ...............................................................................................................2-21

Figure 2-6. Package Dimensions 196-Pin 15 mm x 15 mm FPBGA.............................................................................2-23

Figure 3-1. HNP Memory Map .........................................................................................................................................3-2

Figure 3-2. Little-Endian Mode Addressing ......................................................................................................................3-4

Figure 3-3. Boot Procedure..............................................................................................................................................3-5

Figure 4-1. Address Generation in Direct Circular Buffer Mode ........................................................................................4-6

Figure 4-2. Embedded Tail Linked List Descriptor Example............................................................................................4-10

Figure 4-3. Indirect/Table Linked List Descriptor Example 1 ..........................................................................................4-12

Figure 4-4. Indirect/Table Linked List Descriptor Example 2 ..........................................................................................4-13

Figure 5-1. Host Master Mode Signals.............................................................................................................................5-1

Figure 5-2. Little-Endian Mode Data Bus Mapping ...........................................................................................................5-2

Figure 5-3. Waveforms for Host Master Mode Read Operation (CX82100-11/-12/-51/-52)..............................................5-6

Figure 5-4. Waveforms for Host Master Mode Write Operation (CX82100-11/-12/-51/-52) .............................................5-7

Figure 5-5. Waveforms for Host Master Mode Read Operation (CX82100-41/-42) ........................................................5-10

Figure 5-6. Waveforms for Host Master Mode Write Operation (CX82100-41/-42) ........................................................5-11

Figure 6-1. SDRAM Interface...........................................................................................................................................6-1

Figure 6-2. EMC Clocking Interface..................................................................................................................................6-6

Figure 6-3. EMC I/O Timing .............................................................................................................................................6-6

Figure 7-1. MAC Sublayer Partition, Relationship to OSI Reference Model ......................................................................7-1

Figure 7-2. Ethernet MAC Frame Format..........................................................................................................................7-2

Figure 7-3. EMAC Functional Block Diagram....................................................................................................................7-6

Figure 7-4. MII Connector................................................................................................................................................7-7

Figure 7-5. EMAC Transmit Frame Structure .................................................................................................................7-10

Figure 7-6. TMAC DMA Operation for Channel {x} = 1 or 3.............................................................................................7-14

Figure 7-7. A Perfect Address Filtering Setup Frame Buffer ...........................................................................................7-17

Figure 7-8. A Circuit for Dividing by G(x).......................................................................................................................7-18

Figure 7-9. Imperfect Address Filtering..........................................................................................................................7-20

Figure 7-10. Example of Imperfect Filtering Setup Frame...............................................................................................7-21

Figure 7-11. Sequence of Receiver DMA Operation .......................................................................................................7-26

Figure 8-1. Block Diagram of the USB Interface...............................................................................................................8-2

Figure 8-2. USB Transmit Data Flow ................................................................................................................................8-3

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Tables

Table 1-1. CX82100 Order Numbers, Part Numbers, and Supported Features .................................................................1-1

Table 2-1. CX82100-11/-12/-51/-52 HNP Pin Signals 196-Pin FPBGA ..........................................................................2-4

Table 2-2. CX82100-41/-42 HNP Pin Signals 196-Pin FPBGA.......................................................................................2-7

Table 2-3. CX82100 HNP Pin Signal Definitions ..............................................................................................................2-8

Table 2-4. CX82100 HNP Input/Output Type Descriptions .............................................................................................2-16

Table 2-5. CX82100 HNP DC Electrical Characteristics ..................................................................................................2-17

Table 2-6. CX82100 HNP Operating Conditions .............................................................................................................2-18

Table 2-7. CX82100 HNP Absolute Maximum Ratings...................................................................................................2-18

Table 2-8. CX82100 HNP Power Consumption ..............................................................................................................2-18

Table 2-9. CX82100 HNP Recommended GPIO and Host Signal Use.............................................................................2-19

Table 2-10. CX82100 HNP Definitions of Recommended GPIO and Host Signals ..........................................................2-20

Table 3-1. Starting Addresses for Mapping ASB Slaves ...................................................................................................3-3

Table 3-2. Starting Addresses for Mapping APB Slaves ...................................................................................................3-3

Table 3-3. ARM Exception Vector Addresses ...................................................................................................................3-3

Table 4-1. DMA Channel Definition for DMAC..................................................................................................................4-1

Table 4-2. DMA Requests for APB Peripherals ................................................................................................................4-2

Table 4-3. DMAC Registers..............................................................................................................................................4-3

Table 4-4. Cluster Descriptor Table..................................................................................................................................4-7

Table 4-5. Received Data Packet......................................................................................................................................4-8

Table 5-1. Host Master Mode Signals ..............................................................................................................................5-2

Table 5-2. Chip Select Address Ranges ...........................................................................................................................5-3

Table 5-3. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)............5-6

Table 5-4. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52) ...........5-7

Table 5-5. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-41/-42) ......................5-10

Table 5-6. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-41/-42)......................5-11

Table 5-7. Host Master Mode Registers.........................................................................................................................5-12

Table 6-1. EMC SDRAM Interface Signal Descriptions.....................................................................................................6-2

Table 6-2. PC100 Compliant Mode Register ....................................................................................................................6-2

Table 6-3. Available SDRAM Vendors ..............................................................................................................................6-3

Table 6-4. Allowed SDRAM Configurations......................................................................................................................6-4

Table 6-5. SDRAM Throughput........................................................................................................................................6-5

Table 6-6. HNP to SDRAM/SRAM Interface Signal Mapping ............................................................................................6-7

Table 6-7. EMC Register..................................................................................................................................................6-8

Table 7-1. Parameterized Values Implemented in EMAC ..................................................................................................7-3

Table 7-2. Transmit Descriptor Format ..........................................................................................................................7-11

Table 7-3. Transmit Status Format ................................................................................................................................7-12

Table 7-4. Setup Frame Buffer Format ...........................................................................................................................7-17

Table 7-5. Imperfect Address Filtering Setup Frame Format ..........................................................................................7-19

Table 7-6. Hash Index Generated Using Ethernet CRC Algorithm...................................................................................7-20

Table 7-7. Address Filtering Mode .................................................................................................................................7-22

Table 7-8. Definition of RMAC Receive Status ...............................................................................................................7-24

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Table 7-9. 7-WS Interface Signals .................................................................................................................................7-27

Table 7-10. EMAC Registers ..........................................................................................................................................7-28

Table 8-1. Endpoint Buffer Format in UDC Core...............................................................................................................8-6

Table 8-2. Example of the EndPtBuf Encoding .................................................................................................................8-7

Table 8-3. DMA Channel Supporting USB Receive OUT Endpoints ................................................................................8-10

Table 8-4. Status qword for Receive (OUT) Endpoint APB Buffers .................................................................................8-11

Table 8-5. DMA Channels for USB Transmit IN Endpoints .............................................................................................8-12

Table 8-6. Descriptor qword for Transmit (IN) Endpoint TX DMA Packet Buffer ............................................................8-13

Table 8-7. Status qword for Transmit (IN) Endpoint TX DMA Packet Buffer...................................................................8-13

Table 8-8. UDC Endpoints..............................................................................................................................................8-14

Table 8-9. USB Registers...............................................................................................................................................8-15

Table 8-10. EP_OUT Receive Pending Level Register ....................................................................................................8-34

Table 9-1. GPIO Registers ...............................................................................................................................................9-2

Table 10-1. M2M Transfer Example 1 ............................................................................................................................10-1

Table 10-2. M2M Transfer Example 2 ............................................................................................................................10-2

Table 10-3. M2M Transfer Example 3 ............................................................................................................................10-2

Table 10-4. M2M Registers ...........................................................................................................................................10-3

Table 11-1. INTC Registers............................................................................................................................................11-1

Table 12-1. Timer Resolution and SDRAM Refresh Rate ...............................................................................................12-2

Table 12-2. Timer Registers ..........................................................................................................................................12-3

Table 13-1. FCLKIO/GPIO39 Pin Usage Control .............................................................................................................13-1

Table 13-2. BCLKIO/GPIO38 Pin Usage Control.............................................................................................................13-1

Table 13-3. FCLK PLL Generated Clocks........................................................................................................................13-4

Table 13-4. BCLK PLL Generated Clocks .......................................................................................................................13-4

Table 13-5. FCLK PLL Generated Clocks Programming Examples .................................................................................13-4

Table 13-6. BCLK PLL Generated Clocks Programming Examples .................................................................................13-4

Table 13-7. PLL Register Memory Map .........................................................................................................................13-5

Table 13-8. Desired Frequencies and Programming Parameters....................................................................................13-8

Table 13-9. Clocking Requirements ...............................................................................................................................13-9

Table 14-1. Register Type Definition..............................................................................................................................14-1

Table 14-2. CX82100 Interface Registers Sorted by Supported Function .......................................................................14-2

Table 14-3. CX82100 Interface Registers Sorted by Address.........................................................................................14-6

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Revision History

Changes Incorporated in Doc. No. 101306C

1. Table 1-1: Revised Order No.

2. Figure 2-3: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.

3. Figure 2-4: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.

4. Table 2-2: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.

5. Table 2-3: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.

6. Table 2-9: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5.

7. Table 2-10: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5.

Changes Incorporated in Doc. No. 101306B

1. Chapter 1: Revised maximum MIPS, added HRDY# paragraph, and added CX82100

HNP configuration differences to the introduction.

2. Table 1-1: Added models numbers and expanded table.

3. Section 1.5: Deleted.

4. Section 2.1.1: Revised section with applicability to CX82100-11/-12/-51/-52.

5. Section 2.1.2: Added section with applicability to CX82100-41/-42.

6. Section 2.1.3: Added heading.

7. Figure 2-1: Corrected pin number signals for M13 [HC08 (HRD#)], M12 [HC09

(HWR#)], and P14 [HC00 (HCS0#)/GPIO32].

8. Figure 2-1, Figure 2-2, and Table 2-1: Revised with applicability to CX82100-11/-

12/-51/-52.

9. Figure 2-3, Figure 2-4, and Table 2-2: Added with applicability to CX82100-41/-42.

10. Table 2-3: Revised VSSO pins, revised USBP and USBN interface resistor value,

HC00 pins, and HC10 pins, and GPIO17 and GPIO6 reset state.

11. Section 2.3 (Old): Deleted.

12. Figure 2-6: Corrected signal labels.

13. Table 5-1: Rearranged.

14. Section 5.1.5: Added reference to CX82100-11/-12/-51/-52.

15. Section 5.1.6: Added new section applicable to CX82100-41/-42.

16. Section 5.3.10: Added register description.

17. Section 13.1: Added PLL_F 168 MHz maximum operating frequency.

18. Table 13-3: Added PLL_F 168 MHz maximum operating frequency.

19. Table 13-5: Added PLL_F 168 MHz maximum operating frequency.

20. Section 13.4.1: Revised bits 25:24 (PLL_F_CR) description to add 84 MHz.

21. Table 13-8: Added Example 6 for 168 MHz desired frequency.

CX82100 Home Network Processor Data Sheet

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1-1

Introduction

The ConexantTM CX82100 Home Network Processor (HNP) is a single-chip, 185 MIPS
high performance, ARM940T-based processor integrated with multiple network interface
hardware functions and packaged into a 196-pin FPBGA. Embedded firmware supports
complete networking system solutions in a wide variety of commercial, industrial,
business, SOHO, and home applications with appropriate host software.

Typical applications include a Residential Gateway (RG) with network address
translation (NAT)/firewall services, or a HomePNA 2.0 or HomePlug 1.0 Bridge when
the CX82100 HNP is combined with a standard 10/100 Ethernet PHY or Home
Networking PHY such as Conexant's CX24611 HomePNA 2.0 PHY/AFE.

The CX82100 HNP is available in different models to support basic functions,
programmable HRDY# polarity for 802.11b applications, higher throughput (higher
FCLK frequency), and ability to run Intoto Firewall software (Table 1-1).

Table 1-1. CX82100 Order Numbers, Part Numbers, and Supported Features

Supported Functions

Home Network

Processor (HNP)
[196-pin FPBGA]

Order No./Part No.

Programmable

HRDY# Polarity for

802.11b Wireless

Interface

Max Clock Speed

(FCLK)

Supports Intoto

Firewall Software

CX82100-11

144 MHz

CX82100-12

144 MHz

Yes

CX82100-51

168 MHz

CX82100-52

168 MHz

Yes

CX82100-41*

Yes

168 MHz

CX82100-42*

Yes

168 MHz

Yes

* Recommended for new designs.

CX82100 HNP Configuration Differences:

1. CX82100-11 supports basic functions. HRDY#, for wireless applications, is not

supported. The CX82100-11 supports the following two signals on the indicated pins
(different from the CX82100-41): P13 = VSS0 and P14 = HC00 (HCS0#)/GPIO32
(see Section 2.1.1).

2. CX82100-12 supports basic functions and Intoto Firewall software. Same pinout as

the CX82100-11.

3. CX82100-51 supports basic functions and higher frequency operation (FCLK to 168

MHz). Same pinout as the CX82100-11.

4. CX82100-52 supports basic functions, higher frequency operation (FCLK to 168

MHz), and Intoto Firewall software. Same pinout as the CX82100-11 and CX82100-
12.

5. CX82100-41 supports basic functions and programmable HRDY# polarity for

wireless applications (see Section 5.1.6). The CX82100-41 supports the following
two signals on the indicated pins (different from the CX82100-11): P13 = HC00
(HCS0#)/GPIO32 and P14 = HC10 (HRDY#) (see Section 2.1.2). Recommended for
new designs.

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6. CX82100-42 supports basic functions, programmable HRDY# polarity for wireless

applications and Intoto Firewall software. Same pinout as the CX82100-41.
Recommended for new designs.

1.1

Scope

This document describes the CX82100 HNP hardware architecture.

1.2

Features

· Single-chip, high-performance processor with integrated network interfaces

- ARM940T processor
- Advanced Microcontroller Bus Architecture (AMBA) with two internal busses

Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)

- 16k x 32 internal ROM
- 8k x 32 internal RAM
- External Memory Controller (EMC)
- Two identical 10/100 Mbps IEEE 802.3 Ethernet Media Access Controllers

(EMACs) with MII/7-WS interfaces

- USB 1.1 Slave Interface
- General Purpose Input/Output (GPIO) signals
- Timers
- Interrupt Controller (INTC)
- Clock Generators

· ARM940T processor

- ARM9TDMI Core
- Advanced System Bus (ASB) interface
- Advanced Peripheral Bus (APB) interface
- Separate 4 kB instruction and 4 kB data caches
- Write-back cache scheme and write buffer optimize performance and minimize

ASB traffic

- Five-stage pipeline with fetch, decode, execute, memory and write stages
- `TrackingICE' mode allows a conventional ICE (in-circuit emulator) mode of

operation

· Dual Media Independent Interface (MII) interface to 10/100 Ethernet PHY
· Host Parallel Expansion Bus interface to Flash ROM and other devices
· Parallel interface to SDRAM/SRAM
· JTAG interface
· 22 general purpose I/O lines (13 available for application use, 6 available for

application use if optional signals for EEPROM, Host Parallel Expansion Bus, and
Clock are not used, and 3 dedicated to system signals)

· 196-pin FPBGA

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Figure 1-2. CX82100 HNP Typical System Interface Residential Gateway Firewall plus Router Application

101306-070

Control Logic

ARM940T Processor

CX82100 Home Network Processor (HNP)

Host

Interface

Random

Access

Mem ory

(RAM)

Read-Only

Mem ory

(ROM)

External
Mem ory

Controller

(EMC)

Universal

Serial Bus

(USB)

Interface

General

Purpose

Input/Output

(GPIO)

Interface

SDRAM

or SRAM

Flash ROM

Host

Parallel

Expansion

Bus

MII

LAN RJ-45

Ethernet Media

Access

Controller 1

(EMAC 1)

USB

Ethernet Media

Access

Controller 2

(EMAC 2)

EEPROM

10/100 Ethernet

Interface Devices

1 + 4-Port Switch

LAN RJ-45

10/100 Ethernet
Interface Device

MII

W AN RJ-45

Figure 1-3. CX82100 HNP Typical System Interface Ethernet/HomePNA 2.0 Bridge Application

10/100 Ethernet
Interface Device

101306-002

Control Logic

ARM940T Processor

CX82100 Home Network Processor (HNP)

Host

Interface

Random

Access

Mem ory

(RAM)

Read-Only

Mem ory

(ROM)

External
Mem ory

Controller

(EMC)

Universal

Serial Bus

(USB)

Interface

General

Purpose

Input/Output

(GPIO)

Interface

SDRAM

or SRAM

MII

LAN RJ-11

MII

W AN RJ-45

Ethernet Media

Access

Controller 1

(EMAC 1)

CX24611

HomePNA 2.0

PHY/AFE

100-Pin TQFP

USB

Ethernet Media

Access

Controller 2

(EMAC 2)

EEPROM

Flash ROM

Host

Parallel

Expansion

Bus

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1.3.1

Advanced Microcontroller Bus Architecture

The HNP internal architecture is based on the Advanced Microcontroller Bus
Architecture (AMBA) which defines two internal busses, the Advanced System Bus
(ASB) and the Advanced Peripheral Bus (APB).

· The 32-bit ASB is a high performance, burst-mode, pipelined bus, which connects

multiple bus masters. The ASB supports internal interfaces to functions (blocks)
such as processor, on-chip memory, external memory controller, and DMA
controller.

· The 64-bit APB connects peripheral interface blocks to the ASB through the ASB-

to-APB Bridge/DMAC and is designed for minimal power consumption and reduced
complexity to support the system's peripheral functions such as Timers, EMACs,
and the USB interface.

There are three other components of the AMBA system: the ASB Decoder, ASB Arbiter,
and the ASB-to-APB Bridge.

· The ASB Decoder decodes the addresses for all the ASB slave devices.
· The ASB Arbiter assigns the ASB ownership to ASB masters.
· All APB devices are accessible by ASB masters through the ASB-to-APB Bridge.

1.3.2

ARM940T Processor

The HNP uses an ARM940T Harvard Load/Store Architecture cached processor
macrocell with a high performance 32-bit RISC-based ARM9TDMI Core. The "TDMI"
stands for Thumb 16-bit compressed instruction set, Debug extensions, Multiplier
enhanced, and ICE extension.

Separate 4 kB instruction and 4 kB data caches and a memory protection unit allow the
memory to be segmented and protected in a simple manner. A write-back cache scheme
and write buffer are used to optimize performance and minimize ASB traffic.

The ARM940T uses a 5-stage pipeline consisting of fetch, decode, execute, memory and
write stages. The ARM940T interfaces to the other internal HNP blocks using unified
address and data busses compatible with the AMBA bus architecture. The ARM940T
also has a `TrackingICE' mode that allows a conventional ICE (in-circuit emulator) mode
of operation.

The ARM9TDMI Core has two active-low and level-sensitive interrupt inputs, FIQ# and
IRQ#, which can occur asynchronously. The FIQ# is higher priority than IRQ# in that it
is serviced first when both interrupts assert simultaneously. Servicing an FIQ# disables
IRQ# until the FIQ# handler exits or re-enables IRQ#. An interrupt handler must always
clear the source of the interrupt. The vector addresses for IRQ# and FIQ# are
0x00000018 and 0x0000001C, respectively.

1.3.3

ASB Decoder

The ASB Decoder performs the address decoding and selects slaves appropriately.

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1.3.4

ASB Arbiter

The ASB Arbiter performs arbitration on the ASB to ensure that only one ASB master at
a time is allowed to initiate data transfers. No arbitration scheme is enforced, therefore,
either 'highest priority' or 'fair' access algorithms may be implemented, depending on the
application requirements.

1.3.5

ASB Masters

An ASB master can initiate read and write operations by providing address and control
information. The HNP contains three bus masters: the ARM940T, the Host Interface, and
the DMAC. Only one bus master is allowed to actively use the ASB at any one time. The
DMAC is both an ASB master and an APB master.

ARM940T Master

The ARM940T master transfers data to and from the internal ROM, internal SRAM, the
ASB-to-APB Bridge, and the external SDRAM/SRAM via the EMC. The ARM940T
master also transfers configuration register information directly to and from the DMAC.

DMAC Master

The DMAC master transfers data to and from the external SDRAM/SRAM via the EMC.
The EMC is the only ASB slave accessed by the DMAC master. The DMAC is integrated
with the ASB-to-APB Bridge because the DMAC is both an ASB master and an APB
master. Data transferred on the ASB is always a dword (32 bits). However, data
transferred on the APB is always a qword (64 bits) which requires valid data on the entire
64-bit APB data bus.

Host Interface Master

The Host Interface master transfers data over the Host Parallel Expansion Bus to and
from external Flash ROM and an optional peripheral (e.g., UART) via an internal
memory-mapped register set using two chip select/GPIO signals. The Host Interface
master operates asynchronously.

The Host Interface master can also be used as the Test Interface Controller (TIC) bus
master. The TIC is a low gate-count test interface module which allows externally
applied test vectors to be converted into internal bus transfers. The TIC can also be used
to read and write registers within the HNP from the external Host Interface pins. The TIC
uses a minimal 3-wire handshake mechanism (TREQA, TREQB, and TACK) to control
the application of test vectors and the data path of the EMC.

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1.3.6

ASB Slaves

ASB slaves respond to read or write operations within a given address-space range. A bus
slave signals the success, failure, or waiting of the data transfer back to the active master.
The ASB slaves in the HNP ASIC are the ARM940T (test mode only), EMC, ASB-to-
APB Bridge/DMAC, internal ROM, and internal SRAM.

Detailed discussion of the AMBA signals and protocols may be found in Reference [3].

ARM940T Slave

The ARM940T slave has one 32-bit test-mode register that can be accessed by the TIC
during test mode.

External Memory Controller Slave

The External Memory Controller (EMC) controls all external SDRAM/SRAM accesses.
The SDRAM/SRAM is programmed by the EMC to transfer a burst of four data bytes.
The configuration registers for the EMC reside in the Host Control Register
(HST_CTRL) and the External Memory Control Register (EMCR).

The SDRAM refresh controller is internal to the EMC. The EMC simply asserts the wait
response to the ASB if it is deselected (by the ASB Decoder) during the refresh. The
master requesting the memory access is held off with wait states for the duration of the
refresh operation.

ASB-to-APB Bridge/DMAC

The ASB-to-APB Bridge converts ASB transfers into a suitable format for the slave
devices on the APB. The bridge provides latching of all address, data, and control signals,
as well as provides a second level of decoding to generate slave select signals for the
APB peripherals. The bridge is a slave on the ASB and a master on the APB. All
peripherals on the APB are slaves only.

As an ASB slave, the DMAC is accessed by the ARM940T and the Host Interface
(including the TIC ASB master in test mode). Obviously, the master portion of the
DMAC also has access, not via the ASB but internal to the DMAC module. Note that the
DMAC is also a bus master on the APB.

Internal ROM

The internal 16k x 32 ROM provides high-speed read-only program and data for the
ARM940T. The ARM940T uses this internal ROM or external Flash ROM to run the
boot code upon the de-assertion of the reset signal.

The internal ROM code configures the UDC with configuration data read from an
optional I2C EEPROM or internal ROM. The internal ROM code initiates UDC setup by
communicating to the I2C EEPROM using the I2C_DATA (GPIO15) and I2C_CLOCK
(GPIO16) pins. Based on the signature byte read from the I2C EEPROM, the HNP uses
either I2C EEPROM data or internal ROM data to set up the UDC. See Section for
additional information.

Internal RAM

The internal 8k x 32 RAM provides high-speed read-write program and data for the
ARM940T.

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1.3.7

APB Functions

The Advanced Peripheral Bus (APB) provides signaling for I/O functions.

EMAC Interface

Dual Media Independent Interface (MII) or 7-Wire Serial (7-WS) interfaces, controlled
by two identical HNP 10/100BaseT Ethernet MAC (EMAC) blocks, optionally connect
interchangeably to devices such as an Ethernet transceiver PHY, Conexant CX24611
HomePNA 2.0 AFE/PHY, Conexant CX11647 HomePlug 1.0 device.

USB Interface

The USB controlled by the HNP USB Interface optionally connects to a PC or USB hub.
This interface complies with the Universal Serial Bus Specification Rev. 1.1 and operates
at USB full speed (12 Mbps). It acts as a USB slave device only, i.e., it cannot act as a
root hub).

General Purpose Input/Output Interface

Bidirectional general purpose input/output (GPIO) lines are controlled by the HNP GPIO
Interface. Most of these GPIO lines are used for the interfaces mentioned above in a fully
configured system.

Clock Generation

The Clock Generation block generates internal and external clocks using two
programmable, fractional multiply phase locked loop (PLL) blocks, FCLK_PLL and
BCLK_PLL. Included in each block is the actual PLL circuit including a voltage-
controlled oscillator (VCO), and post-PLL generation logic which divides the output of
each PLL to create a series of sub-multiple clocks.

Interrupt Controller

All peripheral interrupt sources are routed through the Interrupt Controller (INTC) and
reduced to one of two active low inputs to the ARM940T processor, fast interrupt (FIQ#)
or regular interrupt (IRQ#), as selected in the Interrupt Level Assignment Register
(INT_LA). No hardware-assisted priority scheme is implemented in the HNP other than
FIQ# having a higher priority than IRQ#. The system software must implement the
priority scheme for individual interrupts in the FIQ# and IRQ# exception handlers.

1.4

Development Kits

Please contact a local Conexant sales office for information about available development
kits using the CX82100 HNP.

CX82100 Home Network Processor Data Sheet

2-2

Conexant Proprietary and Confidential Information

101306C

Figure 2-1. CX82100-11/-12/-51/-52 HNP Hardware Interface Signals

EM1_COL
EM1_CRS
EM1_MDC
EM1_MDIO
EM1_RX_CLK
EM1_RXD0
EM1_RXD1
EM1_RXD2
EM1_RXD3
EM1_RXDV
EM1_RXER
EM1_TX_CLK
EM1_TX_EN
EM1_TXD0
EM1_TXD1
EM1_TXD2
EM1_TXD3
EM1_TXER

EM2_COL
EM2_CRS
EM2_MDC
EM2_MDIO
EM2_RX_CLK
EM2_RXD0
EM2_RXD1
EM2_RXD2
EM2_RXD3
EM2_RXDV
EM2_RXER
EM2_TX_CLK
EM2_TX_EN
EM2_TXD0
EM2_TXD1
EM2_TXD2
EM2_TXD3
EM2_TXER

USBP
USBN
USB_PWR_DET (GPIO22)*

CLKI

HRST#

VGG

VDD

VDDA

VDDO

VSS
VSSA

VSSO

TST0
TST1
TST2
TST3

PLLBP

BOPT (GPIO14)*

TREQA

GPIO5
GPIO6
GPIO7
GPIO8
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO24
GPIO25
GPIO26
GPIO27
GPIO31
BCLKIO/GPIO38
FCLKIO/GPIO39

G1
G2

M8
G5

H4
H3
H1
H2

P8
E1

F1
F2
F5
F3

J12

B6
A6
C8

A14

A7
B7
E7
C7
D7

L13
J13

M14

K12

L12
L14

K14

D9
E8
C9

N14

H7, H8

A12, B3, B5,
D1, D14, F6,

F9, F12, H10,

J7, K7, K11,

N5, , N9, N11,

N13, P1

G7, G8

A5, B9, B11, D8

D12, F4, G9, H11

K13, L2, N8, P2

P5, P9,

P11, P13, C4

C5
B4
A4
D4

E6
D6
E5
D5
A3
A2
B2
B1
C3
A1

G4
C6

J5
J1

+3.3V

HAD00
HAD01
HAD02
HAD03
HAD04
HAD05
HAD06
HAD07
HAD08
HAD09
HAD10
HAD11
HAD12
HAD13
HAD14
HAD15

HC01
HC02
HC03
HC04
HC05
HC06
HC07

HAD16
HAD17
HAD18
HAD19
HAD20
HAD21
HAD22
HAD23
HAD24
HAD25
HAD26
HAD27
HAD28
HAD29

HC08 (HRD#)

HC09 (HWR#)

HC00 (HCS0#)/GPIO32

HAD31 (HCS4#)/GPIO37

MD00
MD01
MD02
MD03
MD04
MD05
MD06
MD07
MD08
MD09
MD10
MD11
MD12
MD13
MD14
MD15
MA00
MA01
MA02
MA03
MA04
MA05
MA06
MA07
MA08
MA09
MA10
MA11

MM0
MM1

MB0
MB1

MRAS#
MCAS#

MWE#

MCS#
MCLK

MCKE

I2C_DATA (GPIO15)**

I2C_CLOCK (GPIO16)**

TRST#

TCK

TMS

TDI

TDO

NC
NC
NC
NC
NC

P12
N12
L11
J10
M11
L10
K10
L9
M10
P10
N10
J9
K9
L8
M9
N7
P7
L6
P6
N6
K6
M6
L5
M5
L4
P4
N4
M4
P3
N3
M3
N1
N2
M1
M2
L1
L3
M13
M12
P14
J8

F11
E13
F10
F14
G11
F13
G10
G14
H9
G12
G13
H14
J11
H13
H12
J14
A10
B10
D10
C10
A11
F8
C11
D11
B12
A13
C12
B13
E11
E10
A9
E9
D13
C13
B14
C14
E14
E12

E2
E3

J4
K2
J6
K1
K3

C1
C2
D2
D3
F7

101306_066

CX82100

(-11/-12/-51/-52)

Home Network

Processor

(HNP)

196-Pin FPBGA

SDRAM

SRAM

MEDIA INDEPENDENT

INTERFACE 1 (MII 1)/

7-WIRE SERIAL

INTERFACE (7-WS1)

CLOCK

RESET CIRCUIT

JTAG

+3.3V OR +5V (CLAMP)

+1.8V

+1.8V (THROUGH FILTER)

PARALLEL
EXPANSION
BUS

D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
RD#
WE#
CS0# (Flash)

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQMH
DQML
BA0
BA1
RAS#
CAS#
WE#
CS#
CLKE
CLK

SDA
SCL

USB

INTERFACE

MEDIA INDEPENDENT

INTERFACE 2 (MII 2)/

7-WIRE SERIAL

INTERFACE (7-WS2)

Serial EEPROM
(Optional)

COL
CRS

MDC

MDIO

RX_CLK

RXD0
RXD1
RXD2
RXD3

RXDV
RXER

TX_CLK

TX_EN

TXD0
TXD1
TXD2
TXD3

TXER

COL
CRS

MDC

MDIO

RX_CLK

RXD0
RXD1
RXD2
RXD3

RXDV
RXER

TX_CLK

TX_EN

TXD0
TXD1
TXD2
TXD3

TXER

* Dedicated GPIO signal.
** May be assigned to different application use if not
used for indicated function.

4.7K

APPLICATION

DEPENDENT

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

2-3

Figure 2-2. CX82100-11/-12/-51/-52 HNP Pin Signals-196-Pin FPBGA

A10

B10

C10

D10

E10

F10

G10

H10

J10

K10

L10

M10

N10

P10

A11

B11

C11

D11

E11

F11

G11

H11

J11

K11

L11

M11

N11

P11

A12

B12

C12

D12

E12

F12

G12

H12

J12

K12

L12

M12

N12

P12

A13

B13

C13

D13

E13

F13

G13

H13

J13

K13

L13

M13

N13

P13

A14

B14

C14

D14

E14

F14

G14

H14

J14

K14

L14

M14

N14

P14

GPIO24

GPIO20

VDDO

EM1_TX_CLK

EM1_TX_EN

EM1_COL

EM1_RXD2

FCLKIO/GPIO39

TDI

HAD28

HAD26

HAD24

VDDO

GPIO18

GPIO19

I2C_DATA (GPIO15)

EM1_TXD0

EM1_CRS

EM1_RXD3

CLKI

TCK

VSSO

HAD27

HAD25

VSSO

TOP VIEW

101306_067

GPIO17

VDDO

GPIO21

GPIO16

EM1_TXD2

EM1_TXER

EM1_RXD1

PLLBP

TDO

HAD29

HAD23

HAD22

HAD21

TST2

TST1

VSSO

TST3

EM1_TXD3

VSSO

GPIO27

EM1_RXD0

TRST#

BOPT (GPIO14)

HAD17

HAD20

HAD19

HAD18

VSSO

VDDO

TST0

GPIO8

GPIO7

EM1_TXD1

EM1_RX_CLK

VSSA

BCLKIO/GPIO38

TREQA

HC07

HAD16

VDDO

VSSO

EM2_MDIO

EM2_MDC

GPIO31

GPIO6

GPIO5

VDD0

VDDA

VGG

TMS

HC05

HC02

HC06

HC04

HC03

EM2_RXD1

EM2_RXD2

EM2_RXDV

EM2_RXER

EM2_RXD3

VSS

VDD

VDDO

EM1_RXDV

GPIO25

HAD15

HC01

GPIO26

EM2_COL

EM2_RX_CLK

VSSO

USBN

MA05

VSS

VDD

HAD31 (HCS4#)/GPIO37

EM1_MDC

HAD13

EM1_MDIO

VSS0

EM1_RXER

MB0

VSSO

USB_PWR_DET (GPIO22)

USBP

MB1

VDDO

VSSO

MD08

HAD11

HAD12

HAD07

HAD14

VDDO

VSSO

MA00

MA01

MA03

MA02

MM1

MD02

MD06

VDDO

HAD03

HAD06

HAD05

HAD08

HAD10

HAD09

MA04

VSSO

MA06

MA07

MM0

MD00

MD04

VSSO

MD12

VDDO

HAD02

HAD04

VDDO

VSSO

VDDO

MA08

MA10

VSSO

MCKE

VDDO

MD09

MD14

EM2_CRS

EM2_TXD1

EM2_TXD2

HC09 (HWR#)

HAD01

HAD00

MA09

MA11

MCAS#

MRAS#

MD01

MD05

MD10

MD13

EM2_TX_EN

VSSO

EM2_TX_CLK

HC08 (HRD#)

VDDO

VSSO

EM2_RXD0

MWE#

MCS#

VDDO

MCLK

MD03

MD07

MD11

MD15

EM2_TXER

EM2_TXD3

EM2_TXD0

HRST#

HC00 (HCS0#)/GPIO32

CX82100 Home Network Processor Data Sheet

2-4

Conexant Proprietary and Confidential Information

101306C

Table 2-1. CX82100-11/-12/-51/-52 HNP Pin Signals 196-Pin FPBGA

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

GPIO24

VSSO

EM1_RXD2

HAD13

GPIO18

USBP

EM1_RXD3

HAD07

GPIO17

D10

MA02

EM1_RXD1

L10

HAD05

TST2

D11

MA07

EM1_RXD0

L11

HAD02

VSSO

D12

VSSO

VSSA

L12

EM2_TXD2

EM2_MDIO

D13

MRAS#

VGG

L13

EM2_TX_CLK

EM2_RXD1

D14

VDDO

VDD

L14

EM2_TXD3

GPIO26

EM1_TX_CLK

VDD

HAD26

MB0

I2C_DATA (GPIO15)

MD08

HAD27

A10

MA00

I2C_CLOCK (GPIO16)

H10

VDDO

HAD23

A11

MA04

EM1_TXD3

H11

VSSO

HAD20

A12

VDDO

GPIO7

H12

MD14

HAD16

A13

MA09

GPIO5

H13

MD13

HC06

A14

EM2_RXD0

EM2_RXD3

H14

MD11

GPIO25

GPIO20

USBN

FCLKIO/GPIO39

EM1_MDIO

GPIO19

MB1

CLKI

HAD14

VDDO

E10

MM1

PLLBP

M10

HAD08

TST1

E11

MM0

TRST#

M11

HAD04

VDDO

E12

MCKE

BCLKIO/GPIO38

M12

HC09 (HWR#)

EM2_MDC

E13

MD01

TMS

M13

HC08 (HRD#)

EM2_RXD2

E14

MCLK

VDDO

M14

EM2_TXD0

EM2_COL

EM1_TX_EN

HAD31 (HCS4#)/GPIO37

HAD24

VSSO

EM1_TXD0

HAD11

HAD25

B10

MA01

EM1_TXD2

J10

HAD03

HAD22

B11

VSSO

J11

MD12

HAD19

B12

MA08

EM1_TXD1

J12

EM2_CRS

VDDO

B13

MA11

VDDO

J13

EM2_TX_EN

HC04

B14

MWE#

J14

MD15

HAD15

MA05

TDI

VSSO

VDDO

TCK

VDDO

GPIO21

F10

MD02

TDO

N10

HAD10

VSSO

F11

MD00

BOPT (GPIO14)

N11

VDDO

TST0

F12

VDDO

TREQA

N12

HAD01

GPIO31

F13

MD05

HC05

N13

VDDO*

EM2_RXDV

F14

MD03

VDDO

N14

HRST#

EM2_RX_CLK

EM1_COL

EM1_MDC

VDDO

USB_PWR_DET (GPIO22)

EM1_CRS

HAD12

VSSO

C10

MA03

EM1_TXER

K10

HAD06

HAD21

C11

MA06

GPIO27

K11

VDDO

HAD18

C12

MA10

EM1_RX_CLK

K12

EM2_TXD1

VSSO

C13

MCAS#

VDDA

K13

VSSO

HC03

C14

MCS#

VSS

K14

EM2_TXER

HC01

VDDO

VSS

HAD28

EM1_RXER

VSSO

G10

MD06

HAD29

P10

HAD09

TST3

G11

MD04

HAD17

P11

VSSO

GPIO8

G12

MD09

HC07

P12

HAD00

GPIO6

G13

MD10

HC02

P13

VSSO*

EM2_RXER

G14

MD07

EM1_RXDV

P14

HC00 (HCS0#)/GPIO32*

* Different from CX82100-41/-41.

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

2-5

Figure 2-3. CX82100-41/-42 HNP Hardware Interface Signals

EM1_COL
EM1_CRS
EM1_MDC
EM1_MDIO
EM1_RX_CLK
EM1_RXD0
EM1_RXD1
EM1_RXD2
EM1_RXD3
EM1_RXDV
EM1_RXER
EM1_TX_CLK
EM1_TX_EN
EM1_TXD0
EM1_TXD1
EM1_TXD2
EM1_TXD3
EM1_TXER

EM2_COL
EM2_CRS
EM2_MDC
EM2_MDIO
EM2_RX_CLK
EM2_RXD0
EM2_RXD1
EM2_RXD2
EM2_RXD3
EM2_RXDV
EM2_RXER
EM2_TX_CLK
EM2_TX_EN
EM2_TXD0
EM2_TXD1
EM2_TXD2
EM2_TXD3
EM2_TXER

USBP
USBN
USB_PWR_DET (GPIO22)*

CLKI

HRST#

VGG

VDD

VDDA

VDDO

VSS
VSSA

VSSO

TST0
TST1
TST2
TST3

PLLBP

BOPT (GPIO14)*

TREQA

GPIO5
GPIO6
GPIO7
GPIO8
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO24
GPIO25
GPIO26
GPIO27
GPIO31
BCLKIO/GPIO38
FCLKIO/GPIO39

G1
G2

M8
G5

H4
H3
H1
H2

P8
E1

F1
F2
F5
F3

J12

B6
A6
C8

A14

A7
B7
E7
C7
D7

L13
J13

M14

K12

L12
L14

K14

D9
E8
C9

N14

H7, H8

A12, B3, B5,
D1, D14, F6,

F9, F12, H10,

J7, K7, K11,

N5, N9, N11, P1

G7, G8

A5, B9, B11,

C4, D8, D12,

F4, G9, H11,

K13, L2, N8, N13,

P2, P5, P9, P11

C5
B4
A4
D4

E6
D6
E5
D5
A3
A2
B2
B1
C3
A1

G4
C6

J5
J1

+3.3V

HAD00
HAD01
HAD02
HAD03
HAD04
HAD05
HAD06
HAD07
HAD08
HAD09
HAD10
HAD11
HAD12
HAD13
HAD14
HAD15

HC01
HC02
HC03
HC04
HC05
HC06
HC07

HAD16
HAD17
HAD18
HAD19
HAD20
HAD21
HAD22
HAD23
HAD24
HAD25
HAD26
HAD27
HAD28
HAD29

HC08 (HRD#)

HC09 (HWR#)

HC10 (HRDY#)

HC00 (HCS0#)/GPIO32

HAD31 (HCS4#)/GPIO37

MD00
MD01
MD02
MD03
MD04
MD05
MD06
MD07
MD08
MD09
MD10
MD11
MD12
MD13
MD14
MD15
MA00
MA01
MA02
MA03
MA04
MA05
MA06
MA07
MA08
MA09
MA10
MA11

MM0
MM1

MB0
MB1

MRAS#
MCAS#

MWE#

MCS#
MCLK

MCKE

I2C_DATA (GPIO15)**

I2C_CLOCK (GPIO16)**

TRST#

TCK

TMS

TDI

TDO

NC
NC
NC
NC
NC

P12
N12
L11
J10
M11
L10
K10
L9
M10
P10
N10
J9
K9
L8
M9
N7
P7
L6
P6
N6
K6
M6
L5
M5
L4
P4
N4
M4
P3
N3
M3
N1
N2
M1
M2
L1
L3
M13
M12
P14
P13
J8

F11
E13
F10
F14
G11
F13
G10
G14
H9
G12
G13
H14
J11
H13
H12
J14
A10
B10
D10
C10
A11
F8
C11
D11
B12
A13
C12
B13
E11
E10
A9
E9
D13
C13
B14
C14
E14
E12

E2
E3

J4
K2
J6
K1
K3

C1
C2
D2
D3
F7

101306_072

CX82100

(-41/-42)

Home Network

Processor

(HNP)

196-Pin FPBGA

SDRAM

SRAM

MEDIA INDEPENDENT

INTERFACE 1 (MII 1)/

7-WIRE SERIAL

INTERFACE (7-WS1)

CLOCK

RESET CIRCUIT

JTAG

+3.3V OR +5V (CLAMP)

+1.8V

+1.8V (THROUGH FILTER)

PARALLEL
EXPANSION
BUS

D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
RD#
WE#

CS0# (Flash)

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQMH
DQML
BA0
BA1
RAS#
CAS#
WE#
CS#
CLKE
CLK

SDA
SCL

USB

INTERFACE

MEDIA INDEPENDENT

INTERFACE 2 (MII 2)/

7-WIRE SERIAL

INTERFACE (7-WS2)

Serial EEPROM
(Optional)

COL
CRS

MDC

MDIO

RX_CLK

RXD0
RXD1
RXD2
RXD3

RXDV
RXER

TX_CLK

TX_EN

TXD0
TXD1
TXD2
TXD3

TXER

COL
CRS

MDC

MDIO

RX_CLK

RXD0
RXD1
RXD2
RXD3

RXDV
RXER

TX_CLK

TX_EN

TXD0
TXD1
TXD2
TXD3

TXER

* Dedicated GPIO signal.
** May be assigned to different application use if not
used for indicated function.

4.7K

APPLICATION

DEPENDENT

CX82100 Home Network Processor Data Sheet

2-6

Conexant Proprietary and Confidential Information

101306C

Figure 2-4. CX82100-41/-42 HNP Pin Signals-196-Pin FPBGA

A10

B10

C10

D10

E10

F10

G10

H10

J10

K10

L10

M10

N10

P10

A11

B11

C11

D11

E11

F11

G11

H11

J11

K11

L11

M11

N11

P11

A12

B12

C12

D12

E12

F12

G12

H12

J12

K12

L12

M12

N12

P12

A13

B13

C13

D13

E13

F13

G13

H13

J13

K13

L13

M13

N13

P13

A14

B14

C14

D14

E14

F14

G14

H14

J14

K14

L14

M14

N14

P14

GPIO24

GPIO20

VDDO

EM1_TX_CLK

EM1_TX_EN

EM1_COL

EM1_RXD2

FCLKIO/GPIO39

TDI

HAD28

HAD26

HAD24

VDDO

GPIO18

GPIO19

I2C_DATA (GPIO15)

EM1_TXD0

EM1_CRS

EM1_RXD3

CLKI

TCK

VSSO

HAD27

HAD25

VSSO

TOP VIEW

101306_073

GPIO17

VDDO

GPIO21

GPIO16

EM1_TXD2

EM1_TXER

EM1_RXD1

PLLBP

TDO

HAD29

HAD23

HAD22

HAD21

TST2

TST1

VSSO

TST3

EM1_TXD3

VSSO

GPIO27

EM1_RXD0

TRST#

BOPT (GPIO14)

HAD17

HAD20

HAD19

HAD18

VSSO

VDDO

TST0

GPIO8

GPIO7

EM1_TXD1

EM1_RX_CLK

VSSA

BCLKIO/GPIO38

TREQA

HC07

HAD16

VDDO

VSSO

EM2_MDIO

EM2_MDC

GPIO31

GPIO6

GPIO5

VDD0

VDDA

VGG

TMS

HC05

HC02

HC06

HC04

HC03

EM2_RXD1

EM2_RXD2

EM2_RXDV

EM2_RXER

EM2_RXD3

VSS

VDD

VDDO

EM1_RXDV

GPIO25

HAD15

HC01

GPIO26

EM2_COL

EM2_RX_CLK

VSSO

USBN

MA05

VSS

VDD

HAD31 (HCS4#)/GPIO37

EM1_MDC

HAD13

EM1_MDIO

VSS0

EM1_RXER

MB0

VSSO

USB_PWR_DET (GPIO22)

USBP

MB1

VDDO

VSSO

MD08

HAD11

HAD12

HAD07

HAD14

VDDO

VSSO

MA00

MA01

MA03

MA02

MM1

MD02

MD06

VDDO

HAD03

HAD06

HAD05

HAD08

HAD10

HAD09

MA04

VSSO

MA06

MA07

MM0

MD00

MD04

VSSO

MD12

VDDO

HAD02

HAD04

VDDO

VSSO

VDDO

MA08

MA10

VSSO

MCKE

VDDO

MD09

MD14

EM2_CRS

EM2_TXD1

EM2_TXD2

HC09 (HWR#)

HAD01

HAD00

MA09

MA11

MCAS#

MRAS#

MD01

MD05

MD10

MD13

EM2_TX_EN

VSSO

EM2_TX_CLK

HC08 (HRD#)

VSSO

HC00 (HCS0#)/GPIO32

EM2_RXD0

MWE#

MCS#

VDDO

MCLK

MD03

MD07

MD11

MD15

EM2_TXER

EM2_TXD3

EM2_TXD0

HRST#

HC10 (HRDY#)

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

2-7

Table 2-2. CX82100-41/-42 HNP Pin Signals 196-Pin FPBGA

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

GPIO24

VSSO

EM1_RXD2

HAD13

GPIO18

USBP

EM1_RXD3

HAD07

GPIO17

D10

MA02

EM1_RXD1

L10

HAD05

TST2

D11

MA07

EM1_RXD0

L11

HAD02

VSSO

D12

VSSO

VSSA

L12

EM2_TXD2

EM2_MDIO

D13

MRAS#

VGG

L13

EM2_TX_CLK

EM2_RXD1

D14

VDDO

VDD

L14

EM2_TXD3

GPIO26

EM1_TX_CLK

VDD

HAD26

MB0

I2C_DATA (GPIO15)

MD08

HAD27

A10

MA00

I2C_CLOCK (GPIO16)

H10

VDDO

HAD23

A11

MA04

EM1_TXD3

H11

VSSO

HAD20

A12

VDDO

GPIO7

H12

MD14

HAD16

A13

MA09

GPIO5

H13

MD13

HC06

A14

EM2_RXD0

EM2_RXD3

H14

MD11

GPIO25

GPIO20

USBN

FCLKIO/GPIO39

EM1_MDIO

GPIO19

MB1

CLKI

HAD14

VDDO

E10

MM1

PLLBP

M10

HAD08

TST1

E11

MM0

TRST#

M11

HAD04

VDDO

E12

MCKE

BCLKIO/GPIO38

M12

HC09 (HWR#)

EM2_MDC

E13

MD01

TMS

M13

HC08 (HRD#)

EM2_RXD2

E14

MCLK

VDDO

M14

EM2_TXD0

EM2_COL

EM1_TX_EN

HAD31 (HCS4#)/GPIO37

HAD24

VSSO

EM1_TXD0

HAD11

HAD25

B10

MA01

EM1_TXD2

J10

HAD03

HAD22

B11

VSSO

J11

MD12

HAD19

B12

MA08

EM1_TXD1

J12

EM2_CRS

VDDO

B13

MA11

VDDO

J13

EM2_TX_EN

HC04

B14

MWE#

J14

MD15

HAD15

MA05

TDI

VSSO

VDDO

TCK

VDDO

GPIO21

F10

MD02

TDO

N10

HAD10

VSSO

F11

MD00

BOPT (GPIO14)

N11

VDDO

TST0

F12

VDDO

TREQA

N12

HAD01

GPIO31

F13

MD05

HC05

N13

VSSO*

EM2_RXDV

F14

MD03

VDDO

N14

HRST#

EM2_RX_CLK

EM1_COL

EM1_MDC

VDDO

USB_PWR_DET (GPIO22)

EM1_CRS

HAD12

VSSO

C10

MA03

EM1_TXER

K10

HAD06

HAD21

C11

MA06

GPIO27

K11

VDDO

HAD18

C12

MA10

EM1_RX_CLK

K12

EM2_TXD1

VSSO

C13

MCAS#

VDDA

K13

VSSO

HC03

C14

MCS#

VSS

K14

EM2_TXER

HC01

VDDO

VSS

HAD28

EM1_RXER

VSSO

G10

MD06

HAD29

P10

HAD09

TST3

G11

MD04

HAD17

P11

VSSO

GPIO8

G12

MD09

HC07

P12

HAD00

GPIO6

G13

MD10

HC02

P13

HC00 (HCS0#)/GPIO32*

EM2_RXER

G14

MD07

EM1_RXDV

P14

HC10 (HRDY#)

* Different from CX82100-11/-12/-51/-52.

CX82100 Home Network Processor Data Sheet

2-8

Conexant Proprietary and Confidential Information

101306C

Table 2-3. CX82100 HNP Pin Signal Definitions

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

Power and Ground

VDD

H7, H8

PWR

Core Supply Voltage. Connect to +1.8V.

VDDA

PWR

Supply Voltage. Connect to +1.8V through filter.

VDDO

A12, B3, B5,
D1, D14, F6,
F9, F12, H10,
J7, K7, K11,
N5, N9, N11,
P1

PWR

I/O Supply Voltage. Connect to +3.3V.

VDDO

N13 (CX82100
-11/-12/-51/-52)

PWR

I/O Supply Voltage. Connect to +3.3V.

VGG

REF

I/O Clamp Power Supply. Connect to +5V if available, otherwise
connect to +3.3V.

VSS

G7, G8

GND

Core Ground. Connect to digital ground.

VSSA

GND

Ground. Connect to digital ground.

VSSO

A5, B9, B11,
C4, D8, D12,
F4, G9, H11,
K13, L2, N8,
P2, P5, P9,
P11

GND

I/O Ground. Connect to digital ground.

VSSO

N13 (CX82100
41/-42)

GND

I/O Ground. Connect to digital ground.

VSSO

P13 (CX82100
-11/-12/-51/-52)

GND

I/O Ground. Connect to digital ground.

System Control

HRST#

N14

Ith

Reset. Active low input asserted for at least 100

µs to reset the

HNP. All hardware registers are initialized to their default state.
Upon de-assertion of HRST#, the HNP executes the Boot Loader
code (see BOPT pin) then starts processing of the application
code.
Connect HRST# to a reset circuit.

BOPT (GPIO14)

I/O

Itpu/Ot4

Boot Loader Option. Upon de-assertion of the HRST# signal, the
Boot Loader code executes from internal ROM (BOPT pin high, i.e.,
open) or Flash ROM (BOPT pin low, i.e., connected to GND).
For normal operation, typically connect BOPT to GND through
4.7 k

to execute Boot Loader from Flash ROM.

PLLBP

Itpd

PLL Bypass Mode Select. If the PLLBP pin is high (test mode),
pins FCLKIO and BCLKIO are FCLKIO and BCLKIO inputs only
(i.e., not GPIO pins). If the PLLBP pin is low (normal operation),
pins FCLKIO and BCLKIO operate as FCLKIO/GPIO39 and
BCLKIO/GPIO38 as selected in the GPIO_OPT register).
For normal operation, connect PLLBP to GND through 4.7 k

Clock Interface

CLKI

Ith

Clock In. Connect to 35.328 MHz voltage controlled crystal
oscillator (VCXO) output through 51

BCLKIO/GPIO38

I/O

Itpu/Ot4

Bit Clock I/O. If PLLBP pin is high (test mode), this pin is BCLKIO
input only (i.e., not GPIO38). If the PLLBP pin is low (normal
operation), this pin can be used as GPIO38 or BCLKIO (see
GPIO_OPT register bit 6 and PLLBP pin).
For normal operation, BCLKIO output supplies the 25 MHz to the
LAN1 and LAN2 interfaces. Connect BCLKIO to the LAN 1 X1 pin
and to the LAN2 X1 pin though a single 51

resistor.

FCLKIO/GPIO39

I/O

Itpu/Ot4

Frame Clock I/O. If the PLLBP pin is high (test mode), this pin is
FCLKIO input only (i.e., not GPIO39). If the PLLBP pin is low
(normal operation), this pin can be used as GPIO39 or FCLKIO
(see GPIO_OPT register bit 7 and PLLBP pin).

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

2-9

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

USB Interface

USBP
USBN

D9
E8

I/O

Iu/Ou

USB Port. USBP and USBN are the differential data positive and
negative signals of the USB port. Connect USBP and USBN to
USB +Data and -Data, respectively, through 24

, and optionally

through a quick switch in order to isolate the USBP and USBN from
the USB during suspend mode.

USB_PWR_DET
(GPIO22)

It/Ot4

USB Power Detect. Active high input used to detect presence of
+5 V at the USB connector.

JTAG Interface

TRST#

Itpu

JTAG Reset. A high-to-low transition on this signal forces the TAP
controller into a logic reset state. This pin has an internal pullup.
Leave open for normal operation.

TCK

Itpu

JTAG Test Clock. This is the boundary scan clock input signal.
This pin has an internal pullup.
Leave open for normal operation.

TMS

Itpu

JTAG Test Mode Select. This signal controls the operation of the
TAP controller. This pin has an internal pull-up.
Leave open for normal operation.

TDI

Itpu

JTAG Test Input. This signal contains serial data that is shifted in
on the rising edge of TCK. The pin has an internal pullup.
Leave open for normal operation.

TDO

Otts4

JTAG Test Output Data. This is the three-stateable boundary scan
data output signal from the MCU, and it is shifted out on the falling
edge of TCK.
Leave open for normal operation.

Test Interface Controller (TIC) [Factory Test Only]

TREQA

Itpd

Reserved. This pin is connected to internal circuitry. Leave open.

CX82100 Home Network Processor Data Sheet

2-10

Conexant Proprietary and Confidential Information

101306C

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

EMAC 1 Interface

EM1_COL

Itpd

LAN 1 Collision Indication. In full-duplex mode, EM1_COL is
ignored. In half-duplex mode, EM1_COL is asserted by the LAN 1
EPHY upon detection of a collision on the medium, and remains
asserted while the collision condition persists.
For MII, connect to LAN 1 EPHY COL pin through 51

For 7-WS interface, connect to LAN 1 EPHY COL pin through
51

EM1_CRS

Itpd

LAN 1 Carrier Sense. In full-duplex mode, EM1_CRS is ignored.
In half-duplex mode, EM1_CRS is asserted by the LAN 1 EPHY
when either the transmit or receive medium is not idle. It is de-
asserted by the LAN 1 EPHY when both the transmit and receive
media are idle. The LAN 1 EPHY ensures that EM1_CRS remains
asserted throughout the duration of a collision condition, i.e., when
EM1_COL = 1.
For MII, connect to LAN 1 EPHY CRS pin through 51

For 7-WS interface, connect to LAN 1 EPHY CRS pin through
51

EM1_MDC

Otts4

LAN 1 Management Data Clock. EM1_MDC is sourced by the
Station Management entity (STA) of the EMAC as the timing
reference for transfer of information on the EM1_MDIO signal.
EM1_MDC is aperiodic and has no maximum high or low times.
The minimum high and low time for EM1_MDC is 160 ns each. The
minimum period for EM1_MDC is 400 ns.
For MII, connect to LAN 1 EPHY COL pin.
For 7-WS interface, leave open (not used).

EM1_MDIO

I/O

Itpd/Ot4

LAN 1 Serial Management Data Input/Output. EM1_MDIO is a
bidirectional signal used to transfer control and status information
between the LAN 1 EPHY and the STA in the EMAC.
For MII, connect to LAN 1 EPHY MDIO pin and to +3.3V through
4.7 K

For 7-WS interface, connect to LAN 1 EPHY MDIO pin and to
+3.3V through 4.7 K

EM1_RX_CLK

Itpd

LAN 1 Receive Clock. A 10 MHz square wave synchronized to the
Receive Data and only active while receiving an input bit stream.
EM1_RX_CLK is sourced by the LAN 1 EPHY. It provides the
timing reference for the transfer of EM1_RXDV, EM1_RXD[3:0],
and EM1_RXER signals from LAN 1 EPHY. The LAN 1 EPHY can
either recover EM1_RX_CLK from the received data or it may
derive EM1_RX_CLK from a nominal clock (e. g., the
EM1_TX_CLK reference). If loss of received signal from the
medium causes the LAN 1 EPHY to lose the recovered clock
reference, the LAN 1 EPHY must source the clock from a nominal
clock reference. Transitions from nominal clock to recovered clock
or vice versa are made only when EM1_RXDV is de-asserted.
During the interval between the assertion of EM1_CRS and the
assertion of EM1_RXDV at the beginning of a frame, the LAN 1
EPHY may extend a cycle of EM1_RX_CLK by holding it either
high or low until the LAN 1 EPHY has locked to the recovered
clock. Following the de-assertion of EM1_RXDV at the end of a
frame, the LAN 1 EPHY may extend a cycle of EM1_RX_CLK by
holding it either high or low for an interval not to exceed twice the
nominal clock period.
For MII, connect to LAN 1 EPHY RX_CLK pin 51

For 7-WS interface, connect to LAN 1 EPHY RX_CLK pin 51

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

2-11

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

EM1_RXD[3:0]

H2, H1, H3, H4

Itpd

LAN 1 Receive Data. For MII interface, EM1_RXD[3:0] are the 4-
bit parallel receive data lines. Connect EM1_RXD[3:0] to LAN 1
PHY RXD[3:0] through 51

For 7-WS interface, EM1_RXD3 is the Receive input bit stream.
Connect EM1_RXD3 to LAN 1 EPHY RXD pin through 51

EM1_RXD[2:0] are not used and should be left open.

EM1_RXDV

Itpd

LAN 1 Receive Data Valid. EM1_RXDV is asserted by the LAN 1
EPHY to indicate that the nibble on EM1_RXD[3:0] is valid. It
remains asserted for the received frame duration with the exception
of the preamble. It may or may not be asserted during the
preamble. EM1_RXDV is de-asserted prior to the first
EM1_RX_CLK period that follows the final nibble of a received
frame. When EM1_RXDV is de-asserted, the EMAC ignores
EM1_RXD[3:0].
For MII, connect to LAN 1 EPHY RX_DV pin through 51

For 7-WS interface, leave open (not used).

EM1_RXER

Itpd

LAN 1 Receive Error. EM1_RXER is driven by the LAN 1 EPHY. It
is asserted for one or more EM1_RX_CLK periods to indicate that
an error was detected somewhere in the frame presently being
transferred from the LAN 1 EPHY. The RMAC hardware will detect
this condition and declare such a frame invalid. While EM1_RXDV
is deasserted, EM1_RXER has no effect on the Reconciliation
sublayer (which lies between the MII and the MAC), therefore, it
has no effect on the MAC as well.
For MII, connect to LAN 1 EPHY RX_RXER pin through 51

For 7-WS interface, leave open (not used).

EM1_TX_CLK

Itpd

Transmit Clock. EM1_TX_CLK is sourced by the LAN 1 EPHY. It
provides the timing reference for the transfer of EM1_TX_EN,
EM1_TXD[3:0], and EM1_TXER signals to LAN 1 EPHY.
For MII, connect to LAN 1 EPHY TX_CLK pin through 51

For 7-WS interface, connect to LAN PHY TX_CLK pin through
51

EM1_TX_EN

Otts4

LAN 1 Transmit Enable. EM1_TX_EN is driven off the rising edge
and sampled on the rising edge of EM1_TX_CLK. It indicates that
the HNP is presenting nibbles on the MII for transmission.
EM1_TX_EN is asserted when the HNP has data to transmit over
the medium and remains asserted for the duration of the entire
transmitted frame. The HNP de-asserts EM1_TX_EN prior to the
rising edge of EM1_TX_CLK following the final nibble of a frame.
For MII, connect to LAN 1 EPHY TX_EN pin.
For 7-WS interface, connect to LAN 1 EPHY TX_EN pin.

EM1_TXD[3:0]

E4, F3, F5, F2

Otts4

LAN 1 Transmit Data. For MII interface, EM1_TXD[3:0] are the 4-
bit parallel transmit data lines. EM1_TXD[3:0] is driven off the rising
edge and sampled on the rising edge of EM1_TX_CLK. The entire
transmitted frame data is presented by the EM1_TXD[3:0] signal
lines, and commences on the first leading edge of EM1_TX_CLK
subsequent to EM1_TX_EN assertion. For each EM1_TX_CLK
period in which EM1_TX_EN is asserted, EM1_TXD[3:0] are
accepted for transmission by the LAN 1 EPHY. All fields except for
the FCS are transmitted with the least significant nibble first. The
LSb of each nibble is placed on EM1_TXD0. Connect
EM1_TXD[3:0] to LAN 1 EPHY TXD[3:0] through 51

For 7-WS interface, EM1_TXD3 is the transmit input bit stream.
Connect EM1_TXD3 to LAN 1 EPHY TXD pin. EM1_TXD[2:0] are
not used and should be left open.

CX82100 Home Network Processor Data Sheet

2-12

Conexant Proprietary and Confidential Information

101306C

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

EM1_TXER

Otts4

LAN 1 Transmit Coding Error. When EM1_TXER is asserted for
one or more EM1_TX_CLK periods while EM1_TX_EN is also
asserted, the LAN 1 EPHY emits one or more symbols that are not
part of the valid data or delimiter set somewhere in the frame being
transmitted. Permissible encoding of EM1_TXER with EM1_TX_EN
and EM1_TXD[3:0] are:

EM1_TX_EN EM1_TXER EM1_TXD[3:0]

Description

00001111 Normal Inter-Frame

00001111 Reserved

00001111 Normal Data

Transmission

00001111 Transmit Error

Propagation

For MII, connect to LAN 1 EPHY TXER pin.
For 7-WS interface, leave open.

EMAC 2 Interface

The EMAC 2 interface is the same as the EMAC 1 interface. Refer to the EMAC1 interface for signal definitions.
EM2_COL

Itpd

LAN 2 Collision Indication.

EM2_CRS

J12

Itpd

LAN 2 Carrier Sense.

EM2_MDC

Otts4

LAN 2 Management Data Clock.

EM2_MDIO

I/O

Itpd/Ot4

LAN 2 Serial Management Data Input/Output.

EM2_RX_CLK

Itpd

LAN 2 Receive Clock.

EM2_RXD[3:0]

E7, B7, A7,
A14

Itpd

LAN 2 Receive Data.

EM2_RXDV

Itpd

LAN 2 Receive Data Valid.

EM2_RXER

Itpd

LAN 2 Receive Error

EM2_TX_CLK

L13

Itpd

LAN 2 Transmit Clock.

EM2_TX_EN

J13

Otts4

LAN 2 Transmit Enable.

EM2_TXD[3:0]

L14, L12, K12,
M14

Otts4

LAN 2 Transmit Data.

EM2_TXER

K14

Otts4

LAN 2 Transmit Error.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

2-13

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

Host Parallel Expansion Bus Interface

HAD[15:0]

N7, M9, L8, K9,
J9, N10, P10,
M10, L9, K10,
L10, M11, J10,
L11, N12, P12

I/O

Itpu/Ot4

Data Lines 15-00.
Typically, connect to Flash ROM D[15:0], respectively.

HAD[29:16]

L3, L1, M2, M1,
N2, N1, M3,
N3, P3, M4,
N4, P4, L4, M5

It/Ot4

Address Lines 20-7.
Typically, connect to Flash ROM A[20:10], respectively.

HC[07:01]

L5, M6, K6, N6,
P6, L6, P7

It/Ot4

Address Lines 6-0.
Typically, connect to Flash ROM A[6:0], respectively.

HC08 (HRD#)

M13

It/Ot4

Read Enable. Active low read enable asserted when data is
transferred from the selected device onto the data bus.
Typically, connect through 51

as HRD# to Flash ROM OE# and

through 51

as HRDUA# to UART OE#.

HC09 (HWR#)

M12

It/Ot4

Write Enable. Active low write enable asserted when data is
transferred from the data bus into the selected device.
Typically, connect through 51

as HWR# to Flash ROM WR# and

through 51

as HWRUA# to UART WR#.

HC00 (HCS0#)/
GPIO32

P14 (CX82100
-11/-12/-51/-51)
P13 (CX82100
-41/-42)

It/Ot4

Flash ROM Chip Enable. Active low output enables optional Flash
ROM when asserted.
Connect to Flash ROM CE#.

HC10 (HRDY#)

P14 (CX82100
-41/-42)

Itpd/Ot4

Application Dependent.

HAD31
(HCS4#)/
GPIO37

It/Ot4

Application Dependent.

Serial EEPROM Interface

I2C_DATA
(GPIO15)

I/O

Itpu/Ot4

Serial EEPROM Data. I2C_DATA is a bidirectional data line used
to transfer data into and out of the EEPROM.

Connect to the

EEPROM SDA pin and to +3.3V through 4.7K

I2C_CLOCK
(GPIO16)

Itpu/Ot4

Serial EEPROM Shift Clock. The I2C_CLOCK output is used to
clock all data into and out of the EEPROM. Connect to the
EEPROM SCL pin and to +3.3V through 4.7K

CX82100 Home Network Processor Data Sheet

2-14

Conexant Proprietary and Confidential Information

101306C

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

SDRAM/SRAM Interface

MA[11:00]

B13, C12, A13,
B12, D11, C11,
F8, A11, C10,
D10, B10, A10

Ot4

SDRAM/SRAM Address Lines. Twelve-bit multiplexed row and
column address bus addresses up to 8 MB of data.
Connect to SDRAM/SRAM A[11:0], respectively, through 51

MD[15:00]

J14, H12, H13,
J11, H14, G13,
G12, H9, G14,
G10, F13, G11,
F14, F10, E13,
F11

I/O

Itpu/Ot4

SDRAM/SRAM Data Lines. Sixteen-bit bidirectional data bus.
Connect to SDRAM/SRAM D[15:0], respectively, through 51

MM0

E11

Ot4

SDRAM Input/Output Mask 0/SRAM A12.
For SDRAM interface, this signal is a mask for write access.
Connect to SDRAM I/O Mask Low input through 51

For SRAM interface, this signal is address A12 output, Connect to
SRAM A12 input through 51

MM1

E10

Ot4

SDRAM Input/Output Mask 1/SRAM A13.
For SDRAM interface, this signal is a mask for write access.
Connect to SDRAM I/O Mask High input through 51

For SRAM interface, this signal is address A13 output. Connect to
SRAM A13 input through 51

MB0

Ot4

SDRAM Bank Address Select 0/SRAM A14.
For SDRAM interface, this signal selects the active bank. Connect
to SDRAM/SRAM Bank Address Select 0 input through 51

for 8

MB SDRAM; leave open for 2 MB SDRAM.
For SRAM interface, this signal is address A14 output. Connect to
SRAM A14 input through 51

MB1

Ot4

SDRAM Bank Address Select 1/SRAM A15.
For SDRAM interface, this signal selects the active bank. Connect
to SDRAM/SRAM Bank Address Select 1 input through 51

For SRAM interface, this signal is address A15 output. Connect to
SRAM A15 input through 51

MCS#

C14

Ot4

SDRAM Memory Chip Select/SRAM 2 Chip Enable.
For SDRAM interface, this active low output enables the SDRAM
command decoder. Connect to SDRAM CS# input through 51

For SRAM interface, this active low output enables SRAM 2. If one
SRAM is used, leave open; if two SRAMs are used, connect to
SRAM 2 CE# input through 51

MRAS#

D13

Ot4

SDRAM Row Address Strobe/SRAM 1 Chip Enable.
For SDRAM interface, this active low output starts SDRAM access
with strobe of row address. Connect to SDRAM RAS# input
through 51

For SRAM interface, this active low output enables SRAM 1. If one
SRAM is used, connect to SRAM CE# input; if two SRAMs are
used, connect to SRAM 1 CE# input through 51

MCAS#

C13

Ot4

SDRAM Column Address Strobe/SRAM A16.
For SDRAM interface, this active low output strobes column
address and data bytes. Connect to SDRAM CAS# input through
51

For SRAM interface, this signal is address A16 output. Connect to
SRAM A16 input through 51

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Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)

Pin Signal

Pin No.

I/O

I/O Type

Signal Name/Description

SDRAM/SRAM Interface (Continued)

MWE#

B14

Ot4

SDRAM/SRAM Memory Write Enable. This active low output
enables write access to SDRAM/SRAM. Connect to SDRAM/SRAM
WE# input through 51

MCKE

E12

Ot4

SDRAM Clock Enable/SRAM A17.
For SDRAM interface, this active high output enables the SDRAM
clock. Connect to SDRAM CLKE input through 51

For SRAM interface, this signal is address A17 output. Connect to
SRAM A17 input through 51

MCLK

E14

Ot4

SDRAM Clock.
For SDRAM interface, this signal supplies the clock to the SDRAM.
Connect to SDRAM CLK input through 51

. All SDRAM signals

are sampled on the positive (rising) edge.
For SRAM interface, this pin not used. Leave open.

General Purpose Input/Output (GPIO)

Recommended GPIO usage is listed in Table 2-9.
GPIO31

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO27

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO26

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO24

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO21

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO20

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO19

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO18

I/O

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO17

I/O

Itpu/Ot4

Application Dependent. Reset state = low.

GPIO8

I/O

Itpu/Ot4

Application Dependent. Reset state = low.

GPIO7

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO6

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

GPIO5

Itpu/Ot4

Application Dependent. Reset state = Z(pu).

Test

TST[3:0]

D4, A4, B4, C5

Test Pins. Test configuration pins used only during the
manufacturing/test process.
For normal operation, connect TST[3:0] to ground.

No Connect Pins (Balls)

C1, C2, D2, D3,
F7

No Connect. These pins (solder balls) are not connected to
internal circuitry. Leave open.

Notes:
1. I/O Types: See Table 2-4.
2. Unless otherwise specified, output pins or input pins with internal pulldowns or pullups can be left open if not used.
3. The Reset State notation indicates the state of the pin upon power-on and whether or not it has an internal pullup. Z means

a high impedance state (an input) and pu/pd means the pin has an internal pullup/pulldown.

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2.2

CX82100 HNP Electrical and Environmental Specifications

2.2.1

DC Electrical Characteristics

CX82100 HNP DC electrical characteristics are listed in Table 2-5.

Table 2-5. CX82100 HNP DC Electrical Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions1

Input high voltage

VIH

2.0

VGG + 0.5

VDC

Input low voltage

VIL

-0.5

0.8

VDC

Input leakage current

IIL/IIH

µA

VIN = 0 for Min.
VIN = VIN (MAX) for Max.

Input leakage current (with internal pull-
downs) 2

IIL/IIH

µA

VIN = 0 for Min.
VIN = VIN (MAX) for Max.

Input leakage current (with internal pull-
ups) 2

IIL/IIH

µA

VIN = 0 for Min.
VIN = VIN (MAX) for Max.

Internal pullup/pulldown resistance

Rpu/Rpd

200

Output high voltage

VOH

2.4

VDDO

VDC

IOH = 4 mA

Output low voltage

VOL

0.4

VDC

IOL = 4 mA

Input/output capacitance

CINOUT

Notes:
1. Test Conditions (unless otherwise stated):

VDDcore = +1.8 ± 0.15 VDC
VDDO = +3.3 ± 0.3 VDC;
VIN (MAX) = +3.6V for VGG connected to +3.3V;
VIN (MAX) = +5.25V for VGG connected to +5V.

2. Current flow out of the device is shown as minus.
3. Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied.

Exposure to absolute maximum ratings for extended periods of time may affect device reliability.

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2.2.2

Operating Conditions, Absolute Maximum Ratings, and Power Consumption

CX82100 HNP operating conditions are specified in Table 2-6.

CX82100 HNP absolute maximum ratings are stated in Table 2-7.

CX82100 HNP power consumption is listed in Table 2-8.

Table 2-6. CX82100 HNP Operating Conditions

Parameter

Symbol

Min

Typ

Max

Units

Core circuits supply voltage

VDD

1.65

1.8

1.95

VDC

I/O circuits supply voltage

VDDO

3.0

3.3

3.6

VDC

I/O clamp voltage

VGG*

VDC

Operating ambient temperature

°C

*Connect VGG to the highest signaling level being used to drive input signals, i.e. +3.3 V or +5 V.

Table 2-7. CX82100 HNP Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Units

Core circuits supply voltage

VDD

-0.35

2.0

VDC

I/O circuits supply voltage

VDDO

-0.35

3.7

VDC

Input voltage

-0.35

VGG + 0.35*

VDC

Voltage applied to outputs in high
impedance (Off) state

-0.35

VGG + 0.35*

VDC

Storage temperature

-55

125

°C

* VGG = +3.3 V ± 0.3 V or +5 V ± 0.25 V.

Caution: Handling CMOS Devices

These devices contain circuitry to protect the inputs against damage due to high static
voltages. However, normal precautions should be taken to avoid application of any
voltage higher than maximum rated voltage.

An unterminated input can acquire unpredictable voltages through coupling with stray
capacitance and internal crosstalk. Both power dissipation and device noise immunity
degrades. Therefore, all inputs should be connected to an appropriate supply voltage.

Input signals should never exceed the voltage range from 0.5V or more negative than
GND to 0.5V or more positive than VDD. This prevents forward biasing the input
protection diodes and possibly entering a latch up mode due to high current transients.

Table 2-8. CX82100 HNP Power Consumption

Supply Voltage

Typical

Current (mA)

Maximum

Current (mA)

Typical

Power (mW)

Maximum

Power (mW)

VDD

105

155

205

VDDO

Test conditions:

VDD = +1.8 VDC for typical values;
VDD = +1.95 VDC for maximum values.
VDDO = +3.3 VDC for typical values;
VDDO = +3.6 VDC for maximum values.

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2.3

Optional GPIO and Host Signal Usage

Optional GPIO and host signal usage is listed in Table 2-9.

Recommended GPIO signals are described in Table 2-10.

Table 2-9. CX82100 HNP Recommended GPIO and Host Signal Use

Pin Name

Pin

Default Use

Recommended Use

Signal Label

Reset

State

Notes

FCLKIO/GPIO39

GPIO39

Z(pu)

BCLKIO/GPIO38

GPIO38

Z(pu)

HAD31 (HCS4#)/GPIO37

HAD31 (HCS4#)

HCS4#:

High

HC00 (HCS0#)/GPIO32

P14

HC00 (HCS0#)

HCS0#: Flash ROM CE#

High

2, 5

GPIO31

Z(pu)

GPIO27

Z(pu)

GPIO26

Z(pu)

GPIO25

Z(pu)

GPIO24

Z(pu)

USB_PWR_DET (GPIO22)

USB Power Detect

USB_PWR_DET

2, 6

GPIO21

Z(pu)

GPIO20

LAN 1 Reset

LAN1_RST#

Z(pu)

GPIO19

Z(pu)

GPIO18

Z(pu)

GPIO17

Low

3, 5

I2C_CLOCK (GPIO16)

Serial EEPROM Shift Clock

I2C_CLOCK

Z(pu)

I2C_DATA (GPIO15)

Serial EEPROM Data

I2C_DATA

Z(pu)

BOPT (GPIO14)

Boot Loader Option

BOPT

Z(pu)

GPIO8

Low

3, 5

GPIO7

Ready Indicator

LED_READY

Z(pu)

GPIO6

LAN 2 Reset

LAN2_RST#

Z(pu)

GPIO5

Z(pu)

Notes:
1. Refer to applicable reference design information for exact GPIO use.
2. Recommended system use. See Table 2-2 for signal definition.
3. Recommended application use. See Table 2-4 for signal definition.
4. The Reset State column indicates the state of the pin upon power-on and whether or not it has an internal pullup. Z means a

high impedance state (an input) and pu/pd means the pin has an internal pullup/pulldown.

5. GPIOs that default to chip selects (GPIO32 and GPIO37), as well as GPIO8 and GPIO17, default to output upon power-on.
6. GPIO22 is the only GPIO that does not have an internal pullup/down, so if USB detect is important or used, GPIO22 should

be assigned to it. If GPIO22 is not used, or the firmware does not configure it to an output upon initialization, an external
pullup/down must be implemented on the board.

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3.2

Starting Addresses

The starting addresses for mapping ASB and APB slaves are defined in Table 3-1 and
Table 3-2, respectively.

Table 3-1. Starting Addresses for Mapping ASB Slaves

ASB Address:

BA[31:0]

ASB Slave

Description

0x000XXXXX

External Flash
ROM/Internal RAM

16k x 32 Internal ROM/External Flash ROM
(Boot-Time);
8k x 32 Internal RAM (Run-Time)

0x0018XXXX

Internal RAM/Internal ROM

8k x 32 Internal RAM (Boot-Time);
16k x 32 Internal ROM (Run-Time)

0x002XXXXX

Host Interface

Host Master Mode peripherals interface

0x003XXXXX

ASB-to-APB Bridge/DMAC

To ASB-to-APB Bridge and APB peripherals
dword (4 bytes) access only

0x00400000

0x007FFFFF

External Flash ROM

Host Master Mode interface to 4 MB Flash

0x00800000 -

0x00FFFFFF

External SDRAM

External SDRAM/SRAM interface to 8 MB
SDRAM or up to 1 MB SRAM

0x80000000

ARM940T

ARM940T TIC Access

Table 3-2. Starting Addresses for Mapping APB Slaves

ASB Address:

BA[31:0]

APB Slave

Description

0x0030XXXX

ASB-to-APB Bridge/DMAC

ASB-to-APB Bridge Slave and DMAC

0x0031XXXX

EMAC 1

Ethernet Media Access Control 1

0x0032XXXX

EMAC 2

Ethernet Media Access Control 2

0x0033XXXX

USB Interface

USB Device Controller

0x0034XXXX

Reserved

0x0035XXXX

Interrupts, Timers, GPIO,
Clock (ITGC)

Miscellaneous Peripherals (Interrupts, Timers,
GPIOs, and Clock)

3.2.1

ARM Vector Table

Table 3-3 shows the exception vector addresses required by the ARM940T. The first 32-
byte space of the ASB address space is reserved for this table.

Table 3-3. ARM Exception Vector Addresses

Address

Exception

Mode on Entry

0x00000000

Reset

Supervisor

0x00000004

Undefined Instruction

Undefined

0x00000008

Software Interrupt

Supervisor

0x0000000C

Abort (Prefetch)

Abort

0x00000010

Abort (Data)

Abort

0x00000014

Reserved

0x00000018

IRQ#

0x0000001C

FIQ#

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3.3

Endianness

The internal bus architecture supports only Little-Endian mode addressing (see Figure
3-2). Support for Big-Endian mode may occur in a peripheral that handles its data stream
or in the host interface which may exchange data with a Big-Endian mode external
processor.

Figure 3-2. Little-Endian Mode Addressing

100878-008

31:24

7:0

15:8

23:16

Data Bus

Byte Lane No.

BA[1:0]=3

BA[1:0]=0

BA[1:0]=1

BA[1:0]=2

3.4

Boot Procedure

There are two different scenarios for the boot procedure depending on the state of the
BOPT (GPIO14) pin. Upon power-on or reset, boot code will execute from internal ROM
if the BOPT (GPIO14) pin is high or from external Flash ROM if the BOPT (GPIO14)
pin is low.

When booting from internal ROM, the boot code reads EEPROM information (if an
EEPROM is installed) to set up the USB configuration of the HNP. Once complete, USB
communication between PC and the HNP can occur.

When booting from external Flash ROM, the HNP maps the first MB of external Flash
ROM space to internal ROM space (see memory map in Figure 3-1 for detailed
information). A typical boot procedure begins by copying the flash boot code to internal
RAM. The RUN_MAP bit is set in the Host Control Register (see 5.3.1) which causes the
boot code to begin execution from internal RAM. The boot code then configures the
clocks and the enables the SDRAM. This enables the boot code to begin execution from
internal RAM. The boot code then copies the application firmware residing in flash to
SDRAM. The boot code then jumps to the start of the application firmware in SDRAM.

Figure 3-3 illustrates the boot procedure.

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DMAC Interface Description

The DMA controller (DMAC) is both an ASB master and an APB master. It is integrated
with the ASB-to-APB bridge. Using burst transfers and pipelining the data within the bus
bridge interface optimizes ASB efficiency.

The DMAC always performs qword (8 bytes) data transfers which require data valid on
the entire 64-bit APB data bus. Burst transfer on APB is not supported, however, data can
be transferred on consecutive APB cycles (PCLK cycles) for either read or write.

4.1

DMA Channel Definition

The DMAC supports the data stream channels defined in Table 4-1. Each channel's data-
flow is considered with respect to the system memory's point-of-view. A source channel
has the memory supplying data to the DMAC and on to the transmitter's output port. A
destination channel is one where the memory receives data through the DMAC from the
receiver's input port.

Table 4-1. DMA Channel Definition for DMAC

DMA Channel No.

Channel Type

Channel Description

DMA Mode

Src/Dst

EMAC1-TxD

Lnk Lst restart

Dst

EMAC1-RxD

Circ Bfr restart

Src/Dst

EMAC2-TxD

Lnk Lst restart

Dst

EMAC2-RxD

Circ Bfr restart

Src

Reserved

Dst

Reserved

Src

M2M In

Src

Dst

M2M Out

Dst

Src

USB-TxD_EP3

Lnk Lst

Src

USB-TxD_EP2

Lnk Lst

Src

USB-TxD_EP1

Lnk Lst

Dst

USB-RxD

Circ Bfr restart

Src

USB-TxD_EP0

Lnk Lst

4.2

DMA Requests and Data Transfer

The APB peripherals issue DMA data transfer requests to the DMAC. The knowledge of
how much data will be received or transmitted resides within the peripheral. The physical
interface transfers can be controlled to bit transfer resolution even though the DMAC
only operates at qword resolution. So the size of the packets actually DMAed (which may
differ from that transmitted or received) is under peripheral control. The DMAC just
generates sequential incrementing addresses. Table 4-2 lists all the request commands
supported by DMAC.

DMA action requests are signaled by encoding X{x}R where {x} represents the channel
number. The signal X{x}R should remain idle except when issuing a specific request to
the DMAC. Each event is signaled during a single PCLK clock cycle. It is acceptable to
have an interrupt or abort event directly follow a data transfer request. When an APB data

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peripheral makes a DMA data transfer request, however, it should not make another until
after the current request has been processed (APB read or write). It is left up to the
requestor (not the DMAC) to log any overflow or underflow conditions.

Table 4-2. DMA Requests for APB Peripherals

X{x}R

Request

DMAC Action

3'b000

DMA_IDLE

None

3'b001

DMA_INTR

Data Pkt Done interrupt forwarded to interrupt controller.

3'b010

DMA_SAVE

Save channel's state (cnt and/or ptr).

3'b011

DMA_RELD

Reload or restore channel's state from previous save.

3'b100

DMA_XNXT

Data transfer request @ current pointer. Ptr1+ = 8 (1 qword),
Cnt1-- (Cnt1 represents the number of qwords)

3'b101

DMA_XSAV

Data transfer request @ saved pointer. Ptr2+ = 8 (1 qword),
Cnt2-- (Cnt2 represents the number of qwords)

3'b110

DMA_XNUL

Advance current pointer, skip data transfer. Ptr1+ = 8
(1 qword), Cnt1-- (Cnt1 represents the number of qwords)

3'b111

Reserved

Note that DMA_XNXT and DMA_XSAV are the only DMA commands that cause a
data transfer. Once issued, the channel requestor should not issue another until after their
APB DMA port has been accessed. The APB DMA port qword read or write serves as
the DMAC acknowledge to the channel requestor.

The actions DMA_SAVE, DMA_RELD, and DMA_XNUL should not be issued during
a pending data transfer request since the current pointer and counter are not updated until
the channel is serviced. Usually DMA_SAVE will be issued just after the packet's last
qword transfer acknowledge. Usually DMA_RELD is issued when a channel decides to
abort a packet. DMA_XNUL is typically issued before starting a packet transfer.

The action DMA_XNUL can be issued on consecutive PCLKs if the channel desires to
move up its current pointer by several qwords. This action may not be issued when the
DMAC_{x}_Cnt1 is equal to 1. DMA_XNUL may not be used just before an address
link. Normally, when DMA_XNXT is issued for the last data qword, both the link and
data transfers are scheduled concurrently, with the link transfer actually occurring first.

Two problems arise if DMA_XNUL is allowed to decrement the qword counter quickly.
First, the address is changed before a link transfer can be scheduled into the DMAC
transfer queue with the correct address. Second, there is nothing to prevent the requesting
channel from issuing a DMA_XNXT before the new address link is updated.

4.3

Control Registers

Per each DMA channel {x}, the DMAC can support three basic modes of address
generation using up to two 22-bit dword- (4 bytes) aligned address pointers
(DMAC_{x}_Ptr1, DMAC_{x}_Ptr2) and/or up to three 11-bit qword (8 bytes) counters
(DMAC_{x}_Cnt1, DMAC_{x}_Cnt2, DMAC_{x}_Cnt3). DMAC_{x}_Ptr1 will
always be readable as the current qword pointer. The counters are large enough to allow a
maximum DMA contiguous block transfer of 16 KB (less 1 qword). Each channel {x} is
handled uniquely and specifically for operating mode, priority, and data rate. Recall that
the peripheral is in control of initiating, aborting, and ending the DMA transfer requests.

Pointers are 22-bit programmable and dword-aligned. The pointer registers are bit-
aligned to represent the pointers as 24-bit byte-addresses. Thus the pointer registers
should be written and read as 24-bit byte-addresses. However, the lower two bits are
fixed at 2'b00 forcing the pointers to be dword-aligned. Recall that data transfer
resolution is limited to whole qwords.

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4.4

DMAC Register Memory Map

DMAC registers are identified in Table 4-3.

Table 4-3. DMAC Registers

ASB Address

Type

Default Value

Ref.

DMAC_1_Ptr1

DMAC 1 Current Pointer 1

0x00300000

RW*

0x00000000

4.5.1

DMAC_2_Ptr1

DMAC 2 Current Pointer 1

0x00300004

0x00000000

4.5.1

DMAC_3_Ptr1

DMAC 3 Current Pointer 1

0x00300008

RW*

0x00000000

4.5.1

DMAC_4_Ptr1

DMAC 4 Current Pointer 1

0x0030000C

0x00000000

4.5.1

DMAC_5_Ptr1

DMAC 5 Current Pointer 1

0x00300010

RW*

0x00000000

4.5.1

DMAC_6_Ptr1

DMAC 6 Current Pointer 1

0x00300014

RW*

0x00000000

4.5.1

DMAC_7_Ptr1

DMAC 7 Current Pointer 1

0x00300018

RW*

0x00000000

4.5.1

DMAC_8_Ptr1

DMAC 8 Current Pointer 1

0x0030001C

RW*

0x00000000

4.5.1

DMAC_9_Ptr1

DMAC 9 Current Pointer 1

0x00300020

RW*

0x00000000

4.5.1

DMAC_10_Ptr1

DMAC 10 Current Pointer 1

0x00300024

RW*

0x00000000

4.5.1

DMAC_11_Ptr1

DMAC 11 Current Pointer 1

0x00300028

RW*

0x00000000

4.5.1

*** Reserved ***

0x0030002C

DMAC_1_Ptr2

DMAC 1 Indirect/Return Pointer 2

0x00300030

RW*

0x00000000

4.5.4

DMAC_2_Ptr2

DMAC 2 Indirect/Return Pointer 2

0x00300034

RW*

0x00000000

4.5.4

DMAC_3_Ptr2

DMAC 3 Indirect/Return Pointer 2

0x00300038

RW*

0x00000000

4.5.4

DMAC_4_Ptr2

DMAC 4 Indirect/Return Pointer 2

0x0030003C

RW*

0x00000000

4.5.4

DMAC_5_Ptr2

DMAC 5 Indirect/Return Pointer 2

0x00300040

RW*

0x00000000

4.5.4

*** Reserved ***

0x00300044
0x0030005C

DMAC_1_Cnt1

DMAC 1 Buffer Size Counter 1

0x00300060

RW*

0x00000000

4.5.3

DMAC_2_Cnt1

DMAC 2 Buffer Size Counter 1

0x00300064

RW*

0x00000000

4.5.3

DMAC_3_Cnt1

DMAC 3 Buffer Size Counter 1

0x00300068

RW*

0x00000000

4.5.3

DMAC_4_Cnt1

DMAC 4 Buffer Size Counter 1

0x0030006C

RW*

0x00000000

4.5.3

DMAC_5_Cnt1

DMAC 5 Buffer Size Counter 1

0x00300070

RW*

0x00000000

4.5.3

DMAC_6_Cnt1

DMAC 6 Buffer Size Counter 1

0x00300074

RW*

0x00000000

4.5.3

*** Reserved ***

0x00300078
0x0030007C

DMAC_9_Cnt1

DMAC 9 Buffer Size Counter 1

0x00300080

RW*

0x00000000

4.5.3

DMAC_10_Cnt1

DMAC 10 Buffer Size Counter 1

0x00300084

RW*

0x00000000

4.5.3

DMAC_11_Cnt1

DMAC 11 Buffer Size Counter 1

0x00300088

RW*

0x00000000

4.5.3

*** Reserved ***

0x0030008C
0x00300090

DMAC_2_Cnt2

DMAC 2 Buffer Size Counter 2

0x00300094

0x00000000

4.5.4

*** Reserved ***

0x00300098

DMAC_4_Cnt2

DMAC 4 Buffer Size Counter 2

0x0030009C

0x00000000

4.5.4

*** Reserved ***

0x003000A0
0x003000FC

DMAC_12_Ptr1

DMAC 11 Current Pointer 1

0x00300100

RW*

0x00000000

4.5.1

DMAC_13_Ptr1

DMAC 12 Current Pointer 1

0x00300104

RW*

0x00000000

4.5.1

*** Reserved ***

0x00300108
0x0030010C

DMAC_12_Cnt1

DMAC 11 Buffer Size Counter 1

0x00300110

RW*

0x00000000

4.5.3

DMAC_13_Cnt1

DMAC 12 Buffer Size Counter 1

0x00300114

RW*

0x00000000

4.5.3

*** Reserved ***

0x00300118
0x00300124

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4.5

Control Register Formats

4.5.1

DMAC x Current Pointer 1 (DMAC_{x}_Ptr1)

Bit(s)

Type

Default

Name

Description

31:24

Reserved.

23:2

RW*

22'bx

DMAC_{x}_Ptr1

Current DMA qword Address Pointer.
Points to next qword transfer location within source or destination
buffer. Always dword-aligned.

1:0

Reserved.

4.5.2

DMAC x Indirect/Return Pointer 1 (DMAC_{x}_Ptr2)

Bit(s)

Type

Default

Name

Description

31:24

Reserved.

23:2

RW*

22'bx

DMAC_{x}_Ptr2

Indirect or Return DMA qword Address Pointer.
Points to next pointer which points to next qword transfer location
within source or destination buffer. Always dword-aligned.

1:0

Reserved.

4.5.3

DMAC x Buffer Size Counter 1 (DMAC_{x}_Cnt1)

Bit(s)

Type

Default

Name

Description

31:26

Reserved.

25:24

2'b00

DMAC_{x}_LMode

DMA Linked List Mode.

00 =

ptr/cnt at buffer tail.

01 =

ptr/cnt at Ptr2 (table).

10 =

ptr/cnt at Ptr2 (return ptr).

11 =

Reserved.

23:11

Reserved.

10:0

RW*

11'bx

DMAC_{x}_Cnt1

Initialize to DMA Buffer Size in No. of qwords.
Decrements during DMA data transfers and reloads at end of buffer.
Note that a write to DMAC_{x}_Cnt1 also loads buffer size to
DMAC_{x}_Cnt2.

4.5.4

DMAC x Buffer Size Counter 2 (DMAC_{x}_Cnt2)

Bit(s)

Type

Default

Name

Description

31:11

Reserved.

10:0

RW*

11'bx

DMAC_{x}_Cnt2

Saved DMA Buffer Size in No. of qwords.

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The usage of each register for controlling the operation of the circular buffer is as
follows:

· DMAC_{x}_Ptr2. Used as a base pointer to a dword-aligned circular buffer and is

loaded by the microcontroller (by writing to DMAC_{x}_Ptr1) just once (i.e., this
pointer value is fixed) after the buffer has been allocated. This buffer is typically big
enough to handle multiple data packets (packet size is 64 bytes for USB). The buffer
must be a whole multiple of qwords.

· DMAC_{x}_Ptr1. Used as the current pointer, pointing to the next qword to be

transferred. This pointer is constructed by adding 8*(DMAC_{x}_Cnt2
DMAC_{x}_Cnt1) to the base pointer DMA{x}_Ptr2. The constructed
DMAC_{x}_Ptr1 is the value read when reading its register location (writing has no
effect for the Circular Buffer mode).

· DMAC_{x}_Cnt1. Loaded with an 11-bit value representing the size of the entire

circular buffer. The same value is copied to DMAC_{x}_Cnt2 during write to
DMAC_{x}_Cnt1. This counter register is decremented by one as a qword transfer
is processed. When DMA{x}_Cnt1 = 0, it is reloaded with DMAC_{x}_Cnt2.

· DMAC_{x}_Cnt2. Loaded with an 11-bit value representing the size of the entire

circular buffer. This value is not changed during the course of data transfers.

Indirect Circular Pointer Table

The indirect circular pointer table is explained with an example of how the EMAC RxD
channels work. The EMAC-RxD channel (channel 2 or 4) requires its data to be stored in
memory buffers where the location of each buffer is chosen by the firmware on a pointer
per packet basis. Each received data packet is stored in a contiguous memory segment of
fixed size. This size must be large enough to handle the largest expected packet (plus
overhead), usually less than 1536 bytes (192 qwords). The data is normally going to
remain stationary until transmitted or consumed. The circular data buffer method is not
appropriate for this channel because it would require the data to be consumed in the order
received otherwise the data would have to be copied to other buffers which consumes a
lot of bus bandwidth.

The DMA_{x}_Ptr2, where {x} = 2 or 4, is used to point to the location of the table
which contains the list of pointers to be used for the received data destination buffers.
This table holds the following 4-dword structures called cluster descriptors:

Table 4-4. Cluster Descriptor Table

Cluster Descriptor Table (CDT)

DMA_{x}_Ptr2, where {x} = 2 or 4

CD No.

qword

dword

Cluster Pointer 1

Reserved
EMAC-RxD Status [31:0] for packet 1

EMAC-RxD Status [63:32] for packet 1
Cluster Pointer N

2N-1

Reserved
EMAC-RxD Status [31:0] for packet N

EMAC-RxD Status [63:32] for packet N

The cluster descriptors include status that is written back from the EMAC for each
received packet. When DMA_{x}_Ptr2 is written, a copy is saved as the base pointer to
the head of the pointer table (CDT). The DMA_{x}_Ptr2 can be read anytime to indicate
where the DMAC is currently at in the CDT. The CDT is a circular buffer. The size in

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qwords is determined by DMA_{x}_Cnt2. If there are N cluster descriptors then the
value 2N should be written to DMA_{x}_Cnt2.

The DMAC prefetches the cluster pointers to a two-pointer queue using a source DMA
channel. This queue is initialized (filled) automatically as soon as the firmware writes to
DMA_{x}_Cnt2 (so CDT must be valid and DMA_{x}_Ptr2 initialized). The DMAC has
a two-pointer queue in order to reduce the latency seen by the EMAC-RxD channel when
switching from one cluster to another. The DMAC does not want to add the cluster
pointer fetch latency to the data transfer latency. The current pointer in the queue is
DMA_{x}_Ptr1 and points to the location in the cluster buffer where the received data is
to be stored. This pointer can be read anytime.

The DMA_{x}_Cnt1 value is used to limit the number of qwords the EMAC-RxD can
write to the cluster buffer. Writing a value X to this register will cause all qwords DMA
transferred past X to be stored in the same cluster location (overwritten, only last qword
visible). Reading this register will return a value that indicates the number of qwords
transferred which could be even larger than the size written to DMA_{x}_Cnt1. This
register limits how far the DMA_{x}_Ptr1 may advance. The DMA_{x}_Cnt1 value
increments by 1 for each DMA_XNXT as well as DMA_XNUL.

The EMAC-RxD DMA channel uses a state machine to control the interactions of the
firmware, EMAC-RxD DMA requests, and the DMAC. This state machine is initialized
when DMA_{x}_Cnt2 is written. This event triggers the prefetch of two cluster pointers
from the CDT. The DMA_{x}_Ptr2 will be pointing to the first EMAC-RxD status
qword location after it fills its DMA_{X}_Ptr1 queue. When the EMAC-RxD channel
issues DMA_XSAV, the packet status is read and transferred to the current
DMA_{X}_Ptr2 location. The receiver channel then issues DMA_INTR which causes
the packet interrupt. It also triggers this state machine to transfer the prefetched cluster
pointer to DMA_{X}_Ptr1 and then prefetch the next cluster pointer.

At the beginning of each packet the EMAC-RxD channel issues a DMA_SAVE to save a
copy of the DMA_{X}_Ptr1 cluster head pointer. In case of a bad packet (too short, bad
CRC, etc.) the EMAC-RxD channel will abort the packet and issue a DMA_RELD. This
event will cause the copy of the cluster head pointer to be reloaded into DMA_{X}_Ptr1
and the DMA_{X}_Cnt1 to be re-initialized to zero.

The clusters (received packets) consist of received data qwords transferred via
DMA_XNXT surrounded by reserved qwords at the head and tail of the buffers.

Table 4-5. Received Data Packet

qword No.

Cluster qword

DMA_{x}_Ptr1, {x} = 2 or 4

Reserved < DMA_XNUL

EMAC-RxD < DMA_XNXT

P-1

EMAC-RxD < DMA_XNXT

Reserved (0) < DMA_XNXT

...

Maximum length of packet data

X+1

Overflow location for too long packet

The 1

reserved qword is present because the EMAC-RxD channel issues a

DMA_XNUL at the beginning of every packet. The last reserved qword results from the
channel issuing a DMA_XNXT to transfer a zero qword. If DMA_{X}_Cnt1 is set to X,
then all qwords received after that limit for a given packet will be transferred to location
DMA_{X}_Ptr1 + 8(X+1). The DMA_XNUL does increment DMA_{X}_Cnt1. Most
packets will end much shorter than the programmed limit. In the case of a too long
received packet, the EMAC will end up aborting the packet which causes the next packet

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to be stored at the same cluster location. The limiter, DMA_{X}_Cnt1, is used to prevent
the EMAC-RxD channel from overwriting the allocated cluster buffer size.

The protocol for this DMA channel is:

1. ARM initializes the CDT.

2. ARM initializes DMA_{X}_Ptr2 with the base pointer to CDT (a copy saved within

DMAC).

3. ARM initializes DMA_{X}_Cnt1 to limit number of qwords written to cluster.

4. ARM initializes DMA_{X}_Cnt2 for CDT circular size in qwords.

5. DMAC prefetches first cluster pointer from DMA_{X}_Ptr2+ = 8 (post-increments

by 8).

6. DMAC moves prefetched cluster pointer into DMA_{X}_Ptr1 and prefetches second

cluster pointer from DMA_{X}_Ptr2+8 (no post-increment).

7. EMAC-RxD issues DMA_SAVE, DMAC saves cluster head ptr.

8. EMAC-RxD issues DMA_XNUL, DMA_{X}_Ptr1+ = 8, DMA_{X}_Cnt1++.

9. EMAC-RxD issues DMA_XNXT, DMAC saves data to DMA_{X}_Ptr1+ = 8,

DMA_{X}_Cnt1++.

10. Continue with step 8 until entire packet data is received.

11. EMAC-RxD issues DMA_XSAV, DMAC saves status to DMA_{X}_Ptr2+ = 16.

12. EMAC-RxD issues DMA_XNXT, DMAC saves 0 to DMA_{X}_Ptr1+ = 8,

DMA_{X}_Cnt1++.

13. EMAC-RxD issues DMA_INTR, DMAC sets DMA interrupt for RxD channel.

14. DMAC moves prefetched cluster pointer into DMA_{X}_Ptr1 and prefetches next

cluster pointer from DMA_{X}_Ptr2+8 (no post-increment).

The ARM may read DMA_{X}_Ptr2 at anytime to know where the DMAC is currently
processing the table (recall that the DMAC is prefetching cluster pointers). The ARM can
also determine that a EMAC-RxD status qword location has been updated by looking at
bit 3 which is always written with a 1'b1, if it initializes the status qwords with zero and
as it consumes clusters (and ptrs).

Since the CDT operates in circular mode, all ptr2 prefetches and post-increments operate
modulo 8*DMA_Cnt2.

4.6.3

Linked List Mode

There are two linked list modes supported in the current design: 1) embedded tail linked
list descriptor mode and 2) indirect/table linked list descriptor mode. The first mode is
supported for all transmit channels except channel 7 (memory-to-memory DMAs). The
second mode is supported only for USB transmit channels, i.e., channels 9, 10, 11, and
13. The linked list mode can be programmed through the "DMAC_{x}_LMode" field in
the DMAC_{x}_Cnt1 registers.

Embedded Tail Linked List Descriptor Mode

For the Embedded Tail Linked List Descriptor mode, the buffer link descriptor (ptr/cnt) is
embedded in the buffer at its tail end. Figure 4-2 shows an example for this linked list
mode. This tail linked list is a generic example of how the transmitted packets are set up.
The Ctl_Hdr is specific to the type of DMA being performed, e.g., EMAC, and should be
configured accordingly.

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The usage of each register for controlling the operation of the Embedded Tail Linked List
Descriptor mode is described below.
· DMAC_{x}_Ptr1: Loaded with an initial pointer to a dword-aligned source buffer.

A copy of the pointer is automatically saved in DMAC_{x}_Ptr2 whenever
DMAC_{x}_Ptr1 is loaded with a new pointer. As each DMA request is processed,
DMAC_{x}_Ptr1 is incremented by one qword.

· DMAC_{x}_Cnt1: Loaded with the number of qwords to be delivered to the

channel. This value includes the Ctl_Hdr, but not the link fields at the tail. A copy of
the counter value is automatically saved in DMAC_{x}_Cnt2 whenever
DMAC_{x}_Cnt1 is loaded with a new value. As each DMA request is processed,
DMAC_{x}_Cnt1 is decremented by one qword.

· DMAC_{x}_Ptr2: Saves the beginning address of the current buffer in the list. This

pointer is required for EMAC re-transmission support.

· DMAC_{x}_Cnt2: Saves the number of qwords to be delivered in the buffer pointed

by DMAC_{x}_Ptr2. This counter is required for EMAC re-transmission support.

When DMAC_{x}_Cnt1 = = 1, the DMAC will actually do two qword ASB transfers,
forwarding a qword to the APB, and keeping a qword to reload its current pointer
(DMAC_{x}_Ptr1 < = 1

dword of buffer's appended qword) and counter

(DMAC_{x}_Cnt1 < = 2

appended dword) for processing the next buffer. Thus the link

to the next source buffer is found at the tail of the current source buffer.

When using the embedded tail linked list descriptor for the EMAC transmission channels
(channels 1 and 3), the channels require "re-transmission" support. The re-transmission
support is outlined below for channel {x}.

1. When DMAC_{x}_Ptr1 is loaded, automatically save a copy to DMAC_{x}_Ptr2.

2. When DMAC_{x}_Cnt1 is loaded, automatically save a copy to DMAC_{x}_Cnt2.

3. At anytime the channel may decide to abort the packet and restart by signaling:

X{x}R < = DMA_RELD.

This causes the DMAC to re-initialize DMAC_{x}_Ptr1 and DMAC_{x}_Cnt1 to
DMAC_{x}_Ptr2 and DMAC_{x}_Cnt2, respectively. It is acceptable for a re-
transmission to begin after the channel has linked to other successive buffers. The
channel always re-starts at the beginning of the chain.

The EMAC transmission channels also require support for "going back to a saved
pointer" and saving a qword containing status of the transmitted packet. A qword can be
saved at the saved pointer (usually the start-of-pkt ptr, saved for restart) by signaling:

X{x}R < = DMA_XSAV.

This event does not affect the state of the current qword pointer. This data transfer
request is asking the DMAC to perform a data transfer in an opposite direction for a
normal transmitter source channel. However, this is very easy for the DMAC to handle.
To leave room for status to flow back to the data structure, the transmitter source channel
must use DMA_SAVE to save a pointer to the status section. It probably does not need to
open a hole with DMA_XNUL since it can overwrite data at the head or tail of the data
structure.

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Indirect/Table Linked List Descriptor Mode

The example shown in Figure 4-3 illustrates the use of the indirect/table linked descriptor
mode for four transmit buffers. The DMAC operation is virtually identical to that of the
embedded tail linked list descriptor mode except that the next DMA Ptr1 and Cnt1 will
be fetched from a pre-programmed pointer/counter table. The table itself is operated in a
circular fashion, meaning that the DMAC will automatically fetch the next
pointer/counter pair from the top of the table as soon as the last pointer/counter pair has
been used. The base address of the table is pre-stored in the DMAC_{x}_Ptr2 register.
The size of the table (in number of qwords) is pre-stored in the DMAC_{x}_Cnt2
register. Note that DMAC_{x}_Ptr1 and DMAC_{x}_Cnt1 registers should be initialized
to contain the Ptr1/Cnt1 values associated with the first buffer. The same Ptr1/Cnt1
values should also be stored at the bottom of the table in order to make the four buffers
work together like a big circular buffer.

Figure 4-3. Indirect/Table Linked List Descriptor Example 1

101545_012

DMAC_{x}_Cnt1 = 0x01000009

4 Bytes

0 x 00 1 4 0 0 F 8

0 x 0 0 1 4 0 0 F C

0 x 0 0 1 4 0 1 0 0

64-byte

data packet #1

0 x 0 0 1 4 0 1 3 C

0 x 0 0 1 4 0 1 4 0

descriptor/status

0 x 00 1 4 0 2 F 8

0 x 0 0 1 4 0 2 F C

0 x 0 0 1 4 0 3 0 0

64-byte

data packet #2

0 x 0 0 1 4 0 3 3 C

0 x 0 0 1 4 0 3 4 0

descriptor/status

0 x 00 1 4 0 4 F 8

0 x 0 0 1 4 0 4 F C

0 x 0 0 1 4 0 5 0 0

64-byte

data packet #3

0 x 0 0 1 4 0 5 3 C

0 x 0 0 1 4 0 5 4 0

descriptor/status

0 x 00 1 4 0 6 F 8

0 x 0 0 1 4 0 6 F C

0 x 0 0 1 4 0 7 0 0

64-byte

data packet #4

0 x 0 0 1 4 0 7 3 C

0 x 0 0 1 4 0 7 4 0

descriptor/status

DMAC_{x}_Ptr1= 0x001400F8

Address

0x001402F8
0x01000009
0x001404F8
0x01000009
0x001406F8

0x01000009
0x001400F8
0x01000009

0x 0 0 1 4 0 8 0 0

0 x 0 0 1 4 0 8 0 4

0x 0 0 1 4 0 8 0 8

0 x 0 0 1 4 0 8 0 C

0x 0 0 1 4 0 8 1 0

0 x 0 0 1 4 0 8 1 4

0x 0 0 1 4 0 8 1 8

0 x 0 0 1 4 0 8 1 C

Address

DMAC_{x}_Cnt2 = 0x00000004

DMAC_{x}_Ptr2= 0x00140800

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The use of the tail and the indirect/table linked list descriptor modes can be mixed to
form a more complicated list. The dynamic switch from one mode to the other is
controlled by the pre-programmed value in DMAC_{x}_LMode.

Figure 4-4 shows an example for mixing the two modes with five buffers.

Figure 4-4. Indirect/Table Linked List Descriptor Example 2

101545_013

DMAC_{x}_Cnt1 = 0x01000009

4 Bytes

0 x 0 0 1 4 0 0 F 8

0 x 0 0 1 4 0 0 F C

0 x 0 0 1 4 0 1 0 0

64-byte

data packet #1

0 x 0 0 1 4 0 1 3 C

0 x 0 0 1 4 0 1 4 0

descriptor/status

0 x 0 0 1 4 0 2 F 8

0 x 0 0 1 4 0 2 F C

0 x 0 0 1 4 0 3 0 0

64-byte

data packet #2

0 x 0 0 1 4 0 3 3 C

0 x 0 0 1 4 0 3 4 0

descriptor/status

0 x 0 0 1 4 0 4 F 8

0 x 0 0 1 4 0 4 F C

0 x 0 0 1 4 0 5 0 0

64-byte

data packet #3

0 x 0 0 1 4 0 5 3 C

descriptor/status

DMAC_{x}_Ptr1= 0x001400F8

Address

0x001402F8

0x01000009

0x001404F8
0x00000009

0x001408F8

0x01000009
0x001400F8

0x01000009

0 x 0 0 1 4 0 8 0 0

0 x 0 0 1 4 0 8 0 4

0 x 0 0 1 4 0 8 0 8

0 x 0 0 1 4 0 8 0 C

0 x 0 0 1 4 0 8 1 0

0 x 0 0 1 4 0 8 1 4

0 x 0 0 1 4 0 8 1 8

0 x 0 0 1 4 0 8 1 C

Address

DMAC_{x}_Cnt2 = 0x00000004

DMAC_{x}_Ptr2= 0x00140800

0 x 0 0 1 4 0 5 4 0

0x001406F8

0x01000009

0 x 0 0 1 4 0 5 4 4

0 x 0 0 1 4 0 6 F 8

0 x 0 0 1 4 0 6 F C

0 x 0 0 1 4 0 7 0 0

64-byte

data packet #4

0 x 0 0 1 4 0 7 3 C

0 x 0 0 1 4 0 8 4 0

descriptor/status

0 x 0 0 1 4 0 8 F 8

0 x 0 0 1 4 0 8 F C

0 x 0 0 1 4 0 9 0 0

64-byte

data packet #4

0 x 0 0 1 4 0 9 3 C

0 x 0 0 1 4 0 9 4 0

descriptor/

status

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Table 5-1. Host Master Mode Signals

Pin Signal

Host Master

Mode Signal

Pin No.

Signal

Direction

Signal Name

HAD[15:0]

HD[15:0]

N7, M9, L8, K9, J9, N10,
P10, M10, L9, K10, L10,
M11, J10, L11, N12, P12

I/O

Host Bus Data [15:0]

HAD[29:16]

HA[20:7]

L3, L1, M2, M1, N2, N1, M3,
N3, P3, M4, N4, P4, L4, M5

Host Bus Address [20:7]

HC[07:01]

HA[6:0]

L5, M6, K6, N6, P6, L6, P7

Host Bus Address [6:0]

HC08 (HRD#)

HRD#

M13

Host Bus Read Enable

HC09 (HWR#)

HWR#

M12

Host Bus Write Enable

HC10 (HRDY#)

HRDY#

P14 (CX82100-41/-42)

Handshake for slow peripherals

HC00 (HCS0#)/GPIO32*

HCS0#

P14 (CX82100-11/-51/-52)
P13 (CX82100-41/-42)

Host Chip Select 0 (Flash ROM)

HAD31 (HCS4#)/GPIO31*

HCS4#

Host Chip Select 4 (Spare)

Notes:
* = These pins default to host functions; they can be reconfigured to GPIO pins.

The HNP Host Master Mode supports only the little-endian mode data byte orientation.
As depicted in Figure 5-2, the 32-bit little-endian ASB data bus BD[31:0] is mapped
to/from the 16-bit external host data bus HD[15:0] according to the even/odd half-word
(16 bits) data address alignment indicated by the address bit HA1.

Figure 5-2. Little-Endian Mode Data Bus Mapping

101545_15

7:0

15:8

31:24

7:0

15:8

23:16

BD[31:0] to/from ASB

even half-word address: HA1 = 0

7:0

15:8

odd half-word address: HA1 = 1

31:24

7:0

15:8

23:16

BD[31:0] to/from ASB

The ASB side may address the host as a slave in 16-bit or 32-bit mode. The 32-bit mode
accesses are converted to two external 16-bit accesses. The host interface is allocated 5
MB total address space. This address space is allocated to the six chip selects HCS[5:0]#
as shown in Figure 5-1 and Table 5-2.

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Table 5-2. Chip Select Address Ranges

HCS Signal

Typical Slave Device

ASB Address Range

Size

HCS0# (HC00)

Flash ROM

0x004000000x007FFFFF

4 MB

HCS4# (HAD31)

Application dependent

0x002C00000x002CFFFF

64 KB

5.1.2

Flash Memory Interface

The master mode host interface addresses up to 32 Mbit (2 M x 16) of Flash ROM using
HA[21:1]. HCS0# is designed specifically to select Flash ROM. Flash ROM can be
optionally used for the HNP executable memory instead of internal ROM. Typically, a 32
Mbit (2 M x 16) Flash ROM such as an Intel TE28F320C3BA90 or equivalent, or a 16
Mbit (1 M x 16) Flash ROM such as an Intel TE28F160C3BA90 or equivalent, is used.
The HNP supports only 16-bit Flash memories, therefore, all writes to a 16-bit Flash must
be word transfers.

Refer to Section 3.4 for a description of booting from Flash ROM.

5.1.3

Interfacing to Other Slave Devices

The peripheral interface is completely programmable via the Host Control Registers.
These registers allow programming of parameters such as peripheral bus width (8-bit or
16-bit), timing for both read and write operations, and control signal polarity.

During a transfer with an 8-bit peripheral, bit 0 of the address, which is omitted when
interfacing to a 16-bit peripheral, is issued on HD15. (This pin is available in 8-bit mode
because the data bus is using only bits HD[7:0].)

During a transfer with a 16-bit peripheral, there are two byte-write enables (one for the
lower 8 bits of the transfer and another for the upper 8 bits), which allow for individual
byte writes to 16-bit peripherals which support such transfers. The high-byte write enable
is assigned to pin HAD29 and the low-byte write enable is assigned to pin HC09. When
writing data to a 16-bit device which does not support multiple byte write enables, the
host must ensure that writes to the device are initiated internally as either word or dword
transfers.

5.1.4

Host Master Mode DMA Engine

Both asynchronous and isochronous modes of operation are available and are selected by
the MSb (bit 9) of the HDMA_MODE_SEL field in the HST_CTRL register.

Asynchronous DMA Transfer Mode

In Asynchronous DMA Transfer Mode, data transfers complete as fast as the source and
destination bus environments allow.

Isochronous DMA Transfer Mode

In Isochronous DMA Transfer Mode, the data is transferred to or from the external
peripheral at a specified rate.

The user supplies the isochronous transfer rate using an internal timer, as selected by the
HDMA_MODE_SEL field in the HST_CTRL register. This rate can be programmed by
the HDMA_ISOC_TIMER field in the HDMA_TIMERS register.

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If internal DMA timer is selected, a value must be written to HDMA_ISOC_TIMER.
This value is, in terms of BCLK periods, the time between DMA accesses to the external
peripheral. For example, when DMAing data from a peripheral to an internal destination
this register value determines the rate data is read from the peripheral.

The transfer rate is also a function of the peripheral's data bus width. For example, if
HDMA_ISOC_TIMER is set to 200 and the peripheral is set up as an 8-bit wide device,
then 200 BCLK periods will elapse between each byte transaction with the peripheral. If
the same value is programmed, in the case of a 16-bit peripheral, the same 200 BCLK
periods will elapse between each word transaction with the peripheral. Thus, the data rate
in the case of the 16-bit peripheral is twice that of the 8-bit peripheral, even though the
HDMA_ISOC_TIMER is set to the same value in both cases.

General DMA Information

A Host-DMA transfer is configured from the ASB side via the
HDMA_SOURCE_ADDR, HDMA_DEST_ADDR, and HDMA_BCNT registers. The
Host-DMA transfer is started as soon as the HDMA_BCNT register is written to with a
nonzero value. For this reason, the HDMA_BCNT register should only be written to once
the HDMA_SOURCE_ADDR and HDMA_DEST_ADDR registers contain the
appropriate values.

DMA_SRC_ADDR_INC_DISABLE is a 1-bit field in the HST_CTRL register. When
enabled, the DMA transfer always occurs from the 24-bit address programmed into the
HDMA_SOURCE_ADDR. This is needed when a DMA transfer originates from a
register that takes its data sequentially from a FIFO.

DMA_DST_ADDR_INC_DISABLE is a 1-bit field in the HST_CTRL register. Its
purpose is similar to that of DMA_SRC_ADDR_INC_DISABLE except that it transfers
data to a static address location set in HDMA_DEST_ADDR.

HDMA_MODE_SEL is a 2-bit field in the HST_CTRL register with the MSb being the
enable for isochronous mode, and the LSb determining the variation of isochronous
mode.

The HDMA_SOURCE_ADDR register is a 24-bit register that should be written with the
address of the first byte of data to be transferred via the Host-DMA.

The HDMA_DEST_ADDR register is a 24-bit register that should be written with the
byte address of the destination for the Host-DMA data.

The HDMA_BCNT register is a 22-bit register that should be written to with the number
of bytes to be transferred after writing to the HDMA_SOURCE_ADDR and
HDMA_DEST_ADDR. Once the number of bytes has been written into the register, the
host DMA transfer begins.

The HDMA_ISOC_TIMER is an 8-bit field in the HDMA_TIMERS register that is used
when HDMA_MODE_SEL is set to 2'b10. This register is programmed with a value, in
terms of BCLK periods, equal to the length of time between consecutive external DMA
accesses.

The completion of a Host-DMA transfer is signaled by the setting of the INT_HOST
interrupt (bit 6 of INT_Stat register). This bit can be cleared by writing a 1 to the bit.
Subsequent Host-DMA transfers must not be initiated until the previous Host-DMA
transfer has been completed.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

5-9

HRDY# Description (CX82100-41/-42)

HRDY# is used to extend a Host Interface operation. The use of HRDY# can be enabled
or disabled by setting or clearing the corresponding HRDY# Handshake Enable bit in the
MSTR_HANDSHAKE register (0x002D0024).

When HRDY# is enabled, the polarity of HRDY# can be programmed by setting or
clearing bit 0 of the MSTR_HANDSHAKE register.
· With HRDY# Polarity low (default polarity, bit 0 of 0x002D0024 = 0), HRDY# low

indicates the target on the Host Bus is ready/waiting and HRDY# high indicates the
target is busy. In this case, chip selects HCS0#-HCS5# will assert when HRDY# is
low and will not assert when HRDY# is high.

· With HRDY# Polarity high (bit 0 of 0x002D0024 = 1), HRDY# high indicates the

target on the Host Bus is ready/waiting and HRDY# low indicates the target is busy.
In this case, chip selects HCS0#-HCS5# will assert when HRDY# is high and will
not assert when HRDY# is low.

When HRDY# is enabled, the pulse widths of HRD# and HWR# are controlled by either
the HRDY# signal or the timing specified by the Host Read/Write Wait State Control
Register, whichever has longer cycle time. HRD# and HWR# will never have a smaller
width than the programmed values thus minimum Host Interface cycle time is
guaranteed.

When HRDY# is disabled, the state of HRDY# is ignored and the timing of the host
interface control and data signals are controlled by the timing configuration registers:
HST_RWST, HST_WWST, HST_READ_CNTL1, HST_READ_CNTL2,
HST_WRITE_CNTL1, and HST_WRITE_CNTRL2.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

101306C

5.2

Host Master Mode Register Memory Map

Host Master Mode registers are identified in Table 5-7.

Table 5-7. Host Master Mode Registers

Register Label

Register Name

ASB Address

Type

Default Value

Ref.

HST_CTRL

Host Control Register

0x002D0000

0x00000008

5.3.1

HST_RWST

Host Master Mode Read-Wait-State Control
Register

0x002D0004

0x00739CE7

5.3.2

HST_WWST

Host Master Mode Write-Wait-State Control
Register

0x002D0008

0x00739CE7

5.3.3

HST_XFER_CNTL

Host Master Mode Transfer Control Register

0x002D000C

0x00000000

5.3.4

HST_READ_CNTL1

Host Master Mode Read Control Register 1

0x002D0010

0x00000000

5.3.5

HST_READ_CNTL2

Host Master Mode Read Control Register 2

0x002D0014

0x00000000

5.3.6

HST_WRITE_CNTL1

Host Master Mode Write Control Register 1

0x002D0018

0x00000000

5.3.7

HST_WRITE_CNTL2

Host Master Mode Write Control Register 2

0x002D001C

0x00000000

5.3.8

MSTR_INTF_WIDTH

Host Master Mode Peripheral Size

0x002D0020

0x00000000

5.3.9

MSTR_HANDSHAKE

Host Master Mode Peripheral Handshake

0x002D0024

0x00000000

5.3.10

HDMA_SRC_ADDR

Host Master Mode DMA Source Address

0x002D0028

0x00000000

5.3.11

HDMA_DST_ADDR

Host Master Mode DMA Destination Address

0x002D002C

0x00000000

5.3.12

HDMA_BCNT

Host Master Mode DMA Byte Count

0x002D0030

0x00000000

5.3.13

HDMA_TIMERS

Host Master Mode DMA Timers

0x002D0034

0x00000000

5.3.14

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

5-13

5.3

Host Master Mode Registers

5.3.1

Host Control Register (HST_CTRL: 0x002D0000)

Bit(s)

Type

Default

Name

Description

31:12

Reserved.

R/W

1'b0

DMA_SRC_ADDR_INC_DISABLE

Disable DMA Source Address Increment.

0 = Enable DMA Source Address Increment.
1 = Disable DMA Source Address Increment.

R/W

1'b0

DMA_DST_ADDR_INC_DISABLE

Disable DMA Destination Address Increment.

0 = Enable DMA Destination Address Increment.
1 = Disable DMA Destination Address Increment.

9:8

2'b00

HDMA_MODE_SEL

Host Master Mode DMA Transfer Mode Select.

00 =

Asynchronous DMA Mode.

01 =

Reserved.

10 =

Isochronous DMA Mode using internal timer.

11 =

Reserved.

1'b0

EN_BLOCK_ARM

Enable the arbiter to lock 940 ADR/SEQ/ and Bursts.

0 = Disable arbiter to lock 940 ADR/SEQ/ and Bursts.
1 = Enable arbiter to lock 940 ADR/SEQ/ and Bursts.

Reserved.

1'b0

RUN_MAP

Run-Time Memory Map.

0 = Flash ROM @ starting address 0x00000000,

internal RAM @ starting address 0x00180000.

1 = Internal RAM @ starting address 0x00000000,

Flash ROM @ starting address 0x00180000.

3:2

2'b10

XDM_SZ

External Dynamic Memory Size.

00 =

2 MB.

01 =

4 MB.

10 =

8 MB.

11 =

Reserved.

1:0

2'b00

HST_HIRQ

HIRQ0# Output State for External Host.

0x =

Off.

10 =

Asserted low.

11 =

De-asserted and pulled high.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

101306C

5.3.2

Host Master Mode Read-Wait-State Control Register (HST_RWST: 0x002D0004)

Bit(s)

Type

Default

Name

Description

31:25

Reserved.

24:20

5'b00111

HST_RWS4

HCS4 Wait State Control for Master Mode Read Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.

19:5

Reserved.

4:0

5'b00111

HST_RWS0

HCS0 Wait State Control for Master Mode Read Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.

5.3.3

Host Master Mode Write-Wait-State Control Register) (HST_WWST: 0x002D0008)

Bit(s)

Type

Default

Name

Description

31:25

Reserved.

24:20

5'b00111

HST_WWS4

HCS4 Wait State Control for Master Mode Write Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.

19:5

Reserved.

4:0

5'b00111

HST_WWS0

HCS0 Wait State Control for Master Mode Write Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.

5.3.4

Host Master Mode Transfer Control Register (HST_XFER_CNTL: 0x002D000C)

Bit(s)

Type

Default

Name

Description

31:8

Reserved.

1'b0

Hcs4_ds_polarity

HCS4 External Data Strobe Polarity.

0 = Negative data strobe polarity.
1 = Positive data strobe polarity.

6:4

Reserved.

1'b0

Hcs4_xfer_mode

HCS4 External Transfer Mode.

0 = WE# and RE# transfer mode.
1 = R/W# and DS# transfer mode.

2:0

Reserved.

5.3.5

Host Master Mode Read Control Register 1 (HST_READ_CNTL1: 0x002D0010)

Bit(s)

Type

Default

Name

Description

31:28

4'b0

HRcs4_Tcss

HCS4 Chip Select Setup Time Relative to RE# or R/W#.
Length = count value * 1 BCLK period.

27:16

Reserved.

15:12

4'b0

HRcs4_Tcsh

HCS4 Chip Select Hold Time Relative to RE# or R/W#.
Length = count value * 1 BCLK period.

11:0

Reserved.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

5-15

5.3.6

Host Master Mode Read Control Register 2 (HST_READ_CNTL2: 0x002D0014)

Bit(s)

Type

Default

Name

Description

31:28

4'b0

HRcs4_Tas

HCS4 Address Setup Time to Active Read.
Length = count value * 1 BCLK period + 1 BCLK period.

27:16

Reserved.

15:12

4'b0

HRcs4_Tah

HCS4 and HCS5 Address Hold Time Following Active Read.
Length

count value * 1 BCLK period + 4 BCLK periods.

11:0

Reserved.

5.3.7

Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018)

Bit(s)

Type

Default

Name

Description

31:28

4'b0

HWcs4_Tcss

HCS4 Chip Select Setup Time Relative to WE# or R/W#.
Length = count value * 1 BCLK period.

27:16

Reserved.

15:12

4'b0

HWcs4_Tcsh

HCS4 Chip Select Hold Time Relative to WE# or R/W#.
Length = count value * 1 BCLK period.

11:0

Reserved.

5.3.8

Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C)

Bit(s)

Type

Default

Name

Description

31:28

4'b0

HRcs4_Tas

HCS4 Address Setup Time to Active Write.
Length = count value * 1 BCLK period + 1 BCLK period.

27:16

Reserved.

15:12

4'b0

HRcs4_Tadh

HCS4 Address and Data Hold Time Following Active Write.
For data, Length = count value * 1 BCLK period + 1 BCLK period.
For address, Length

count value * 1 BCLK period + 5 BCLK periods.

11:0

Reserved.

5.3.9

Host Master Mode Peripheral Size (MSTR_INTF_WIDTH: 0x002D0020)

Bit(s)

Type

Default

Name

Description

31:5

Reserved.

1'b0

Mstr_intf_width4

HCS4 Data Length.

0 = 16-bit data length.
1 = 8-bit data length.

3:0

Reserved.

CX82100 Home Network Processor Data Sheet

5-16

Conexant Proprietary and Confidential Information

101306C

5.3.10

Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024)
(CX82100-41/-42)

Bit(s)

Type

Default

Name

Description

31:5

Reserved.

1'b0

Mstr_handshake4

HCS4 HRDY# Handshake Enable.

0 = Disable HRDY# handshake.
1 = Enable HRDY# handshake.

3:1

Reserved.

1'b0

Mstr_handshake0

HRDY# Polarity.

0 = Active low
1 = Active high

5.3.11

Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)

Bit(s)

Type

Default

Name

Description

31:24

Reserved.

23:0

24'b0

HDma_source_addr

Least significant 24 bits of the address of the first byte of DMA source
data.

5.3.12

Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C)

Bit(s)

Type

Default

Name

Description

31:24

Reserved.

23:0

24'b0

HDma_dest_addr

Least significant 24 bits of the first location of the DMA destination.

5.3.13

Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030)

Bit(s)

Type

Default

Name

Description

31:22

Reserved.

21:0

22'b0

HDma_byte_count

The number of bytes of data to be transferred via the host DMA.

5.3.14

Host Master Mode DMA Timers (HDMA_TIMERS: 0x002D0034)

Bit(s)

Type

Default

Name

Description

31:16

Reserved.

15:8

8'b0

HDMA_ISOC_TIMER

Timer which dictates the transfer rate for an isochronous mode
DMA transfer in terms of the number of BCLK periods.

7:0

8'b0

HDMA_INACTIVE_TIMER

The minimum interval, in terms of number of BCLK periods,
between subsequent accesses to an external DMA source or
destination.

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

6-3

6.2

Available Vendor SDRAM ICs and Features

Although the EMAC is not fully PC100 compliant due to the fact that both the CAS#
latency and the burst length are hard wired, many other PC100 compliant vendor
SDRAMs are usable for the EMAC design. Table 6-3 lists some of these SDRAMs and
their corresponding features and access timings.

Table 6-3. Available SDRAM Vendors

1M x 16 x 4 SDRAM

Input

Output

Initialization

Sequence

Spec./

Vendor

Basic

Features

Ref.

Rate

Clock
Cycle

Setup

Hold

Valid

Hold

Valid to Z

Intel
PC100 Spec.
(Rev. 1.63)

CL = 2,3
BL = 1,2,4
Burst Read
Burst Write
Auto Refresh

Period: 10 ns
High: 3 ns
Low: 3 ns

2 ns

1 ns

CL = 3: 6 ns
C

= 2: 6 ns

3 ns

Min: 3 ns
Max: 9 ns

200

s -> Precharge ->

8RF -> MRS-> 1st
Command

Micron
MT48LC4M16A2

CL = 1,2,3
BL = 1,2,4,8,FP
Burst Read
Burst Write
Single Write
Auto Refresh
Self Refresh

15.6

CL = 3: 8 ns
CL = 2: 10 ns

2 ns

1 ns

CL = 3: 6 ns
CL = 2: 6 ns

1.8 ns CL = 3: 6 ns

CL = 2: 7 ns

100

s -> Precharge ->

2RF min -> MRS -> 1st
Command

Samsung
KM416S4030D

CL = 2,3
BL = 1,2,4,8,FP
Burst Read
Burst Write
Auto Refresh
Self Refresh

15.6

Period: 10 ns

2 ns

1 ns

CL = 3: 6 ns
CL = 2: 6 ns

3 ns

CL = 3: 6 ns
CL = 2: 7 ns

100

s -> Precharge ->

2RF min -> MRS-> 1st
Command

Fujitsu
MB81F641642D

CL = 2,3
BL = 2,4,8,FP
Burst Read
Burst Write
Single Write
Auto Refresh
Self Refresh

15.6

Period: 10 ns
High: 3 ns
Low: 3 ns

2 ns

1 ns

CL = 3: 6 ns
CL = 2: 6 ns

3 ns

Min: 3 ns
Max: 6 ns

100

s -> Precharge ->

2RF min -> MRS-> 1st
Command

NEC
PD4564841-10

CL = 2,3
BL = 1,2,4,8,FP
Burst Read
Single Write
Auto Refresh
Self Refresh

15.6

CL = 3: 10 ns
CL = 2: 13 ns
High: 3 ns
Low: 3 ns

2 ns

1 ns

CL = 3: 6 ns
CL = 2: 7 ns

3 ns

CL = 3: 6 ns
CL = 2: 7 ns
Min: 3 ns

200

s -> Precharge ->

2RF min -> MRS-> 1st
Command

IBM
19L3264-10

CL = 2,3
BL = 1,2,4,8,FP
Burst Read
Single Write
Auto Refresh
Self Refresh

15.6

CL = 3: 10 ns
CL = 2: 15 ns

3 ns

1 ns

CL = 3: 7 ns
CL = 2: 8 ns

3 ns

Min: 3 ns
Max: 7 ns

200

s -> Precharge ->

8RF -> MRS-> 1st
Command

Toshiba
TC59S6416BFT-
10

CL = 2,3
BL = 1,2,4,8,FP
Burst Read
Single Write
Auto Refresh
Self Refresh

15.6

10 ns

2.5 ns

1 ns

7 ns

3 ns

Min: 3 ns
Max: 10 ns

200

s -> Precharge ->

8RF -> MRS-> 1st
Command

CX82100 Home Network Processor Data Sheet

6-4

Conexant Proprietary and Confidential Information

101306C

6.3

Supported Configurations

Table 6-4 lists supported SDRAM configurations. There are only one or two memory ICs
at most that reside on the external SDRAM bus (e.g., two 2M x 8 SDRAMs are required
to get 4 MB). This bus is not shared with any other external function. Since the EMC
buffers write data phases, this pipelined activity implies that the SDRAM bus can be busy
concurrently with asynchronous and independent host bus transfers. (An external host can
read/write SDRAM as well.)

Table 6-4. Allowed SDRAM Configurations

Total

Memory

Config.

No. of

SDRAMs

SDRAM

Config.

SDRAM

Capacity

SDRAM

No. of

Banks

SDRAM

No. of

Rows

SDRAM

No. of

Columns

2 MB

1Mb x 16

16 Mb

2Kb

256

4 MB

2Mb x 16

2Mb x 8

16 Mb

2Kb

512

8 MB

4Mb x 16

64 Mb

4Kb

256

6.4

Access Cycles

The EMC's SDRAM 16-bit interface is synchronous. All of the SDRAM inputs are
registered on the positive edge of MCLK. The SDRAM uses an internal pipelined
architecture to achieve high-speed operation. Read and write accesses to the SDRAM are
burst oriented (it's been noted from the simulation that the EMAC design only allows
read accesses to the SDRAM to be burst oriented). A burst of 8 allows a cache line (16
bytes) to be refilled in one single read. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or WRITE command.

6.5

Initialization

The SDRAM requires a 200

µs delay prior to applying an executable command. The

delay begins after reset when power and clock are stable. The microcontroller should not
access the SDRAM during this time, otherwise all processes will be held up while the
EMC inserts wait states for the full initialization duration. No user intervention is
required during the initialization process. All appropriate settings are managed by the
SDRAM controller.

6.6

Refresh

The SDRAM controller supports Auto-Refresh. Refresh requests are generated to meet a
15.625

µs per row interval (to be safe, it is preferable that refresh requests could be

generated at a rate less than 15.625

µs per row interval). Refresh cycles are transparent to

the host, but will insert wait cycles if the memory is accessed during a refresh request.
Refresh requests have top priority when accessing the memory. Refresh cycles will not
interrupt a memory cycle in process.

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

6-7

6.11

SRAM Interface

The HNP EMC can alternatively interface to SRAM memory. The SDRAM associated
pins are used for this interface and are multiplexed to either interface to SDRAM or
SRAM. SDRAM or SRAM interface is controlled by the EMCR register and allows for
different external sizes and up to two SRAM devices. Using two 512-kbyte SRAM
devices (256k x 16 each), a maximum of 1 MB of external SRAM can be achieved. The
EMCR register controls for SRAM read/write wait state control, selection of one or two
memory chips, and selection of various sizes for each of the memories.

The SDRAM-to-SRAM signal mapping is shown in Table 6-6.

If one SRAMs are used, connect CE_SRAM1# to the SRAM CE# (Chip Enable) and
leave CE_SRAM2# open.

If two SRAMs are used, connect CE_SRAM1# to the lower address range SRAM
(SRAM 1) CE# and CE_SRAM2# to the upper address range SRAM (SRAM 2) CE#.

For the SRAMs, connect OE# (Output Enable), BLE# (Byte Low Enable), and BHE#
(Byte High Enable) to VSS.

Table 6-6. HNP to SDRAM/SRAM Interface Signal Mapping

HNP Pin Signal

SDRAM Interface

SRAM Pin Signal

MCKE

CKE

A17

MCAS#

A16

MB1

A15

MB0

A14

MM1

A13

MM0

A12

MA[11:0]

A[11:0]

MD[15:0]

D[15:0]

IO[15:0]

MCS#

CS#

CE# (SRAM 1)

MRAS#

RAS#

CE# (SRAM 2)

MWE#

WE#

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6-8

Conexant Proprietary and Confidential Information

101306C

6.12

EMC Register

The EMC register is identified in Table 6-7.

Table 6-7. EMC Register

Register Label

Register Name

ASB Address

Type

Default Value

Ref.

EMCR

External Memory Control Register

0x00350010

0x00000000

6.12.1

External Memory Control Register (EMCR: 0x00350010)

Bit(s)

Type

Default

Name

Description

7:6

2'b00

SRWSC

SRAM Read/Write Wait State Control.

00 =

No extra delay.

01 =

Delayed by one BCLK period.

10 =

Delayed by two BCLK periods.

11 =

Delayed by three BCLK periods.

Note: The delay cycles are extra to the normal access cycles.

5:4

2'b00

SRCSEL2

SRAM Chip Select 2.

00 =

Do not select the second SRAM chip.

01 =

Select the second SRAM chip, size = 64K x 16.

10 =

Select the second SRAM chip, size = 128K x 16.

11 =

Select the second SRAM chip, size = 256K x 16.

Notes:
1.

EXMSEL must be 2'b10 if the second SRAM chip is selected.

The size for the second SRAM must be no greater than the size
of the first SRAM.

If the second SRAM size is programmed at a value greater than
that of the first SRAM, then the actual size for the second SRAM
will be reduced to the same size as the first automatically by the
hardware.

3:2

2'b00

SRCSEL1

SRAM Chip Select 1.

00 =

Do not select the first SRAM chip.

01 =

Select the first SRAM chip, size = 64K x 16.

10 =

Select the first SRAM chip, size = 128K x 16.

11 =

Select the first SRAM chip, size = 256K x 16.

Note: EXMSEL must be 2'b10 if the first SRAM chip is selected.

1:0

2'b00

EXMSEL

External Memory Select.

00 =

Select SDRAM interface; SDRAM in Disabled Mode.

01 =

Select SDRAM interface; SDRAM in Enabled Mode.

10 =

Select SRAM interface.

11 =

Reserved.

CX82100 Home Network Processor Data Sheet

101306C

Conexant Proprietary and Confidential Information

7-1

Ethernet Media Access Control Interface Description

The HNP implements the Ethernet Media Access Control (EMAC) as defined in
Reference [4]. Also implemented is the MII interface to the physical layer as defined in
Reference [5].

In the OSI reference model as shown in Figure 7-1, the lowest layer is Physical and the
next layer up is Data Link. The Data Link layer is segmented into 2 parts, Medium
Access Control (MAC) which interfaces to the PHY, and the Logical Link Control (LLC)
which interfaces to the MAC and to higher layers.

Figure 7-1. MAC Sublayer Partition, Relationship to OSI Reference Model

101545_028

Reconciliation

PMA

PLS

Reconciliation

PMA

PLS

PMD

Physical

Network

Transport

Session

Presentation

Application

Data Link

PMA

OSI Reference M odel

Layers

LAN CSM A/CD Layers

Higher Layers

AUI

1 Mb/s, 10 Mb/s

10 Mb/s

100 Mb/s

AUI = Attachm ent Unit Interface
MDI = Medium Dependent Interface
MII = Media Independent Interface
PLS = Physical Layer Signaling
PMA = Physical Medium Attachm ent
PMD = Physical Medium Dependent

PLS

Medium

MII

MDI

LLC - Logical Link Control

M AC - M edia Access Control

The LLC together with the MAC must provide the following Data Link functionality:
· Data Encapsulation (transmit and receive)

- Framing (frame boundary delimitation, frame synchronization)
- Addressing (handling of source and destination addresses)

· Error detection (detection of physical medium transmission errors)

- Media Access Management
- Medium Allocation (collision avoidance)
- Contention Resolution (collision handling)

CX82100 Home Network Processor Data Sheet

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Conexant Proprietary and Confidential Information

101306C

7.1

MAC Frame Format

Figure 7-2 shows the MAC frame format supported by the HNP (see Section 3.1.1 of
Reference [4]). As depicted in the figure, the bytes of a frame are transmitted from top to
bottom. The bits of each byte in each field (with the exception of the FCS) are
transmitted from the LSb to MSb (i.e., LSb transmitted first).

Figure 7-2. Ethernet MAC Frame Format

101545_029

Pream ble

LLC Data

Length

Source Address (SA)

Destination Address (DA)

Start Fram e Delim iter (SFD)

Fram e Check Sequence (FCS)

PAD

2 or 6 Bytes

7 Bytes

2 or 6 Bytes

1 Byte

2 Bytes

(variable)

4 Bytes

i
th

r
a

i
tte

fro

-
to

-B

tto

Defined in Standard

Pream ble

LLC Data

Length

Source Address (SA)

Destination Address (DA)

Start Fram e Delim iter (SFD)

Fram e Check Sequence (FCS)

PAD

6 Bytes

7 Bytes

6 Bytes

1 Byte

2 Bytes

(variable)

4 Bytes

Implemented

i
el

ds i

v
o

l
v
ed i

put

t
i
o

At the head of the MAC frame is the 7-byte preamble 0xAA AA AA AA AA AA AA
followed by the 1-byte Start of Frame Delimiter (SFD) 0xAB. The MAC receiver must
detect the SFD pattern 0xAB. After SFD the MAC must begin receiving the frame
(assuming the Carrier Sense signal is asserted).

The address fields are the next fields in the frame. First is the 48-bit destination address
followed by the 48-bit source address. Then comes the 2-byte length field. Then comes
the LLC data and any pad bits required so the frame size is the minimum allowable
(which is 64 bytes not including FCS).

Finally, we have the 4 byte frame check sequence (FCS) which is a CRC to check for
frame errors due to Ethernet PHY (EPHY) transmission impairments. All fields except
the preamble, SFD, and FCS are used to compute the CRC. The CRC generating
polynomial is G(x) = X

+X+1.

The 32 bits of the CRC value are placed in the FCS field so that the X

term is the

leftmost bit of the first byte of the field, and the X

term is the rightmost bit of the last

byte of the field. The bits of the FCS field are thus transmitted in the order X

, X

, ...,

, X

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7.3

EMAC Functional Features

The EMAC block supports the MAC sublayer of the IEEE 802.3 and allows it to be
connected to an IEEE 802.3 10/100 Mbps (100BASE-T and 10BASE-T) MII compatible
EPHY device. The EMAC block supports the following features:
· For frame transmission

- Accepts data from host and constructs a frame
- Presents nibble data stream to the EPHY

· For frame reception

- Receives nibble data stream from the EPHY
- Presents to the host frames that are either broadcast/multicast frames or directly

addressed to the local station

- Discards or passes to the host all frames not addressed to it (programmable)
- Defers transmission whenever the medium is busy
- Delays transmission of frame for specified interframe gap (IFG) period
- Appends preamble, SFD, FCS to frames, and inserts PAD field for frames

whose data length is less than minFrameSize

- Halts transmission when collision is detected
- Enforces collision to ensure propagation throughout network by sending jam

message

- Schedules retransmission after a collision until attemptLimit is reached
- Checks received frames for transmission errors by way of FCS
- Discards received frames that are less than minFrameSize.
- Removes preamble and SFD. FCS and pad field (if necessary) from received

frames are passed along.

- IEEE 802.3u MII Physical Layer Interface
- Full-duplex or half-duplex operation
- Normal and internal loopback mode
- Linked list transmit data structures for scatter/gather support.
- Programmable data padding and FCS capability
- Address filtering (promiscuous, perfect, inverse and hash filtering)
- Programmable IFG
- Generates signals for software to maintain MIB (Management Information

Base) status in software

- Management Data Interface (MDI) to an MII compliant EPHY
- qword (64-bit) interface to the DMA controller

In half-duplex mode, the HNP checks the line condition before starting to transmit. If the
condition is clear, it starts transmitting (after IFG). Transmit enable (EMx_TXEN) asserts
and data is transferred through the MII port.

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Full-duplex operation allows simultaneous transmission and reception of data, which can
effectively double data throughput to 20 or 200 Mb/s. In full-duplex mode, the HNP
starts transmitting a frame provided that IFG duration time has elapsed since its previous
transmission. Since there is no collision in full-duplex mode, the transmission always
ends successfully. The HNP monitors the line for a new frame transmission in both half
and full duplex modes. A new frame transmission is defined as both transmit data valid
and carrier sense asserted.

The following features of the EMAC should be taken into account:

· The FCS is defined as a 32-bit field, which means the minimum number of data

bytes required for a meaningful FCS is 4 (i.e. you can not generate a 32-bit FCS
from data that is shorter than 32-bits). Packets which are less than 4 bytes long,
should not be checked for FCS.

· Received EMAC frames are padded to align to qword boundaries, during

reception, prior to DMAC transfer. However, the length that is used in the length
status field is calculated prior to the padding insertion. This length field, FL, bits
31-16 of the RMAC in-line status qword, is provided in bytes. This length, FL,
includes the entire frame that was transmitted, including CRC, but it does not
include the padding bytes that were added by the EMAC receiver to align to the
qword boundary. The next frame is defined to start at the beginning of that same
qword boundary.

· Setting up the EMAC receiver for address filtering is done by directly

programming all filter related register bits (E_NA_HP, E_NA_HO, E_NA_IF,
E_NA_PR, and E_NA_PM) via writes to the E_NA register.

· If an RX FIFO overflow interrupt occurs, the RX should be reset via bit

E_NA_RRX in the E_NA register. The most recently written packet in the RX
circular buffer is damaged, and must be aborted by the software.

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7.6

EMAC Interrupts

The EMAC provides three interrupts each for EMAC1 and EMAC2:
· Int_EMAC#{x}_ERR (diagnostics/exception interrupt)
· Int_DMAC_EMAC#{x}_RX (packet received interrupt)
· Int_DMAC_EMAC#{x}_TX (transmission complete interrupt)
where {x} indicates the EMAC number (1 or 2).

These interrupt bits are located in the INT_Stat register (see Section 11.2.2).

Int_EMAC#{x}_ERR is set to 1 if any number of EMAC interrupts occur. Before an
EMAC interrupt can be recognized by the HNP, its corresponding enable bit must be set
to 1 in E_IE_{x}. The equation for the Int_EMAC#{x}_ERR is as follows:

Int_EMAC#{x}_ERR =

(E_IE_AU and E_LP_AU) or

(E_IE_AI and (E_S_ES or E_S_TUF or E_S_TOF or E_S_RO or E_S_TJT or
E_S_RWT)) or

E_IE_NI and (E_LP_RI or E_LP_TI) or

(E_IE_TU and E_S_TU) or

(E_IE_RW and E_S_RWT) or

(E_IE_TOF and E_S_TOF) or

(E_IE_TUF and E_S_TUF) or

(E_IE_ED and E_S_ED) or

(E_IE_DF and E_S_DF) or

(E_IE_RLD and E_S_RLD) or

(E_IE_TF and E_S_TF) or

(E_IE_TJT and E_S_TJT) or

(E_IE_NCRS and E_S_NCRS) or

(E_IE_LCRS and E_S_LCRS) or

(E_IE_16 and E_S_16) or

(E_IE_LC and E_S_LC) or

(E_IE_RI and E_LP_RI) or

(E_IE_TI and E_LP_TI)

Int_DMAC_EMAC#{x}_RX bit field is set to 1 in the INT_Stat register after the
receiver posts the status in the status field of the RX buffer for a good packet when
E_NA_PB bit of E_NA_{x} is 0 (do not pass bad packet). When E_NA_PB is set to 1
(pass bad or good packet), The Int_DMAC_EMAC#{x}_RX bit is set after the receiver
post the status for a good or bad packet.

Int_DMAC_EMAC#{x}_TX bit field is set to 1 in the INT_Stat register after the
transmitter posts the status of the packet in the TX buffer or when the transmitter gets a
stop descriptor (ready bit in the TDES is zero).

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7.7

TMAC Architecture

Before the host requests transmission of a frame, it constructs the data (LLC data) field of
the frame in memory. The TMAC appends a preamble and a SFD to the beginning of the
frame. Using information from the descriptor, TMAC also appends a PAD at the end of
the data field of sufficient length to ensure that the transmitted frame length satisfies a
minimum frame. TMAC then attempts to avoid contention with other traffic on the
medium by monitoring the carrier sense signal provided by the Ethernet PHY and
deferring to passing traffic. When the medium is clear, frame transmission is initiated
(after a brief interframe delay to provide recovery time for other devices on the medium).
The TMAC then provides data nibbles to the EPHY on the MII.

The EPHY monitors the medium and generates the collision detect signal, which, in the
contention-free case, remains off for the duration of the frame. When transmission has
completed without contention, the TMAC informs the host by writing status into the
memory and awaits the next request.

7.7.1

Transmit Frame Structure

Before the TMAC can start transmitting a frame containing the LLC data, a transmit
message structure as shown in Figure 7-5 must be constructed by the host in ARM's
memory. TMAC reads data from the memory (via DMA channel 1 or 3) to transmit via
MII and writes data into the memory to update the status. The ARM host is the master for
TMAC transmit operations and serves data to the TMAC via the APB. It is also the host's
task to assemble Ethernet frames to be sent out by the TMAC. The transmit descriptor
(TDES), the transmit status (TSTAT), and the sequence of transmitter DMA operation
are described below. Note that the qword count which is to be loaded into the
DMAC_{x}_CNT1 register should always include the first qword reserved for the
transmit status.

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7.7.3

Transmit Status (TSTAT)

The contents of the Transmit Status (TSTAT) are described in Table 7-3.

Table 7-3. Transmit Status Format

Bit(s)

Default

Type

Name

Description

1'b0

TDN

Transmit Completed.

0 = Transmit not completed successfully.
1 = Transmit completed successfully (from buffer manager).

1'b0

Transmit Stopped.

0 = Transmit not stopped.
1 = Transmit stopped (descriptor not ready).

29:21

Unused.

20:17

4'b0

Transmit State.

0 = MII transmitter state inactive.
1 = MII transmitter state active (except during setup frames).

For test only.

1'b0

TOF

Transmit Buffer Manager FIFO Overflow.

0 = Transmit buffer manager FIFO overflow has not occurred

(MIB11).

1 = Transmit buffer manager FIFO overflow has occurred.

1'b0

TUF

Transmit Buffer Manager FIFO Underflow.

0 = Transmit buffer manager FIFO underflow has not occurred

(MIB11).

1 = Transmit buffer manager FIFO underflow has occurred (MIB11).

1'b0

Excessive Transmit Deferrals.

0 = Excessive deferral did not occur.
1 = The HNP is attempting to transmit and is deferred longer than:

10 Mbps: 8192 x 400 ns
100 Mbps: 81920 x 40 ns

1'b0

Frame Deferred.

0 = Frame has not been deferred at least once (MIB8).
1 = Frame has been deferred at least once (MIB8).

1'b0

*, **

Frame Transmit Completed.

0 = Frame transmit not completed successfully (from MII interface).
1 = Frame transmit completed successfully (from MII interface).

1'b0

Transmit Error Summary.

0 = Frame has not been deferred at least once (MIB8).
1 = Transmitter error summary (TF or C16 or LC or NCRS or LCRS

or TJT).

1'b0

RLD

Reload.

0 = Frame has not been deferred at least once (MIB8).
1 = Transmit FIFO reload/abort during frame (includes collisions).

1'b0

*, **

Transmit Fault (from MII Interface).

0 = Unexpected transmit data request during frame has not

occurred.

1 = Unexpected transmit data request during frame has occurred.

1'b0

TJT

Transmit Jabber Timeout.

0 = Jabber timer not expired.
1 = Jabber timer expired.

E_NA_HUJ and E_NA_HUJ must be configured for this bit to function.

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7.7.4

Sequence of Transmitter DMA Operation

TMAC DMA operation is illustrated in Figure 7-6.

Figure 7-6. TMAC DMA Operation for Channel {x} = 1 or 3

101545_033

Host programes the base
pointer DMAC_{x}_PTR1 and
the length DMAC_{x}_CNT1 for
the 1st fragment of the frame

Host assembles the frame to
be transmitted in linked list
structure and writes the TDES

Host sets the E_NA_STRT bit in
register E_NA_{x} to cause the
TMAC to start the transmission

TMAC starts the DMA on channel {x} by issuing
the DMA_SAVE command to DM AC. DMAC
saves PTR 1 to PRT2 and CNT1 to CNT2.

TMAC issues DMA_XN XT
command to DMAC to skip
the TSTAT field.

TMAC issues DMA_XNXT command
to DMAC to receive the TDES and
the 1st 4 bytes of the data.

TDES.RDY bit ON?

TM AC issues DMA_XNXT
commands to fill up the FIFO
and starts transmitting nibbles.

Last double word

received?

yes

TM AC updates the E_S_TU bit in register
E_Stat_1 (or E_Stat_2) to interrupt the
host, providing the bit E_IE_TU is set in
register E_IE_1 (or E_IE_2)

Host reads the bit
TSTAT.TDN to determine
the transmission status.

TMAC Transmission

stopped.

yes

TMAC issues
DMA_XSAVE to request
DMAC to write the TSTAT
to host memory

TMAC issues DMA_IN TR
to DMAC to signal the
end of a frame.

TMAC continues to
transmit nibbles in the
FIFO until completion.

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7.8

RMAC Architecture

7.8.1

Support for the Detection of Invalid MAC Frames

As defined in the 802.3 specification, an invalid MAC frame meets at least one of the
following conditions:

· The frame length is inconsistent with the length field.
· The frame length is not an integral number of bytes.
· The frame bits (excluding FCS) do not generate correct CRC value (CRC mismatch).
The 802.3 specification requires that contents of invalid frames must not be passed to
LLC. This functional requirement will be handled by software. The software will be
supplied status to distinguish valid from invalid frames. This is described as follows:

Condition 1

The RMAC hardware will not parse the type/length field. In the case of a valid frame, the
hardware will infer the length based on MII signaling, and pass the length (the FL field)
as part of the "status qword" (see Section 7.8.5). For invalid frames, the length
information may or may not be available to the software. In the case where the
type/length field is type, neither hardware nor software will detect this invalid condition.
If the type/length field is length, the software will detect this condition. The type/length
field indicates whether the frame is in IEEE 802.3 format or Ethernet format. A field
greater than 1500 is interpreted as a type field, which defines the type of protocol of the
frame. A field smaller than or equal to 1500 is interpreted as a length field, which
indicates the number of data bytes in the frame.

Condition 2

The RMAC hardware will detect this invalid condition and report it in the status qword as
bit DB (dribble bit).

Condition 3

The RMAC hardware will detect and record this invalid condition by using a local
Management Information Base (MIB) counter, named "CRC" (bits 52-59 of the status
qword, see Table 7-8). This is an 8-bit counter which will be reset when the RMAC
hardware detects that a good packet has been read by the DMAC. It will be incremented
by one when a CRC mismatch occurs. This counter is passed to the software as part of
the status qword.

7.8.2

Support for the Reception Without Contention

The 802.3 specification requires that each receiving station is responsible for collecting
data bits from MII as long as the Carrier Sense signal is asserted. When Carrier Sense is
deasserted, the frame is truncated to a byte boundary, if necessary, and passed to Receive
Data Decapsulation for processing. Receive Data Decapsulation is required to check the
frame's Destination Address field to decide if the frame should be received by this
station. If so, it passes the Destination Address, the Source Address, and LLC data unit to

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the LLC sublayer along with a status code indicating reception_complete or
reception_too_long (longer than 1518 bytes).

To support this requirement, address filtering (see Section 7.8.4) is to be used. Address
filtering is very computation intensive since it is required to be performed on every
packet on the Ethernet, regardless of its intended destination. Address filtering will be
supported in the RMAC hardware for "Destination Address" only. Nevertheless, the
software will be capable to program the hardware to promiscuous mode (see page 7-22),
which would pass all packets. Also, the software will be able to program the hardware to
pass bad packets. Therefore, the software will have flexibility to handle address filtering
if it so chooses.

The RMAC hardware will also provide hooks to the software to support
reception_complete or reception_too_long to allow compliance with the 802.3
specification requirement. These conditions are reported in the status qword.

7.8.3

Support for the Reception With Contention

EMx_COL asserted indicates collision detected. RMAC is required to distinguish frame
fragments received during collisions from valid frames. It will be implemented in
hardware. Early collisions will be ignored. Late collisions, after DMAC transfer
initiation, will be reported in the RMAC status qword as bit LC (late collision).

7.8.4

Address Filtering

The HNP EMAC supports address filtering in hardware for full 48-bit Ethernet
destination addresses only. The process for setting up the address filters and configuring
the filtering modes are described in the next few sections.

Setup Frame

The TMAC and RMAC operate independently during normal operation except during
setup frames. Setup frames are not transmitted on the MII interface but are looped back
from the TMAC to the RMAC and are used to program the address filters. A setup frame
defines the Ethernet addresses that are used to filter all incoming frames and must be
processed before the reception process is started, except when it operates in promiscuous
filtering mode. When processing the setup frame, the receiver logic temporarily
disengages from the MII interface and the transmission process must be running. The
setup frame is processed after all preceding frames have been transmitted and the current
frame reception (if any) is completed. The setup frame size must be exactly 192 bytes
(see Table 7-4).

Perfect Address Filtering

The HNP system can store up to 16 full 48-bit Ethernet destination addresses. RMAC
compares the destination address of any incoming frame to these addresses and decides
whether to reject or accept the frame based on the filtering mode configured in the
E_NA_1 or E_NA_2 register (defined in Section 7.11.3). This filtering method is called
perfect address filtering (as opposed to the hashing-based imperfect address filtering
defined in this section) because it accepts addresses that

· Do not match if in inverse filtering mode (defined in this section).
· Match if not in inverse filtering mode.
Table 7-4 shows the perfect address filtering Setup Frame format in the host memory.
The RMAC only keeps the column labeled "15....0" in a 48 x 16-bit hardware buffer.

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Table 7-4. Setup Frame Buffer Format

Entry No.

Bytes

Bits 31:16

Bits 15:0

Physical Address No.

3:0

XXXXXXXXXXXXXXXX

Bytes [1:0]

7:4

XXXXXXXXXXXXXXXX

Bytes [3:2]

11:8

XXXXXXXXXXXXXXXX

Bytes [5:4]

Address 0