UltraLogicTM 128-Macrocell Flash CPLD
fax id: 6139
CY7C374i
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 1995 Revised December 19, 1997
Features
128 macrocells in eight logic blocks
64 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISRTM) Flash technology
-- JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
-- f
MAX
= 125 MHz
-- t
PD
= 10 ns
-- t
S
= 5.5 ns
-- t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
Pin compatible with the CY7C373i
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370iTM family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogicTM F
LASH
370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Logic Block Diagram
7C374i-1
PIM
INPUT
MACROCELL
CLOCK
INPUTS
4
4
36
16
16
36
LOGIC
BLOCK
36
16
16
36
8 I/Os
36
36
36
16
16
36
16
16
32
32
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
I/O
7
A
INPUTS
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
8
I/O
15
I/O
16
I/O
23
I/O
24
I/O
31
I/O
56
I/O
63
I/O
48
I/O
55
I/O
40
I/O
47
I/O
32
I/O
39
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
Selection Guide
7C374i125
7C374i100
7C374i83
7C374i66
7C374iL66
Maximum Propagation Delay
[1]
, t
PD
(ns)
10
12
15
20
20
Minimum Set-Up, t
S
(ns)
5.5
6
8
10
10
Maximum Clock to Output
[1]
, t
CO
(ns)
6.5
7
8
10
10
Typical Supply Current, I
CC
(mA)
125
125
125
125
75
Note:
1.
The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
CY7C374i
4
Functional Description
(continued)
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource--the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the F
LASH
370i family, the CY7C374i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O pins on the
CY7C374i. In addition, there is one dedicated input and four
input/clock pins.
Finally, the CY7C374i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C374i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C374i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C374i have I/O pins associ-
ated with them. The input to the macrocell is the sum of be-
tween 0 and 16 product terms from the product term allocator.
The I/O macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and two
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the addi-
tion of input register capability. The user can program the bur-
ied macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C374i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, "An In-
troduction to In System Reprogramming with F
LASH
370i."
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term dis-
tribution.
3.3V or 5.0V I/O Operation
The F
LASH
370i family can be configured to operate in both 3.3V
and 5.0V systems. All devices have two sets of V
CC
pins: one
set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
CCIO
pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability
is available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device's performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C371i is available from Cy-
press's
Warp2, Warp2SimTM, and Warp3 software packag-
es. All of these products are based on the IEEE-standard
VHDL language. Cypress also actively supports third-party de-
sign tools from companies such as Synopsys, Mentor Graph-
ics, Cadence, and Synario. Please refer to third-party tool sup-
port for further information.
CY7C374i
5
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied ............................................. 55
C to +125
C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
DC Program Voltage .....................................................12.5V
Output Current into Outputs......................................... 16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Notes:
2.
T
A
is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
4.
If V
CCIO
is not specified, the device can be operating in either 3.3V or 5V I/O mode; V
CC
=V
CCINT
.
5.
I
OH
= 2
mA, I
OL
= 2 mA for SDO.
6.
When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional
information.
7.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9.
Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
Operating Range
Range
Ambient
Temperature
V
CC
V
CCINT
V
CCIO
Commercial
0
C to +70
C
5V
.25V
5V
.25V
OR
3.3V
.3V
Industrial
-
40
C to +85
C
5V
.5V
5V
.5V
OR
3.3V
.3V
Military
[2]
55C to +125C
5V
.5V
Electrical Characteristics
Over the Operating Range
[3, 4]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 3.2 mA (Com'l/Ind)
[5]
2.4
V
I
OH
= 2.0 mA (Mil)
V
V
OHZ
Output HIGH Voltage
with Output Disabled
[9]
V
CC
= Max.
I
OH
= 0
A (Com'l/Ind)
[5, 6]
4.0
V
I
OH
= 50
A (Com'l/Ind)
[5, 6]
3.6
V
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 16 mA (Com'l/Ind)
[5]
0.5
V
I
OL
= 12 mA (Mil)
V
V
IH
Input HIGH Voltage
Guaranteed Input Logical HIGH voltage for all inputs
[7]
2.0
7.0
V
V
IL
Input LOW Voltage
Guaranteed Input Logical LOW voltage for all inputs
[7]
0.5
0.8
V
I
IX
Input Load Current
V
I
= Internal GND, V
I
= V
CC
10
+10
A
I
OZ
Output Leakage Current
V
CC
= Max., V
O
= GND or V
O
= V
CC
, Output Disabled
50
+50
A
V
CC
= Max., V
O
= 3.3V, Output Disabled
[6]
0
70
125
A
I
OS
Output Short
Circuit Current
[8, 9]
V
CC
= Max., V
OUT
= 0.5V
30
160
mA
I
CC
Power Supply Current
V
CC
= Max., I
OUT
= 0 mA,
Com'l/Ind.
125
200
mA
f = 1 MHz, V
IN
= GND, V
CC
[10]
Com'l "L" 66
75
125
mA
Military
125
250
mA
I
BHL
Input Bus Hold LOW
Sustaining Current
V
CC
= Min., V
IL
= 0.8V
+75
A
I
BHH
Input Bus Hold HIGH
Sustaining Current
V
CC
= Min., V
IH
= 2.0V
75
A
I
BHLO
Input Bus Hold LOW
Overdrive Current
V
CC
= Max.
+500
A
I
BHHO
Input Bus Hold HIGH
Overdrive Current
V
CC
= Max.
500
A
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