4K x 8/9 Dual-Port Static RAM

fax id: 5204

CY7C138
CY7C139

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

November 1996

1CY 7C13 9

Features

· True Dual-Ported memory cells which allow

simultaneous reads of the same memory location

· 4K x 8 organization (CY7C138)
· 4K x 9 organization (CY7C139)
· 0.65-micron CMOS for optimum speed/power
· High-speed access: 15 ns
· Low operating power: I

= 160 mA (max.)

· Fully asynchronous operation
· Automatic power-down
· TTL compatible
· Expandable data bus to 32/36 bits or more using

Master/Slave chip select when using more than one
device

· On-chip arbitration logic
· Semaphores included to permit software handshaking

between ports

· INT flag for port-to-port communication
· Available in 68-pin PLCC

Functional Description

The CY7C138 and CY7C139 are high-speed CMOS 4K x 8
and 4K x 9 dual-port static RAMs. Various arbitration schemes

are included on the CY7C138/9 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9
can be utilized as a standalone 8/9-bit dual-port static RAM or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 16/18-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications sta-
tus buffering, and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.

The CY7C138 and CY7C139 are available in a 68-pin PLCC.

Notes:

BUSY is an output in master mode and an input in slave mode.

Interrupt: push-pull output and requires no pull-up resistor.

C138-1

R/W

11L

11R

R/W

I/O

INTERRUPT

SEMAPHORE

ARBITRATION

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS
DECODER

SEM

BUSY

INT

M/S

(7C139)I/O

I/O

(7C139)

Logic Block Diagram

[2]

[1, 2]

R/W

CY7C138
CY7C139

Pin Configurations

Notes:

I/O

on the CY7C139.

I/O

on the CY7C139.

Top View

68-Pin PLCC

3132 33 34 35 36 37 38 39 40 41 42 43

5 4 3 2 1 68

66 65 64 63 62 61

INT

BUSY

GND

M/S

BUSY

INT

I/O

GND

I/O

GND

I/O

2728 29 30

9 8 7 6

I/O

C138-2

CY7C138/9

Pin Definitions

Left Port

Right Port

Description

I/O

0L7L(8L)

I/O

0R7R(8R)

Data Bus Input/Output

0L11L

0R11R

Address Lines

Chip Enable

Output Enable

R/W

Read/Write Enable

SEM

Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O

pin is used when writing to a

semaphore. Semaphores are requested by writing a 0 into the respective
location.

INT

Interrupt Flag. INT

is set when right port writes location FFE and is cleared

when left port reads location FFE. INT

is set when left port writes location

FFF and is cleared when right port reads location FFF.

BUSY

Busy Flag

M/S

Master or Slave Select

Power

GND

Ground

Selection Guide

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Maximum Access Time (ns)

Maximum Operating
Current (mA)

Commercial

220

180

160

Maximum Standby
Current for I

SB1

(mA)

Commercial

CY7C138
CY7C139

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature ................................. 65

C to +150

Ambient Temperature with
Power Applied............................................. 55

C to +125

Supply Voltage to Ground Potential ............... 0.5V to +7.0V

DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V

DC Input Voltage

[5]

......................................... 0.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......................................... >2001V
(per MILSTD883, Method 3015)

LatchUp Current ................................................... >200 mA

Operating Range

Range

Ambient

Temperature

Commercial

C to +70

5V ± 10%

Industrial

C to +85

5V ± 10%

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

7C138-15
7C139-15

7C138-25
7C139-25

Unit

Min.

Max.

Min.

Max.

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

2.2

Input LOW Voltage

0.8

Input Leakage Current

GND < V

< V

+10

Output Leakage Current

Output Disabled, GND < V

< V

+10

Operating Current

= Max.,

OUT

= 0 mA,

Outputs Disabled

Com'l

220

180

Ind

190

SB1

Standby Current
(Both Ports TTL Levels)

and CE

> V

f = f

MAX

[6]

Com'l

Ind

SB2

Standby Current
(One Port TTL Level)

and CE

> V

f = f

MAX

[6]

Com'l

130

110

Ind

120

SB3

Standby Current
(Both Ports CMOS Levels)

Both Ports
CE and CE

> V

0.2V,

> V

0.2V

or V

< 0.2V, f = 0

[6]

Com'l

Ind

SB4

Standby Current
(One Port CMOS Level)

One Port
CE

or CE

> V

0.2V,

> V

0.2V or

< 0.2V, Active

Port Outputs, f = f

MAX

[6]

Com'l

125

100

Ind

115

Notes:

Pulse width < 20 ns.

MAX

= 1/t

= All inputs cycling at f = 1/t

(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS

level standby I

SB3

CY7C138
CY7C139

]

Electrical Characteristics

Over the Operating Range

(continued)

Parameter

Description

Test Conditions

7C138-35
7C139-35

7C138-55
7C139-55

Unit

Min.

Max.

Min.

Max.

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

2.2

Input LOW Voltage

0.8

Input Leakage Current

GND < V

< V

+10

Output Leakage Current

Output Disabled, GND < V

< V

+10

Operating Current

= Max.,

OUT

= 0 mA,

Outputs Disabled

Com'l

160

Ind

180

SB1

Standby Current
(Both Ports TTL Levels)

and CE

> V

f = f

MAX

[6]

Com'l

Ind

SB2

Standby Current
(One Port TTL Level)

and CE

> V

f = f

MAX

[6]

Com'l

100

Ind

110

SB3

Standby Current
(Both Ports CMOS Levels)

Both Ports
CE and CE

> V

0.2V,

> V

0.2V

or V

< 0.2V, f = 0

[6]

Com'l

Ind

SB4

Standby Current
(One Port CMOS Level)

One Port
CE

or CE

> V

0.2V,

> V

0.2V or

< 0.2V, Active

Port Outputs, f = f

MAX

[6]

Com'l

Ind

100

Capacitance

[7]

Parameter

Description

Test Conditions

Max.

Unit

Input Capacitance

= 25

C, f = 1 MHz,

= 5.0V

OUT

Output Capacitance

AC Test Loads and Waveforms

Note:

Tested initially and after any design or process changes that may affect these parameters.

3.0V

GND

90%

10%

< 3 ns

10%

ALL INPUT PULSES

(a) Normal Load (Load 1)

R1=893

OUTPUT

R2=347

C = 30 pF

=250

=1.4V

OUTPUT

C=30pF

(b) Thé venin Equivalent(Load 1)

(c) Three-State Delay (Load 3)

C = 30 pF

OUTPUT

Load (Load 2)

C138-3

C138-4

C138-5

C138-6

C138-7

R1=893

R2=347

OUTPUT

C = 5 pF

CY7C138
CY7C139

Switching Characteristics

Over the Operating Range

[8]

Parameter

Description

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

Address to Data Valid

OHA

Output Hold From Address Change

ACE

CE LOW to Data Valid

DOE

OE LOW to Data Valid

LZOE

[9,10,11]

OE Low to Low Z

HZOE

[9,10,11]

OE HIGH to High Z

LZCE

[9,10,11]

CE LOW to Low Z

HZCE

[9,10,11]

CE HIGH to High Z

[11]

CE LOW to Power-Up

[11]

CE HIGH to Power-Down

WRITE CYCLE

Write Cycle Time

SCE

CE LOW to Write End

Address Set-Up to Write End

Address Hold From Write End

Address Set-Up to Write Start

PWE

Write Pulse Width

Data Set-Up to Write End

Data Hold From Write End

HZWE

[10,11]

R/W LOW to High Z

LZWE

[10,11]

R/W HIGH to Low Z

WDD

[12]

Write Pulse to Data Delay

DDD

[12]

Write Data Valid to Read Data Valid

BUSY TIMING

[13]

BLA

BUSY LOW from Address Match

BHA

BUSY HIGH from Address Mismatch

BLC

BUSY LOW from CE LOW

BHC

BUSY HIGH from CE HIGH

Port Set-Up for Priority

R/W LOW after BUSY LOW

R/W HIGH after BUSY HIGH

BDD

[14]

BUSY HIGH to Data Valid

Note

INTERRUPT TIMING

[13]

INS

INT Set Time

INR

INT Reset Time

CY7C138
CY7C139

SEMAPHORE TIMING

SOP

SEM Flag Update Pulse (OE or SEM)

SWRD

SEM Flag Write to Read Time

SPS

SEM Flag Contention Window

Switching Characteristics

Over the Operating Range

[8]

(continued)

Parameter

Description

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Switching Waveforms

Notes:

Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

and 30-pF load capacitance.

At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

10. Test conditions used are Load 3.

11.

This parameter is guaranteed but not tested.

12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Test conditions used are Load 2.
14. t

BDD

is a calculated parameter and is the greater of t

WDD

- t

PWE

(actual) or t

DDD

- t

(actual).

15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CE

= L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.

OHA

DATA VALID

PREVIOUS DATA VALID

DATA OUT

ADDRESS

C138-8

Read Cycle No. 1 (Either Port Address Access)

[15, 16]

ACE

LZOE

DOE

HZOE

HZCE

DATA VALID

DATA OUT

SEM or CE

LZCE

C138-9

Read Cycle No. 2 (Either Port CE/OE Access)

[15, 17, 18]

CY7C138
CY7C139

Notes:

19. BUSY = HIGH for the writing port.
20. CE

= CE

= LOW.

21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or (t

HZWE

+ t

) to allow the I/O drivers to turn off and data to be placed on the

bus for the required t

. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified

PWE

23. R/W must be HIGH during all address transitions.

Switching Waveforms

(continued)

VALID

DDD

WDD

MATCH

R/W

DATA

INR

DATA

OUTL

C138-10

ADDRESS

PWE

VALID

ADDRESS

Read Timing with Port-to-Port Delay (M/S = L)

[19, 20]

C138-11

DATA VALID

HIGH IMPEDANCE

SCE

PWE

HZOE

LZOE

SEM OR CE

R/W

DATA OUT

DATA IN

ADDRESS

Write Cycle No. 1: OE Three-States Data I/Os (Either Port)

[21, 22, 23]

CY7C138
CY7C139

Architecture

The CY7C138/9 consists of an array of 4K words of 8/9 bits
each of dualport RAM cells, I/O and address lines, and con-
trol signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle simul-
taneous writes/reads to the same location, a BUSY pin is provided on
each port. Two interrupt (INT) pins can be utilized for porttoport
communication. Two semaphore (SEM) control pins are used for al-
locating shared resources. With the M/S pin, the CY7C138/9 can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7C138/9 has an automatic power-down fea-
ture controlled by CE. Each port is provided with its own output enable
control (OE), which allows data to be read from the device.

Functional Description

Write Operation

Data must be set up for a duration of t

before the rising edge

of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the OE pin (see Write Cycle No. 1 waveform) or the
R/W pin (see Write Cycle No. 2 waveform). Data can be written to the
device t

HZOE

after the OE is deasserted or t

HZWE

after the falling edge

of R/W. Required inputs for non-contention operations are summa-
rized in

Table 1.

If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
the port t

DDD

after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE
and CE pins. Data will be available t

ACE

after CE or t

DOE

after OE is

asserted. If the user of the CY7C138/9 wishes to access a sema-
phore flag, then the SEM pin must be asserted instead of the CE pin.

Interrupts

The interrupt flag (INT) permits communications between
ports.When the left port writes to location FFF, the right port's interrupt
flag (INT

) is set. This flag is cleared when the right port reads that

same location. Setting the left port's interrupt flag (INT

) is accom-

plished when the right port writes to location FFE. This flag is cleared
when the left port reads location FFE. The message at FFF or FFE
is user-defined. See

Table 2 for input requirements for INT. INT

and

INT

are push-pull outputs and do not require pull-up resistors to op-

erate. BUSY

and BUSY

in master mode are push-pull outputs and

do not require pull-up resistors to operate.

Busy

The CY7C138/9 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports'
CEs are asserted and an address match occurs within t

of each

other the Busy logic will determine which port has access. If t

violated, one port will definitely gain permission to the location,
but it is not guaranteed which one. BUSY will be asserted t

BLA

after an address match or t

BLC

after CE is taken LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device

with no external components.Writing of slave devices must be
delayed until after the BUSY input has settled. Otherwise, the
slave chip may begin a write cycle during a contention situa-
tion.When presented as a HIGH input, the M/S pin allows the
device to be used as a master and therefore the BUSY line is
an output. BUSY can then be used to send the arbitration out-
come to a slave.

Semaphore Operation

The CY7C138/9 provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore loca-
tion. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t

SOP

before attempting to read the sema-

phore. The semaphore value will be available t

SWRD

+ t

DOE

after the rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control over the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore.When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the a sema-
phore.If the left side no longer requires the semaphore, a one
is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A

represents the

semaphore address. OE and R/W are used in the same man-
ner as a normal memory access.When writing or reading a
semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O

is used. If a zero is

written to the left port of an unused semaphore, a one will ap-
pear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set
to one for both sides. However, if the right port had requested
the semaphore (written a zero) while the left port had control,
the right port would immediately own the semaphore as soon
as the left port released it.

Table 3 shows sample semaphore

operations.

When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t

SPS

of each other, the semaphore will defi-

nitely be obtained by one side or the other, but there is no guar-
antee which side will control the semaphore.

Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.

CY7C138
CY7C139

Table 1. Non-Contending Read/Write

Inputs

Outputs

Operation

R/W

SEM

I/O

0-7/8

High Z

Power-Down

Data Out

Read Data in
Semaphore

High Z

I/O Lines Disabled

Data In

Write to Semaphore

Data Out

Read

Data In

Write

Illegal Condition

Table 2. Interrupt Operation Example (assumes BUSY

=BUSY

=HIGH)

Left Port

Right Port

Function

R/W

0-11

INT

R/W

0-11

INT

Set Left INT

FFE

Reset Left INT

FFE

Set Right INT

FFF

Reset Right INT

FFF

Table 3. Semaphore Operation Example

Function

I/O

0-7/8

Left

I/O

0-7/8

Right

Status

No action

Semaphore free

Left port writes semaphore

Left port obtains semaphore

Right port writes 0 to semaphore

Right side is denied access

Left port writes 1 to semaphore

Right port is granted access to semaphore

Left port writes 0 to semaphore

No change. Left port is denied access

Right port writes 1 to semaphore

Left port obtains semaphore

Left port writes 1 to semaphore

No port accessing semaphore address

Right port writes 0 to semaphore

Right port obtains semaphore

Right port writes 1 to semaphore

No port accessing semaphore

Left port writes 0 to semaphore

Left port obtains semaphore

Left port writes 1 to semaphore

No port accessing semaphore

CY7C138
CY7C139

Typical DC and AC Characteristics

1.4

1.0

0.4

4.0

4.5

5.0

5.5

6.0

125

1.2

1.0

120

1.0

2.0

3.0

4.0

SUPPLYVOLTAGE (V)

NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE

0.0

0.8

0.6

=5.0V

1.6

1.4

1.2

1.0

0.8

-55

125

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

1.4

1.3

1.2

1.0

0.9

4.0

4.5

5.0

5.5

6.0

SUPPLYVOLTAGE (V)

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

120

140

100

0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

VCC=5.0V

TA =25_C

0.6

0.8

=5.0V

=25°C

1.25

1.0

0.75

0.50

NORMALIZED I

vs.CYCLE TIME

CYCLE FREQUENCY (MHz)

1.00

0.25

1.0

2.0

3.0

5.0

25.0

30.0

20.0

10.0

5.0

200

400

600

800

15.0

0.0

SUPPLYVOLTAGE (V)

TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

4.0

1000

0.50

0.2

0.6

1.2

SB3

0.2

0.4

SB3

1.1

=4.5V

=25°C

=5.0V

=25°C

=0.5V

5.0

=5.0V

=25°C

160

200

5.0

0.75

CY7C138
CY7C139

© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

4K x9 Dual-Port SRAM

Document #: 3800536

Ordering Information

4K x8 Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C13815JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13825JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13825JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

CY7C13835JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13835JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

CY7C13855JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13855JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

Speed

(ns)

Ordering Code

Package

Type

Package Type

Operating

Range

CY7C13915JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13925JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13925JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

CY7C13935JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13935JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

CY7C13955JC

J81

68Lead Plastic Leaded Chip Carrier

Commercial

CY7C13955JI

J81

68Lead Plastic Leaded Chip Carrier

Industrial

Package Diagram

68-Lead Plastic Leaded Chip Carrier J81

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY2310ANZ

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY2310ANZ