PRELIMINARY
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output
Zero Delay Buffer
CY23EP09
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07760 Rev. *A
Revised April 25, 2005
Features
10 MHz to 220 MHz maximum operating range
Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
Multiple low-skew outputs
-- 45 ps typical output-output skew
-- One input drives nine outputs, grouped as 4 + 4 + 1
25 ps typical cycle-to-cycle jitter
15 ps typical period jitter
Standard and High drive strength options
Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages
3.3V or 2.5V operation
Industrial temperature available
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The -1H version operates up to 220
(200) MHz frequencies at 3.3V (2.5V), and has higher drive
than the -1 devices. All parts have on-chip PLLs that lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the "Select Input
Decoding" table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25
A of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP09 is available in different configurations, as
shown in the Ordering Information table. The CY23EP09-1 is
the base part. The CY23EP09-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Top View
Pin Configuration
PLL
MUX
Select Input
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
CLKOUT
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 2 of 11
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled "CY2305 and CY2309 as PCI and SDRAM Buffers".
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin Definition
Pin
Signal
Description
1
REF
[1]
Input reference frequency
2
CLKA1
[2]
Buffered clock output, Bank A
3
CLKA2
[2]
Buffered clock output, Bank A
4
V
DD
3.3V or 2.5V supply
5
GND
Ground
6
CLKB1
[2]
Buffered clock output, Bank B
7
CLKB2
[2]
Buffered clock output, Bank B
8
S2
[3]
Select input, bit 2
9
S1
[3]
Select input, bit 1
10
CLKB3
[2]
Buffered clock output, Bank B
11
CLKB4
[2]
Buffered clock output, Bank B
12
GND
Ground
13
V
DD
3.3V or 2.5V supply
14
CLKA3
[2]
Buffered clock output, Bank A
15
CLKA4
[2]
Buffered clock output, Bank A
16
CLKOUT
[2]
Buffered output, internal feedback on this pin
Select Input Decoding
S2
S1
CLOCK A1A4
CLOCK B1B4
CLKOUT
[4]
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 3 of 11
Absolute Maximum Conditions
Supply Voltage to Ground Potential ................. 0.5V to 4.6V
DC Input Voltage...................................... V
SS
0.5V to 4.6V
Storage Temperature.................................... 65C to 150C
Junction Temperature .................................................. 150C
Static Discharge Voltage
(per MIL-STD-883, Method 3015.............................. > 2000V
Operating Conditions
Parameter
Description
Min.
Max.
Unit
V
DD3.3
3.3V Supply Voltage
3.0
3.6
V
V
DD2.5
2.5V Supply Voltage
2.3
2.7
V
T
A
Operating Temperature (Ambient Temperature)--Commercial
0
70
C
Operating Temperature (Ambient Temperature)--Industrial
40
85
C
C
L
[5]
Load Capacitance, <100 MHz, 3.3V
30
pF
Load Capacitance, <100 MHz, 2.5V with High drive
30
pF
Load Capacitance, <133.3 MHz, 3.3V
22
pF
Load Capacitance, <133.3 MHz, 2.5V with High drive
22
pF
Load Capacitance, <133.3 MHz, 2.5V with Standard drive
15
pF
Load Capacitance, >133.3 MHz, 3.3V
15
pF
Load Capacitance, >133.3 MHz, 2.5V with High drive
15
pF
C
IN
Input Capacitance
[6]
5
pF
BW
Closed-loop bandwidth (typical), 3.3V
11.5
MHz
Closed-loop bandwidth (typical), 2.5V
0.8
MHz
R
OUT
Output Impedance (typical), 3.3V High drive
29
Output Impedance (typical), 3.3V Standard drive
41
Output Impedance (typical), 2.5V High drive
37
Output Impedance (typical), 2.5V Standard drive
41
t
PU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.01
50
ms
Theta Ja
[7]
Dissipation, Junction to Ambient, 16-pin SOIC
95
C/W
Dissipation, Junction to Ambient, 16-pin TSSOP
70
C/W
Theta Jc
[7]
Dissipation, Junction to Case, 16-pin SOIC
58
C/W
Dissipation, Junction to Case, 16-pin TSSOP
48
C/W
3.3V DC Electrical Specifications
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
DD
Supply Voltage
3.0
3.6
V
V
IL
Input LOW Voltage
0.8
V
V
IH
Input HIGH Voltage
2.0
V
DD
+0.3
V
I
IL
Input Leakage Current
0 < V
IN
< V
IL
10
A
I
IH
Input HIGH Current
V
IN
= V
DD
100
A
V
OL
Output LOW Voltage
I
OL
= 8 mA (standard drive)
I
OL
= 12 mA (High drive)
0.4
0.4
V
V
V
OH
Output HIGH Voltage
I
OH
= 8 mA (standard drive)
I
OH
= 12 mA (High drive)
2.4
2.4
V
V
I
DD
(PD mode)
Power Down Supply Current REF = 0 MHz (Commercial)
12
A
REF = 0 MHz (Industrial)
25
A
I
DD
Supply Current
Unloaded outputs, 66-MHz REF
30
mA
Notes:
5. Applies to Test Circuit #1
6. Applies to both REF Clock and internal feedback path on CLKOUT
7. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 4 of 11
2.5V DC Electrical Specifications
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
DD
Supply Voltage
2.3
2.7
V
V
IL
Input LOW Voltage
0.7
V
V
IH
Input HIGH Voltage
1.7
V
DD
+ 0.3
V
I
IL
Input Leakage Current
0<V
IN
< V
DD
10
A
I
IH
Input HIGH Current
V
IN
= V
DD
100
A
V
OL
Output LOW Voltage
I
OL
= 8 mA (Standard drive)
I
OL
= 12 mA (High drive)
0.5
0.5
V
V
V
OH
Output HIGH Voltage
I
OH
= 8 mA (Standard drive)
I
OH
= 12 mA (High drive)
V
DD
0.6
V
DD
0.6
V
V
I
DD
(PD mode)
Power Down Supply Current REF = 0 MHz (Commercial)
12
A
REF = 0 MHz (Industrial)
25
A
I
DD
Supply Current
Unloaded outputs, 66-MHz REF
45
mA
3.3V and 2.5V AC Electrical Specifications
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
1/t
1
Maximum Frequency
[8]
(Input/Output)
3.3V High drive
10
220
MHz
3.3V Standard drive
10
167
MHz
2.5V High drive
10
200
MHz
2.5V Standard drive
10
133
MHz
T
IDC
Input Duty Cycle
<133.3 MHz
25
75
%
>133.3 MHz
40
60
%
t
2
t
1
Output Duty Cycle
[9]
<133.3 MHz
47
53
%
>133.3 MHz
45
55
%
t
3,
t
4
Rise, Fall Time (3.3V)
[9]
Std drive, CL = 30 pF, <100 MHz
1.6
ns
Std drive, CL = 22 pF, <133.3 MHz
1.6
ns
Std drive, CL = 15 pF, <167 MHz
0.6
ns
High drive, CL = 30 pF, <100 MHz
1.2
ns
High drive, CL = 22 pF, <133.3 MHz
1.2
ns
High drive, CL = 15 pF, >133.3 MHz
0.5
ns
t
3,
t
4
Rise, Fall Time (2.5V)
[9]
Std drive, CL = 15 pF, <133.33 MHz
1.5
ns
High drive, CL = 30 pF, <100 MHz
2.1
ns
High drive, CL = 22 pF, <133.3 MHz
1.3
ns
High drive, CL = 15 pF, >133.3 MHz
1.2
ns
t
5
Output to Output Skew
[9]
All outputs equally loaded, 3.3V supply,
2.5 supply standard drive
45
100
ps
All outputs equally loaded, 2.5V supply high drive
110
ps
t
6
Delay, REF Rising Edge to
CLKOUT Rising Edge
[9]
PLL Bypass mode
1.5
4.4
ns
PLL enabled @ 3.3V
100
100
ps
PLL enabled @2.5V
200
200
ps
t
7
Part to Part Skew
[9]
Measured at V
DD
/2.
Any output to any output, 3.3V supply
150
ps
Measured at V
DD
/2.
Any output to any output, 2.5V supply
300
ps
Notes:
8. For the given maximum loading conditions. See C
L
in Operating Conditions Table
9. Parameter is guaranteed by design and characterization. Not 100% tested in production
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 5 of 11
t
LOCK
PLL Lock Time
[9]
Stable power supply, valid clocks presented on
REF and CLKOUT pins
1.0
ms
T
JCC
[9,10]
Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF
25
55
ps
3.3V supply, >66 MHz, <30 pF, standard drive
65
125
ps
3.3V supply, >66 MHz, <30 pF, high drive
53
100
ps
2.5V supply, >66 MHz, <15 pF, standard drive
35
95
ps
2.5V supply, >66 MHz, <15 pF, high drive
30
65
ps
2.5V supply, >66 MHz, <30 pF, high drive
75
145
ps
T
PER
[9,10]
Period Jitter, Peak
3.3V supply, 66100 MHz, <15 pF
20
75
ps
3.3V supply, >100 MHz, <15 pF
15
45
ps
3.3V supply, >66 MHz, <30 pF, standard drive
40
100
ps
3.3V supply, >66 MHz, <30 pF, high drive
30
70
ps
2.5V supply, >66 MHz, <15 pF, standard drive
25
60
ps
2.5V supply, 66100 MHz, <15 pF, high drive
25
60
ps
2.5V supply, >100 MHz, <15 pF, high drive
15
45
ps
Note:
10. As defined by JESD65B. Typical jitter is measured at 3.3V or 2.5V, 29C, with all outputs driven into the maximum specified load.
3.3V and 2.5V AC Electrical Specifications
(continued)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t
1
t
2
V
DD
/2
V
DD
/2
V
DD
/2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V(2.5V)
0V
0.8V(0.6V)
2.0V(1.8V)
2.0V(1.8V)
0.8V(0.6V)
t
4
Output-Output Skew
t
5
OUTPUT
OUTPUT
V
DD
/2
V
DD
/2
Input-Output Propagation Delay
V
DD
/2
t
6
INPUT
FBK
V
DD
/2
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 6 of 11
Supplemental Parametric Information
Switching Waveforms
(continued)
V
DD
/2
V
DD
/2
t
7
Any output, Part 1 or 2
Any output, Part 1 or 2
Part-Part Skew
Test Circuits
0.1
F
V DD
0.1
F
V DD
CLK
C LOAD
OUTPUTS
GND
GND
Test Circuit # 1
-1200
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
-20
-10
0
10
20
Load CLKOUT- Load CLKA/B (pF)
Standard Drive
High Drive
Figure 1. 3.3V Typical room temperature graph for REF Input to CLKA/CLKB delay versus loading difference
between CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency.
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 7 of 11
25
50
75
100
125
150
175
200
33
66
100
133
166
200
233
Frequency (MHz)
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
30pF, -45C, Standard Drive
30pF, 90C, Standard Drive
15pF, -45C, High Drive
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
Figure 2. 3.6V measured supply current versus frequency, drive strength, loading, and temperature. Note that the
30-pF data above 100 MHz is beyond the data sheet specification of 22 pF.
20
40
60
80
100
120
33
66
100
133
166
200
Frequency (MHz)
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
15pF, -45C, High Drive
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
Figure 3. 2.7V measured supply current versus frequency, drive strength, loading, and temperature. Note that
the 30-pF high-drive data above 100MHz is beyond the data sheet specification of 22 pF.
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 8 of 11
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
3 0 0
3 5 0
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
F re q u e n c y (M H z )
1 5 p F , S ta n d a rd D riv e
1 5 p F , H ig h D riv e
3 0 p F , S ta n d a rd D riv e
3 0 p F , H ig h D riv e
Figure 4. Typical 3.3V measured cycle-to-cycle jitter at 29C, versus frequency, drive strength, and loading
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
3 0 0
3 5 0
0
2 0
4 0
6 0
8 0
1 0 0
1 2 0
1 4 0
1 6 0
1 8 0
2 0 0
F r e q u e n c y ( M H z )
1 5 p F , S ta n d a r d D r iv e
1 5 p F , H ig h D r iv e
3 0 p F , H ig h D r iv e
Figure 5. Typical 2.5V measured cycle-to-cycle jitter at 29C, versus frequency, drive strength, and loading.
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
F r e q u e n c y ( M H z )
1 5 p F , S t a n d a r d D r iv e
1 5 p F , H ig h D r iv e
3 0 p F , S t a n d a r d D r iv e
3 0 p F , H ig h D r iv e
Figure 6. Typical 3.3V measured period jitter at 29C, versus frequency, drive strength, and loading.
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
0
5 0
1 0 0
1 5 0
2 0 0
2 5 0
F r e q u e n c y ( M H z )
1 5 p F , S ta n d a r d D r iv e
1 5 p F , H ig h D r iv e
3 0 p F , H ig h D r iv e
Figure 7. Typical 2.5V measured period jitter at 29C, versus frequency, drive strength, and loading.
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 9 of 11
Ordering Information
Ordering Code
Package Type
Operating Range
Lead-free
CY23EP09SXC-1
16-pin 150-mil SOIC
Commercial
CY23EP09SXC-1T
16-pin 150-mil SOIC Tape and Reel
Commercial
CY23EP09SXI-1
16-pin 150-mil SOIC
Industrial
CY23EP09SXI-1T
16-pin 150-mil SOIC Tape and Reel
Industrial
CY23EP09SXC-1H
16-pin 150-mil SOIC
Commercial
CY23EP09SXC-1HT
16-pin 150-mil SOIC Tape and Reel
Commercial
CY23EP09SXI-1H
16-pin 150-mil SOIC
Industrial
CY23EP09SXI-1HT
16-pin 150-mil SOIC Tape and Reel
Industrial
CY23EP09ZXC-1H
16-pin 4.4-mm TSSOP
Commercial
CY23EP09ZXC-1HT
16-pin 4.4-mm TSSOP Tape and Reel
Commercial
CY23EP09ZXI-1H
16-pin 4.4-mm TSSOP
Industrial
CY23EP09ZXI-1HT
16-pin 4.4-mm TSSOP Tape and Reel
Industrial
Package Drawing and Dimensions
PIN 1 ID
0~8
16 Lead (150 Mil) SOIC
1
8
9
16
SEATING PLANE
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.386[9.804]
0.393[9.982]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.016[0.406]
0.010[0.254]
X 45
0.004[0.102]
REFERENCE JEDEC MS-012
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
PACKAGE WEIGHT 0.15gms
16-Lead (150-Mil) SOIC S16
51-85068-*B
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 10 of 11
Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Drawing and Dimensions
(continued)
4.90[0.193]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
16
PIN 1 ID
6.50[0.256]
SEATING
PLANE
1
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
BSC.
5.10[0.200]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
BSC
0.25[0.010]
0-8
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
PLANE
GAUGE
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
PART #
Z16.173
STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16-lead TSSOP 4.40 MM Body Z16.173
51-85091-*A
PRELIMINARY
CY23EP09
Document #: 38-07760 Rev. *A
Page 11 of 11
Document History Page
Document Title: CY23EP09 2.5V or 3.3V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer
Document Number: 38-07760
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
345446
See ECN
RGL
New data sheet
*A
355777
See ECN
RGL
Updated part to part skew to agree with latest char results
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