MPEG Clock Generator with VCXO
CY2412
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07227 Rev. *C
Revised December 12, 2002
Features
Benefits
Integrated phase-locked loop (PLL)
Highest-performance PLL tailored for multimedia applications
Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
VCXO with analog adjust
Large 150-ppm range, better linearity
3.3V operation
Enables application compatibility
Part Number
Outputs
Input Frequency Range
Output Frequencies
VCXO Pro-
file
CY2412
3
13.5-MHz pullable crystal input per
Cypress specification
Two 27-MHz outputs, one 54-MHz output (3.3V) Linear
CY2412-3
3
13.5-MHz pullable crystal input per
Cypress specification
27 MHz, 13.5 MHz, 54 MHz (3.3V)
Linear
Logic Block Diagram
13.5 XIN
XOUT
CLKC
OUTPUT
DIVIDERS
PLL
OSC
VCXO
CLKA
Q
P
VCO
VDD
VSS
CLKB
8-pin SOIC
CY2412,-3
1
2
3
4
XOUT
XIN
VCXO
CLKA
VSS
CLKC
CLKB
5
6
7
8
VDD
Pin Configuration
CY2412
Document #: 38-07227 Rev. *C
Page 2 of 5
Pullable Crystal Specifications
Absolute Maximum Conditions
Recommended Operating Conditions
Pin Summary
Pin Name
Pin Number
Pin Description
X
IN
1
Reference Crystal Input
V
DD
2
Voltage Supply
VCXO
3
Input Analog Control for VCXO
V
SS
4
Ground
CLKA
5
54-MHz clock output
CLKB
6
27-MHz clock output (-1)
CLKB
6
13.5-MHz clock output (-3)
CLKC
7
27-MHz clock output
X
OUT
[1]
8
Reference Crystal Output
Parameter
Description
Min.
Typ.
Max.
Unit
CR
load
Crystal Load Capacitance
14
pF
C0/C1
240
ESR
Equivalent Series Resistance
35
50
T
o
Operating Temperature
0
70
C
Crystal Accuracy
Crystal Accuracy
20
ppm
TT
s
Stability over Temperature and Aging
50
ppm
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electrostatic Discharge
2
kV
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.14
3.3
3.47
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
13.5
MHz
t
PU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Notes:
1.
Float X
OUT
if X
IN
is externally driven.
2.
Rated for ten years.
CY2412
Document #: 38-07227 Rev. *C
Page 3 of 5
DC Electrical Characteristics
AC
Electrical
Char
acteristics
Note:
3.
Not 100% tested.
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
f
XO
VCXO pullability range
+150
ppm
V
VCXO
VCXO input range
0
V
DD
V
f
VBW
VCXO input bandwidth
DC to 200
kHz
I
DD
Supply Current
Sum of Core and Output Current
35
mA
Parameter
[3]
Description
Test Conditions
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
ER
Rising Edge Rate
Clock Edge Rate, Measured from 20% to 80%
of V
DD,
C
LOAD
= 15pF See figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD,
C
LOAD
= 15 pF See figure 2.
0.8
1.4
V/ns
t
9
Clock Jitter
Peak to Peak period jitter
100
200
ps
t
10
PLL Lock Time
3
ms
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4
CY2412
Document #: 38-07227 Rev. *C
Page 4 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
All products and company names mentioned in this document may be the trademarks of their respective holders.
Test Circuit
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY2412SC
S8
8-pin SOIC
Commercial
3.3V
CY2412SCT
S8
8-pin SOICTape and Reel
Commercial
3.3V
CY2412SC-3
S8
8-pin SOIC
Commercial
3.3V
CY2412SC-3T
S8
8-pin SOICTape and Reel
Commercial
3.3V
8-lead (150-mil) SOIC S8
51-85066-A
CY2412
Document #: 38-07227 Rev. *C
Page 5 of 5
Document Title: CY2412 MPEG Clock Generator with VCXO
Document Number: 38-07227
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110492
10/28/01
SZV
Change from Spec number: 38-00898 to 38-07227
*A
112457
03/14/02
CKN
Added CY2412-2 to data sheet
*B
116961
08/06/02
CKN
Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet.
*C
121879
12/12/02
RBI
Power up requirements added to Operating Conditions Information
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