PRELIMINARY
27-MHz Clock Generator with
Serial Programming Interface
CY24202
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07198 Rev. *A
Revised December 14, 2002
Features
Benefits
Integrated phase-locked loop
High-performance PLL tailored for multimedia applications
Low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
Serial Programming Interface (SPI)
Dynamic Digital VCXO control
3.3V Operation
Enables application compatibility in low power systems
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY24202
2
13.5-MHz pullable crystal input per
Cypress Specification
2 copies of 27 MHz
Logic Block Diagram
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
Q
P
VCO
VDD
VSS
CLK2
Serial
Programming
Interface
SCLK
SDAT
CLK1
Digital VCXO
8-pin SOIC
CY24202
Pin Configuration
1
2
3
4
XOUT
XIN
SDAT
SCLK
VSS
CLK2
CLK1
5
6
7
8
VDD
CY24202
PRELIMINARY
Document #: 38-07198 Rev. *A
Page 2 of 6
Notes:
1.
Float XOUT if XIN is externally driven.
2.
Rated for 10 years.
Summary
Name
Pin Number
Description
XIN
1
Reference Crystal Input
VDD
2
Voltage Supply
SDAT
3
Digital VCXO Serial Data Input
VSS
4
Ground
SCLK
5
Digital VCXO Serial Clock Input
CLK1
6
Clock Output 1 @ 27 MHz
CLK2
7
Clock Output 2 @ 27 MHz
XOUT
[1]
8
Reference Crystal Output
Pullable Crystal Specifications
Parameter
Description
Min.
Typ.
Max.
Unit
CR
load
Crystal Load Capacitance
14
pF
C0/C1
240
ESR
Equivalent Series Resistance
35
T
o
Operating Temperature
0
70
C
Crystal Accuracy
Crystal Accuracy
20
ppm
TT
s
Stability over temperature and aging
50
ppm
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electro-Static Discharge
2
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
13.5
MHz
t
PU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
CY24202
PRELIMINARY
Document #: 38-07198 Rev. *A
Page 3 of 6
Note:
3.
Not 100% tested.
Se
rial Programmable Interface Protocol
The CY24202 utilizes a 2-wire interface SDAT and SCLK that
operates up to 400 kbits/sec in Read or Write mode. The basic
Write serial format is as follows: Start Bit; 7-bit Device Address
(DA); R/
W
Bit; Slave Clock Acknowledge (ACK); 8-bit Memory
Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if
desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit, as
illustrated in Figure 1.
Data Valid
Data is valid when the Clock is HIGH, and may only be transi-
tioned when the clock is LOW as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop se-
quence, as illustrated in Figure 3.
Start Sequence
Start Frame is indicated by SDAT going LOW when SCLK is
HIGH. Every time a start signal is given the next 8-bit data
must be the device address (7 bits) and a R/
W
bit (0 for write),
followed by register address (8 bits) and register data (8 bits).
See Figure 3.
Stop Sequence
Stop Frame is indicated by SDAT going high when SCLK is
high. A Stop Frame frees the bus for writing to another part on
the same bus or writing to another random register address.
See Figure 3.
Acknowledge Pulse
During Write Mode the CY24202 will respond with an Acknowl-
edge pulse after every 8 bits. This is accomplished by pulling
the SDAT line low during the next clock cycle after the 8th bit
is shifted in.
Device Address
The 7 bit device address is 1101001.
Register Address
The 8 bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00H - FFH. As
you increase the value, the capacitance on the XIN and XOUT
pins will increase, thereby decreasing the xtal frequency.
DC Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
I
VDD
Supply Current
20
30
mA
AC
Electrical
Characteristics
(V
DD
= 3.3V
)
Parameter
[3]
Name
Description
Min
Typ
Max
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 4, 50% of VDD
45
50
55
%
t
3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of VDD
0.8
1.4
V/ns
t
4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of VDD
0.8
1.4
V/ns
t
9
Clock Jitter
Peak to Peak period jitter
175
ps
t
10
PLL Lock Time
3
ms
SDA Write
Start Signal
Device
Address
7 Bit
R/W = 0
1 Bit
8 Bit
Register
Address
Slave
1 Bit
ACK
Slave
1 Bit
ACK
8 Bit
Register
Data
Stop Signal
Slave
1 Bit
ACK
Figure 1. Data Frame Architecture
CY24202
PRELIMINARY
Document #: 38-07198 Rev. *A
Page 4 of 6
SDAT
SCLK
Data Valid
Transition
to next Bit
CLK
LOW
CLK
HIGH
VIH
VIL
t
SU
t
DH
Figure 2. Data Valid and Data Transition Periods
START
Transition
to next Bit
STOP
SDAT
SCLK
Figure 3. Start and Stop Frame
Serial Programming Interface Timing Specifications
Parameter
Description
Min.
Max.
Unit
f
SCL
Frequency of SCLK
400
kHz
Start Mode Time from SDAT LOW to SCLK LOW
0.6
s
CLK
LOW
SCLK LOW Period
1.3
s
CLK
HIGH
SCLK HIGH Period
0.6
s
t
SU
Data Transition to SCLK HIGH
100
ns
t
DH
Data Hold (SCLK LOW to Data Transition)
0
ns
Rise Time of SCLK and SDAT
300
ns
Fall Time of SCLK and SDAT
300
ns
Stop Mode Time from SCLK HIGH to SDA HIGH
0.6
s
Stop Mode to Start Mode
1.3
s
CY24202
PRELIMINARY
Document #: 38-07198 Rev. *A
Page 5 of 6
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Test Circuit
Package Diagram
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
Figure 4. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 5. Rise and Fall Time Definitions
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY24202SC
S8
8-Pin SOIC
Commercial
3.3V
8-Lead (150-Mil) SOIC S8
51-85066-A
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