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Электронный компонент: CY24210SC-3

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100-MHz Clock Generator with Spread Spectrum
CY24210
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Document #: 38-07361 Rev. *A
Revised December 5, 2002
Features
Benefits
Integrated phase-locked loop (PLL)
High-performance PLL tailored for multimedia applications
Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
Spread Spectrum
Spread Spectrum outputs for EMI reduction
3.3V operation
Enables application compatibility
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY24210
3
14.31818 MHz
Two copies of 100 MHz, 14.31818 MHz
Logic Block Diagram
XIN
XOUT
REF
OUTPUT
DIVIDERS
PLL
OSC
CLK1
Q
P
VCO
VDD
VSS
CLK2
SSON
SPREAD
SPECTRUM
8-pin SOIC
CY24210
Pin Configuration
1
2
3
4
XOUT
XIN
SSON
REF
VSS
CLK1
CLK2
5
6
7
8
VDD
Spread Spectrum Profiles
Part Numbers
Center Spread Percentage
CY24210SC-3
+ 1.875%
CY24210SC-4
+ 1.375%
CY24210SC-5
+ 2.375%
CY24210SC-6
+ 2.875%
CY24210SC-7
+ 3.375%
CY24210
Document #: 38-07361 Rev. *A
Page 2 of 5
Absolute Maximum Conditions
Recommended Operating Conditions
DC Electrical Specifications
Pin Description
Pin Name
Pin Number
Description
X
IN
1
Reference Crystal Input
V
DD
2
Voltage Supply
SSON
3
Spread Spectrum Control for CLK1, CLK2, 0 = SS off, 1 = SS on, Internal Pull-up Resistor
V
SS
4
Ground
REF
5
Buffered Reference Clock Output
CLK2
6
100-MHz Clock Output with Spread Spectrum
CLK1
7
100-MHz Clock Output with Spread Spectrum
X
OUT
[1]
8
Reference Crystal Output
Parameter
Description
Min.
Max.
Unit
V
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electrostatic Discharge
2
kV
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.14
3.3
3.47
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
14.31818
MHz
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3 V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3 V
12
24
mA
I
IH
Input High Current
V
IH
= V
DD
5
A
I
IL
Input Low Current
V
IL
= 0V
50
A
V
IH
Input High Voltage
CMOS levels, 70% of V
DD
0.7
V
DD
V
IL
Input Low Voltage
CMOS levels, 30% of V
DD
0.3
V
DD
C
IN
Input Capacitance
7
pF
I
DD
Supply Current
Sum of Core and Output Current
35
mA
R
UP
Pull-up Resistor on Input Pin
80
100
150
k
Z
OUT
Output Impedance
CLK1, CLK2, REF outputs
18.4
Notes:
1.
Float X
OUT
if X
IN
is externally driven.
2.
Rated for 10 years.
CY24210
Document #: 38-07361 Rev. *A
Page 3 of 5
AC Electrical Specifications
Test and Measurement Setup
Voltage and Timing Definitions
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is Defined in Figure 1, 50% of V
DD
45
50
55
%
t
3
Rising Edge Slew Rate
Output Clock Rise Time, 20%80% of V
DD
0.8
1.4
2
V/ns
t
4
Falling Edge Slew Rate
Output Clock Fall Time, 80%20% of V
DD
0.8
1.4
2
V/ns
t
5
Output to Output Skew
CLK1 + CLK2 Equally Loaded
200
ps
t
9
Clock Jitter
Peak to Peak Period Jitter with Spread Off
300
ps
t
10
PLL Lock Time
3
ms
Note:
3.
Not 100% tested.
0.1
F
V
DD
CLK
C
LOAD
GND
OUTPUTS
Figure 1. Duty Cycle Definition; DC = t2/t1
CLK
t1
t2
50%
50%
Figure 2. Rise and Fall Time Definitions
CLK
t3
t4
80%
20%
CY24210
Document #: 38-07361 Rev. *A
Page 4 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
All product and company names mentioned in this document may be the trademarks of their respective holders.
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY24210SC-3
S8
8-pin SOIC
Commercial
3.3V
CY24210SC-3T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
CY24210SC-4
S8
8-pin SOIC
Commercial
3.3V
CY24210SC-4T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
CY24210SC-5
S8
8-pin SOIC
Commercial
3.3V
CY24210SC-5T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
CY24210SC-6
S8
8-pin SOIC
Commercial
3.3V
CY24210SC-6T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
CY24210SC-7
S8
8-pin SOIC
Commercial
3.3V
CY24210SC-7T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
8-lead (150-Mil) SOIC S8
51-85066-*A
CY24210
Document #: 38-07361 Rev. *A
Page 5 of 5
Document History Page
Document Title: CY24210 100-MHz Clock Generator with Spread Spectrum
Document Number: 38-07361
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112458
04/04/02
CKN
New Data Sheet
*A
120234
12/05/02
CKN
Pg. 2 added Z
OUT
row to the DC Electrical Specif. table. Pg. 3 added "SC"
and Tape and Reel to all the dash numbers in the Ordering Information table.