One-PLL Clock Generator
CY26114
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07098 Rev. *A
Revised December 14, 2002
Features
Benefits
Integrated phase-locked loop
Internal PLL with up to 333 MHz internal operation
Low skew, low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
3.3V Operation with 2.5 V Output Option
Enables application compatibility
Part Number
Outputs
Input Frequency
Output Frequency Range
CY26114
4
25MHz Crystal Input
2 copies of 100MHz, 1 copy of 50MHz,
1 copy 25/33/50/66MHz (frequency selectable)
CLK4 Frequency Select Options
FS1
FS0
CLK 4
Units
0
0
25
MHz
0
1
33
MHz
1
0
50
MHz
1
1
66
MHz
Logic Block Diagram
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
100MHz
Q
P
VCO
VDDL
AVSS
AVDD
VSS
FS0
FS1
100MHz
50MHz
25/33/50/66MHz
VSSL
VDD
(frequency selectable)
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
FS1
XIN
XOUT
VDD
FS0
AVSS
N/C
CLK4
CLK3
AVDD
VDDL
N/C
Pin Configurations
LCLK1
LCLK2
CY26114
Document #: 38-07098 Rev. *A
Page 2 of 5
Absolute Maximum Conditions
Recommended Operating Conditions
Pin Definitions
Name
Pin Number
Description
XIN
1
Reference Crystal Input
V
DD
2
Voltage Supply
AV
DD
3
Analog Voltage Supply
FS0
4
Frequency Select 0
AV
SS
5
Analog Ground
V
SSL
6
LCLK Ground
LCLK1
7
100-MHz output clock at V
DDL
Level
LCLK2
8
100-MHz output clock at V
DDL
Level
N/C
9
No Connect
FS1
10
Frequency Select 1
V
DDL
11
LCLK Voltage Supply (2.5V or 3.3V)
N/C
12
No Connect
VSS
13
Ground
CLK3
14
50-MHz output clock
CLK4
15
25/33/50/66-MHz clock output (frequency selectable)
XOUT
16
Reference Crystal Output
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
V
DDL
I/O Supply Voltage
7.0
V
T
J
Junction Temperature
125
C
Digital Inputs
AV
SS
0.3
AV
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DDL
V
SS
0.3
V
DDL
+0.3
V
Electro-Static Discharge
2
kV
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.0
3.3
3.6
V
V
DDL
Operating Voltage
2.375
2.5
2.625
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
25
MHz
t
PU
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be
monotonic)
0.05
500
ms
Note:
1.
Float XOUT if XIN is externally driven.
CY26114
Document #: 38-07098 Rev. *A
Page 3 of 5
DC Electrical Characteristics
AC Electrical Characteristics
Parameter
[2]
Name
Description
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
12
24
mA
I
OH
Output High Current
V
OH
= V
DDL
0.5, V
DDL
=2.5V
8
16
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DDL
= 2.5V
8
16
mA
V
IH
Input High Voltage
CMOS levels, 70% of V
DD
0.7
VDD
V
IL
Input Low Voltage
CMOS levels, 30% of V
DD
0.3
VDD
I
VDD
Supply Current
AV
DD
/V
DD
Current
25
mA
I
VDDL
Supply Current
V
DDL
Current (V
DDL
= 3.6V)
20
mA
I
VDDL
Supply Current
V
DDL
Current (V
DDL
= 2.625V)
15
mA
Parameter
[2]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1; t1/t2, 50% of
V
DD
45
50
55
%
t
3
Rising Edge Rate
Output Clock Rise Time, 20% 80% of
V
DD
/V
DDL
= 3.3V
0.8
1.4
V/ns
t
3
Rising Edge Rate
Output Clock Rise Time, 20% 80% of
V
DDL
= 2.5V
0.6
1.2
V/ns
t
4
Falling Edge Rate
Output Clock Fall Time, 80% 20% of
V
DD
/V
DDL
= 3.3V
0.8
1.4
V/ns
t
4
Falling Edge Rate
Output Clock Fall Time, 80% 20% of
V
DDL
= 2.5V
0.6
1.2
V/ns
t5
Skew
Delay between related outputs at rising edge
250
ps
t9
Clock Jitter
Peak to Peak period jitter
200
ps
t10
PLL Lock Time
3
ms
Figure 1. Duty Cycle Definitions: DC = t2/t1.
Figure 2. Rise Time and Fall Time Definitions.
Note:
2.
Not 100% tested.
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
CY26114
Document #: 38-07098 Rev. *A
Page 4 of 5
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Test Circuit
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26114ZC
Z16
16-Pin TSSOP
Commercial
3.3V
0.1
F
V
DD
0.1
F
AV
DD
CLK out
C
LOAD
GND
OUTPUTS
CY26114
Document #: 38-07098 Rev. *A
Page 5 of 5
Document Title: CY26114 One-PLL Clock Generator
Document Number: 38-07098
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
107333
08/28/01
CKN
New Data Sheet
*A
121867
12/14/02
RBI
Power up requirements added to Operating Condi-
tions Information
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