PRELIMINARY
T1/E1 Clock Generator
CY26200
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07335 Rev. *A
Revised December 14, 2002
Features
Benefits
Integrated phase-locked loop (PLL)
High-performance PLL tailored for T1/E1 clock generation
Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
3.3V operation
Enables application compatibility
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY26200
1
19.44 MHz
1.544 MHz/2.048 MHz (selectable)
Logic Block Diagram
19.44 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
Q
P
VCO
VDD
VSS
CLK1
8-pin SOIC
CY26200
Pin Configuration
1
2
3
4
XOUT
XIN
FS
VDD
AVSS
VSS
CLK1
5
6
7
8
AVDD
AVDD
AVSS
Table 1: CY26200 Frequency Select Option
Frequency Select
CLK1
Unit
0
1.544
MHz
1
2.048
MHz
PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 2 of 5
Pin Summary
Pin Name
Pin Number Pin Description
XIN
1
19.44-MHz Reference Input
AVDD
2
Analog Voltage Supply
FS
3
Frequency Select see Table 1
AVSS
4
Analog Ground
VDD
5
Voltage Supply
CLK1
6
1.544-MHz/2.048-MHz Clock Output
VSS
7
Ground
XOUT
[1]
8
Reference Output
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs Referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electrostatic Discharge
2000
V
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
/AV
DD
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature (Commercial)
0
70
C
T
A
Ambient Temperature (Industrial)
40
+85
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
19.44
MHz
t
PU
Power-up time for all VDD's to reach
minimum specified voltage (power
ramps must be monotonic)
0.05
500
ms
DC Electrical Characteristics (Commercial)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
I
DD
Supply Current
Sum of Core and Output Current
20
mA
DC Electrical Characteristics (Industrial)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
11
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
11
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
I
DD
Supply Current
Sum of Core and Output Current
25
mA
AC Electrical Characteristics (V
DD
= 3.3V, Commercial)
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
t
3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of V
DD
0.8
1.4
V/ns
Notes:
1.
Float XOUT if XIN is externally driven
2.
Rated for 10 years
3.
Not 100% tested
PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 3 of 5
t
4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of V
DD
0.8
1.4
V/ns
t
9
Clock Jitter
Peak to Peak period jitter
200
ps
t
10
PLL Lock Time
3
ms
AC Electrical Characteristics (V
DD
= 3.3V, Industrial)
Parameter
[3]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
t
3
Rising Edge Slew Rate
Output Clock Rise Time, 20% 80% of V
DD
0.8
1.4
V/ns
t
4
Falling Edge Slew Rate
Output Clock Fall Time, 80% 20% of V
DD
0.8
1.4
V/ns
t
9
Clock Jitter
Peak to Peak period jitter
200
ps
t
10
PLL Lock Time
3
ms
AC Electrical Characteristics (V
DD
= 3.3V, Commercial) (continued)
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
Test Circuit
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26200SC
S8
8-lead SOIC
Commercial
3.3V
CY26200SI
S8
8-lead SOIC
Industrial
3.3V
0.1 mF
VDD
CLK out
C LOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 4 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
All product and company names mentioned in this document are the trademarks of their respective holders.
51-85066-A
8-lead (150-mil) SOIC S8
PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 5 of 5
Document Title: CY26200 T1/E1 Clock Generator
Document Number: 38-07335
REV.
ECN No.
Issue
Date
Orig. of
Change
Description of Change
**
111745
05/06/02
CKN
New Data Sheet
*A
121890
12/14/02
RBI
Power up requirements added to Operating Conditions Information
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