FTG for VIA PL133T and PLE133T

CY28316

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07125 Rev. **

Revised November 9, 2001

Features

· Single-chip system frequency synthesizer for VIA

PL133T and PLE133T chipsets

· Programmable clock output frequency with less than

1 MHz increment

· Integrated fail-safe Watchdog Timer for system recov-

ery

· Automatically switches to HW-selected or SW-

programmed clock frequency when Watchdog Timer
time-out occurs

· Capable of generating system RESET after a Watchdog

Timer time-out occurs or a change in output frequency
via SMBus interface

· Support SMBus byte Read/Write and block Read/Write

operations to simplify system BIOS development

· Vendor ID and Revision ID support
· Programmable drive strength for SDRAM and PCI

output clocks

· Programmable output skew for CPU, PCI, and SDRAM
· Maximized EMI Suppression using Cypress's Spread

Spectrum technology

· Available in 48-pin SSOP

Key Specifications

CPU to CPU Output Skew:.......................................... 175 ps

PCI to PCI Output Skew: ............................................. 500 ps

Block Diagram

Pin Configuration

Note:

Signals marked with `*' have internal pull-up resistors.

[1]

VDD_REF

REF0

PCI0/FS4*

XTAL

PLL Ref Freq

PLL 1

REF1/FS2*

VDD_PCI

PCI2:6

48MHz/FS0*

24_48MHz/FS1*

PLL2

÷2,3,4

OSC

VTTPWRGD#

VDD_48MHz

SMBus

SDATA

Logic

SCLK

SDRAM0:12

SDRAMIN

VDD_SDRAM

PCI1/FS3*

CPU0:1

÷2

VDD_REF

GND_REF

X1
X2

VDD_PCI

*FS4/PCI0
*FS3/PCI1

GND_PCI

PCI2
PCI3
PCI4
PCI5
PCI6

VDD_PCI

SDRAMIN

GND_SDRAM

SDRAM11
SDRAM10

VDD_SDRAM

SDRAM9
SDRAM8

GND_SDRAM

SDATA

SCLK

2831

VTT_PWRGD#
REF0
REF1/FS2*
GND_CPU
CPU0
CPU1
VDD_CPU
RST#
SDRAM_12
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
SDRAM6
SDRAM7
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

SMBus

{

Logic

Reset

RST#

CY28316

Document #: 38-07125 Rev. **

Page 2 of 20

Pin Definitions

Pin Name

Pin No.

Pin Type

Pin Description

CPU0:1

44, 43

CPU Clock Output 0 through 1: CPU clocks for processor and chipset.

PCI2:6

9, 10, 11, 12,

PCI Clock Outputs 2 through 6: 3.3V 33-MHz PCI clock outputs. Frequency
is set by FS0:4 inputs or through serial data interface.

PCI1/FS3

I/O

Fixed PCI Clock Output/Frequency Select 3: 3.3V PCI clock outputs. As an
output, frequency is set by FS0:4 inputs or through the serial data interface. This
pin also serves as a power-on strap option to determine the device operating
frequency, as described in Table 5.

PCI0/FS4

I/O

Fixed PCI Clock Output/Frequency Select 4: 3.3V PCI clock outputs. This pin
also serves as a power-on strap option to determine the device operating fre-
quency, as described in Table 5.

RST#

(open-

drain)

Reset# Output: Open drain system reset output.

48MHz/FS0

I/O

48-MHz Output/Frequency Select 0: 3.3V 48-MHz non-spread spectrum out-
put. This pin also serves as a power-on strap option to determine the device
operating frequency as described in Table 5.

24_48MHz/
FS1

I/O

24_48MHz Output/Frequency Select 1: 3.3V 24- or 48-MHz non-spread spec-
trum output. This pin also serves as a power-on strap option to determine the
device operating frequency, as described in Table 5.

REF1/FS2

I/O

Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output
clock. This pin also serves as a power-on strap option to determine the device
operating frequency as described in Table 5.

REF0

Reference Clock Output 0: 3.3V 14.318-MHz output clock.

SDRAMIN

SDRAM Buffer Input Pin: Reference input for SDRAM buffer.

SDRAM0:12

38, 37, 35,
34, 32, 31,
29, 28, 21,

20, 18, 17, 40

SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.

SCLK

Clock pin for SMBus circuitry.

SDATA

I/O

Data pin for SMBus circuitry.

Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.

Crystal Connection: An output connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.

VTT_PWRGD#

VTT_PWRGD#: 3.3V LVTTL compatible input that controls the FS0:4 to be
latched and enables all outputs. CY28316 will sample the FS0:4 inputs and
enable all clock outputs after all V

become valid and VTT_PWRGD# is held

LOW.

VDD_REF,
VDD_PCI,
VDD_SDRAM,
VDD_48MHz

1, 5, 14, 19,

27, 30, 36

Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Con-
nect to 3.3V supply.

VDD_CPU

Power Connection: Power supply for CPU outputs. Connect to 2.5V supply.

GND_REF,
GND_PCI,
GND_SDRAM,
VDD_48MHz,
VDD_CPU

2, 8, 16, 22,

33, 39, 45

Ground Connections: Connect all ground pins to the common system ground
plane.

CY28316

Document #: 38-07125 Rev. **

Page 3 of 20

Serial Data Interface

The CY28316 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions.

Data Protocol

The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from

the controller. For block Write/Read operation, the bytes must
be accessed in sequential order from lowest to highest byte,
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the sys-
tem controller can access individual indexed bytes. The offset
of the indexed byte is encoded in the command code.

The definition for the command code is defined in Table 1.

Table 1. Command Code Definition

Bit

Descriptions

0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation

6:0

Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at `0000000'.

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code 8 bits
`00000000' stands for block operation

11:18

Command Code 8 bits
`00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 0 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

...

Data Byte N/Slave Acknowledge...

39:46

Data byte from slave 8 bits

...

Data Byte N 8 bits

Acknowledge

...

Acknowledge from slave

48:55

Data byte from slave 8 bits

...

Stop

Acknowledge

...

Data bytes from slave/Acknowledge

...

Data byte N from slave 8 bits

...

Not acknowledge

...

Stop

CY28316

Document #: 38-07125 Rev. **

Page 4 of 20

Table 3. Word Read and Word Write Protocol

Word Write Protocol

Word Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

11:18

Command Code 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

Acknowledge from slave

20:27

Data byte low 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte high 8 bits

Read

Acknowledge from slave

Stop

30:37

Data byte low from slave 8 bits

Acknowledge

39:46

Data byte high from slave 8 bits

Not acknowledge

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

11:18

Command Code 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

Acknowledge from slave

20:27

Data byte 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

Stop

Read

Acknowledge from slave

30:37

Data byte from slave 8 bits

Not acknowledge

Stop

CY28316

Document #: 38-07125 Rev. **

Page 5 of 20

CY28316 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be writ-

ten to a "0" level.

3. All register bits labeled "Write with 1" must be written to "1"

during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

Spread Select1

See definition in Bit[0]

Bit 6

SEL2

See Table 5

Bit 5

SEL1

See Table 5

Bit 4

SEL0

See Table 5

Bit 3

FS_Override

0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings

Bit 2

SEL4

See Table 5

Bit 1

SEL3

See Table 5

Bit 0

Spread Select0

`00' = OFF

`01' = 0.5%

`10' = ± 0.5%

`11' = ± 0.25%

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

Latched FS4 input

Latched FS[4:0] inputs. These bits are read-only.

Bit 6

Latched FS3 input

Bit 5

Latched FS2 input

Bit 4

Latched FS1 input

Bit 3

Latched FS0 input

Bit 2

CPU0

(Active/Inactive)

Bit 1

CPU1

(Active/Inactive)

Bit 0

Vendor Test Mode

Write with `0'

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Bit 7

SDRAM12

(Active/Inactive)

Bit 6

PCI0

(Active/Inactive)

Bit 5

PCI6

(Active/Inactive)

Bit 4

PCI5

(Active/Inactive)

Bit 3

PCI4

(Active/Inactive)

Bit 2

PCI3

(Active/Inactive)

Bit 1

PCI2

(Active/Inactive)

Bit 0

PCI1

(Active/Inactive)

CY28316

Document #: 38-07125 Rev. **

Page 6 of 20

Byte 3: Control Register 3

Bit

Pin#

Name

Default

Description

Bit 7

21, 20, 18, 17

SDRAM8:11

(Active/Inactive)

Bit 6

SEL_48MHz

0 = 24 MHz
1 = 48 MHz

Bit 5

48MHz

(Active/Inactive)

Bit 4

24_48MHz

(Active/Inactive)

Bit 3

29, 28

SDRAM6:7

(Active/Inactive)

Bit 2

32, 31

SDRAM4:5

(Active/Inactive)

Bit 1

35, 34

SDRAM2:3

(Active/Inactive)

Bit 0

38, 37

SDRAM0:1

(Active/Inactive)

Byte 4: Control Register 4

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 5: Control Register 5

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

REF1

(Active/Inactive)

Bit 0

REF0

(Active/Inactive)

Byte 6: Watchdog Timer Register

Bit

Name

Default

Pin Description

Bit 7

PCI_Skew1

PCI skew control
00 = Normal
01 = 500 ps
10 = Reserved
11 = +500 ps

Bit 6

PCI_Skew0

CY28316

Document #: 38-07125 Rev. **

Page 7 of 20

Bit 5

WD_TIMER4

These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set
to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches "0," it will set the WD_TO_STATUS bit and
generate Reset if RST_EN_WD is enabled.

Bit 4

WD_TIMER3

Bit 3

WD_TIMER2

Bit 2

WD_TIMER1

Bit 1

WD_TIMER0

Bit 0

WD_PRE_
SCALER

0 = 150 ms
1 = 2.5 sec

Byte 6: Watchdog Timer Register (continued)

Bit

Name

Default

Pin Description

Byte 7: Control Register 7

Bit

Pin#

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

24_48MHz_DRV

0 = Norm, 1 = High Drive

Bit 5

48MHz_DRV

0 = Norm, 1 = High Drive

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 8: Vendor ID and Revision ID Register (Read Only)

Bit

Name

Default

Pin Description

Bit 7

Revision_ID3

Revision ID bit[3]

Bit 6

Revision_ID2

Revision ID bit[2]

Bit 5

Revision_ID1

Revision ID bit[1]

Bit 4

Revision_ID0

Revision ID bit[0]

Bit 3

Vendor_ID3

Bit[3] of Cypress Semiconductor's Vendor ID. This bit is read-only.

Bit 2

Vendor_ID2

Bit[2] of Cypress Semiconductor's Vendor ID. This bit is read-only.

Bit 1

Vendor _ID1

Bit[1] of Cypress Semiconductor's Vendor ID. This bit is read-only.

Bit 0

Vendor _ID0

Bit[0] of Cypress Semiconductor's Vendor ID. This bit is read-only.

Byte 9: System RESET and Watchdog Timer Register

Bit

Name

Default

Pin Description

Bit 7

SDRAM_DRV

SDRAM clock output drive strength
0 = Normal
1 = High Drive

Bit 6

PCI_DRV

PCI clock output drive strength
0 = Normal
1 = High Drive

Bit 5

Reserved

CY28316

Document #: 38-07125 Rev. **

Page 8 of 20

Bit 4

RST_EN_WD

This bit will enable the generation of a Reset pulse when a Watchdog Timer time-
out occurs.
0 = Disabled
1 = Enabled

Bit 3

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled

Bit 2

WD_TO_STATUS

Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)

Bit 1

WD_EN

0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency
mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note: CY28316 will generate a system Reset, reload a recovery frequency, and
lock itself into a recovery frequency mode after a Watchdog Timer time-out oc-
curs. Under recovery frequency mode, CY28316 will not respond to any attempt
to change output frequency via the SMBus control bytes. System software can
unlock CY28316 from its recovery frequency mode by clearing the WD_EN bit.

Bit 0

CPU0:1_DRV

CPU0:1 clock output drive strength
0 = Normal
1 = High Drive

Byte 9: System RESET and Watchdog Timer Register (continued)

Bit

Name

Default

Pin Description

Byte 10: Skew Control Register

Bit

Name

Default

Description

Bit 7

CPU0:1_Skew2

CPU0:1 output skew control.
000 = Normal
001 = 150 ps
010 = 300 ps
011 = 450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps

Bit 6

CPU0:1_Skew1

Bit 5

CPU0:1_Skew0

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

CY28316

Document #: 38-07125 Rev. **

Page 9 of 20

Byte 11: Recovery Frequency N-Value Register

Bit

Name

Default

Pin Description

Bit 7

ROCV_FREQ_N7

If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog Timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU and
PCI. When it is cleared, CY28316 will use the same frequency ratio stated in
the Latched FS[4:0] register. When it is set, CY28316 will use the frequency
ratio stated in the SEL[4:0] register.
CY28316 supports programmable CPU frequencies ranging from 50 MHz to
248 MHz.
CY28316 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore it is
recommended to use word or block Write to update both registers within the
same SMBus bus operation.

Bit 6

ROCV_FREQ_N6

Bit 5

ROCV_FREQ_N5

Bit 4

ROCV_FREQ_N4

Bit 3

ROCV_FREQ_N3

Bit 2

ROCV_FREQ_N2

Bit 1

ROCV_FREQ_N1

Bit 0

ROCV_FREQ_N0

Byte 12: Recovery Frequency M-Value Register

Bit

Name

Default

Pin Description

Bit 7

ROCV_FREQ_SEL

ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically
switch to the recovery CPU frequency based on the selection on
ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]

Bit 6

ROCV_FREQ_M6

If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs.
The setting of the FS_Override bit determines the frequency ratio for CPU,
SDRAM, and PCI. When it is cleared, CY28316 will use the same frequency
ratio stated in the Latched FS[4:0] register. When it is set, CY28316 will use
the frequency ratio stated in the SEL[4:0] register.
CY28316 supports programmable CPU frequencies ranging from 50 MHz to
248 MHz.
CY28316 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use word or block Write to update both registers within the same
SMBus bus operation.

Bit 5

ROCV_FREQ_M5

Bit 4

ROCV_FREQ_M4

Bit 3

ROCV_FREQ_M3

Bit 2

ROCV_FREQ_M2

Bit 1

ROCV_FREQ_M1

Bit 0

ROCV_FREQ_M0

Byte 13: Programmable Frequency Select N-Value Register

Bit

Name

Default

Pin Description

Bit 7

CPU_FSEL_N7

If Prog_Freq_EN is set, CY28316 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre-
quency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of the FS_Override bit determines the frequency ratio for CPU,
SDRAM, and PCI. When it is cleared, CY28316 will use the same frequency
ratio stated in the Latched FS[4:0] register. When it is set, CY28316 will use
the frequency ratio stated in the SEL[4:0] register.
CY28316 supports programmable CPU frequencies ranging from 50 MHz to
248 MHz.

Bit 6

CPU_FSEL_N6

Bit 5

CPU_FSEL_N5

Bit 4

CPU_FSEL_N4

Bit 3

CPU_FSEL_N3

Bit 2

CPU_FSEL_N2

Bit 1

CPU_FSEL_N1

Bit 0

CPU_FSEL_N0

CY28316

Document #: 38-07125 Rev. **

Page 10 of 20

Byte 14: Programmable Frequency Select M-Value Register

Bit

Name

Default

Description

Bit 7

Pro_Freq_EN

Programmable output frequencies enabled
0 = Disabled
1 = Enabled

Bit 6

CPU_FSEL_M6

Bit 5

CPU_FSEL_M5

Bit 4

CPU_FSEL_M4

Bit 3

CPU_FSEL_M3

Bit 2

CPU_FSEL_M2

Bit 1

CPU_FSEL_M1

Bit 0

CPU_FSEL_M0

Byte 15: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Vendor test mode

Reserved. Write with `0'

Bit 1

Vendor test mode

Test mode. Write with `1'

Bit 0

Vendor test mode

Test mode. Write with `1'

Byte 16: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

CY28316

Document #: 38-07125 Rev. **

Page 11 of 20

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

PLL Gear

Constant (G)

FS4

FS3

FS2

FS1

FS0

CPU

PCI

SEL4

SEL3

SEL2

SEL1

SEL0

200.0

33.3

48.000741

190.0

38.0

48.000741

180.0

36.0

48.000741

170.0

34.0

48.000741

166.0

33.2

48.000741

160.0

32.0

48.000741

150.0

37.5

48.000741

145.0

36.3

48.000741

140.0

35.0

48.000741

136.0

34.0

48.000741

130.0

32.5

48.000741

124.0

31.0

48.000741

67.2

33.6

48.000741

100.8

33.6

48.000741

118.0

39.3

48.000741

134.4

33.6

48.000741

67.0

33.5

48.000741

100.5

33.5

48.000741

115.0

38.3

48.000741

134.0

33.5

48.000741

66.8

33.4

48.000741

100.2

33.4

48.000741

110.0

36.7

48.000741

133.6

33.4

48.000741

105.0

35.0

48.000741

90.0

30.0

48.000741

85.0

28.3

48.000741

78.0

39.0

48.000741

66.6

33.3

48.000741

100.0

33.3

48.000741

75.0

37.5

48.000741

133.3

33.3 48.000741

CY28316

Document #: 38-07125 Rev. **

Page 12 of 20

Programmable Output Frequency, Watchdog
Timer, and Recovery Output Frequency
Functional Description

The Programmable Output Frequency feature allows users to
generate any CPU output frequency in the range of 50 MHz to
248 MHz. Cypress offers the most dynamic and the simplest
programming interface for system developers to utilize this
feature in their platforms.

The Watchdog Timer and Recovery Output Frequency fea-
tures allow users to implement a recovery mechanism when
the system hangs or gets unstable. System BIOS or other con-
trol software can enable the Watchdog Timer before it at-
tempts to make a frequency change. If the system hangs and
a Watchdog Timer time-out occurs, a system reset will be gen-
erated and a recovery frequency will be activated.

All the related registers are summarized in Table 6.

Table 6. Register Summary.

Name

Description

Pro_Freq_EN

Programmable output frequencies enabled
0 = Disabled (default)
1 = Enabled
When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If the FS_Override bit is set, the programmed value of SEL[4:0] will be used.
When it is enabled, the CPU output frequency will be determined by the programmed value of
CPUFSEL_N, CPUFSEL_M, and the PLL Gear Constant. The program value of FS_Override,
SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio
between CPU and other frequency outputs

FS_Override

When Pro_Freq_EN is cleared or disabled,
0 = Select operating frequency by FS input pins (default)
1 = Select operating frequency by SEL bits in SMBus control bytes
When Pro_Freq_EN is set or enabled,
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default)
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes

CPU_FSEL_N,
CPU_FSEL_M

When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determine the CPU output frequency. The new frequency will start to load when-
ever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-
mended to use word or block Write to update both registers within the same SMBus bus operation.
The setting of the FS_Override bit determines the frequency ratio for CPU and PCI. When FS_Override
is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When
FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus
control bytes.

ROCV_FREQ_SEL

ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]

ROCV_FREQ_N[7:0],
ROCV_FREQ_M[6:0]

When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog
Timer time-out occurs
The setting of the FS_Override bit determines the frequency ratio for CPU and SDRAM. When it is
cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used.
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block Write to update both regis-
ters within the same SMBus bus operation.

WD_EN

0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.
Note: CY28316 will generate system reset, reload a recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28316
will not respond to any attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28316 from its recovery frequency mode by clearing the WD_EN bit.

CY28316

Document #: 38-07125 Rev. **

Page 13 of 20

How to Program CPU Output Frequency?

When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:

Fcpu = G * (N+3)/(M+3)

"N" and "M" are the values programmed in Programmable Fre-
quency Select N-Value Register and M-Value Register, re-
spectively.

"G" stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 3.

The ratio of (N+3) and (M+3) needs to be greater than "1"
[(N+3)/(M+3) > 1].

Table 7 lists set of N and M values for different frequency out-
put ranges. This example uses a fixed value for the M-Value
Register and selects the CPU output frequency by changing
the value of the N-Value Register.

Table 7. Examples of N and M Value for Different CPU Frequency Range

WD_TO_STATUS

Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)

WD_TIMER[4:0]

These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog Timer reaches "0," it will set the WD_TO_STATUS bit.

WD_PRE_SCALER

0 = 150 ms
1 = 2.5 sec

RST_EN_WD

This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled
1 = Enabled

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled

Table 6. Register Summary.

Name

Description

Frequency Ranges

Gear Constants

Fixed Value for

M-Value Register

Range of N-Value Register

for Different CPU Frequency

50 MHz 129 MHz

48.00741

97255

130 MHz 248 MHz

48.00741

127245

CY28316

Document #: 38-07125 Rev. **

Page 14 of 20

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.

Parameter

Description

Rating

Unit

, V

Voltage on any pin with respect to GND

0.5 to +7.0

STG

Storage Temperature

65 to +150

°C

Ambient Temperature under Bias

55 to +125

°C

Operating Temperature

0 to +70

°C

ESD

PROT

Input ESD Protection

2 (min.)

DC Electrical Characteristics:

= 0°C to +70°C, V

DDQ3

= 3.3V ±5%

[2]

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

3.3V Supply Current

260

2.5V Supply Current

Logic Inputs

Input Low Voltage

GND 0.3

0.8

Input High Voltage

2.0

+ 0.3

Input Low Current

[3]

µA

Input High Current

[3]

µA

Clock Outputs

Output Low Voltage

= 1 mA

Output High Voltage

= 1 mA

3.1

Output Low Current

PCI

= 1.5V

110

135

REF

= 1.5V

100

48 MHz

= 1.5V

100

24 MHz

= 1.5V

100

SDRAM

= 1.5V

110

135

Output High Current

PCI

= 1.5V

110

135

REF

= 1.5V

100

48 MHz

= 1.5V

100

24 MHz

= 1.5V

100

SDRAM

= 1.5V

110

135

Notes:

All clock outputs loaded with 6" 60

transmission lines with 20-pF capacitors.

CY28316 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.

CY28316

Document #: 38-07125 Rev. **

Page 15 of 20

AC Electrical Characteristics

= 0°C to +70°C, V

DDQ3

= 3.3V±5%, f

XTL

= 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.

Notes:

X1 input threshold voltage (typical) is V

/2.

The CY28316 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. The total load placed on the
crystal is 18 pF; this includes typical stray capacitance of short PCB traces to the crystal.

X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Refer to Figure 1for K7 operation clock driver test circuit.

Crystal Oscillator

X1 Input Threshold Voltage

[4]

DDQ3

= 3.3V

1.65

LOAD

Load Capacitance, Imposed on
External Crystal

[5]

IN,X1

X1 Input Capacitance

[6]

Pin X2 unconnected

TBD

Pin Capacitance/Inductance

Input Pin Capacitance

Except X1 and X2

OUT

Output Pin Capacitance

Input Pin Inductance

DC Electrical Characteristics:

= 0°C to +70°C, V

DDQ3

= 3.3V ±5%

[2]

(continued)

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)

[7]

Parameter

Description

Test Condition/Comments

CPU = 100 MHz

CPU = 133 MHz

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Output Rise Edge Rate

1.0

4.0

1.0

4.0

V/ns

Output Fall Edge Rate

1.0

4.0

1.0

4.0

V/ns

Duty Cycle

Measured at 50% point

Jitter, Cycle to Cycle

375

Frequency Stabilization
from Power-up (cold
start)

Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.

AC Output Impedance

= V

CY28316

Document #: 38-07125 Rev. **

Page 16 of 20

PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Period

Measured on the rising edge at 1.5V

High Time

Duration of clock cycle above 2.4V

Low Time

Duration of clock cycle below 0.4V

Output Rise Edge Rate

Measured from 0.4V to 2.4V

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

V/ns

Duty Cycle

Measured on the rising and falling edges at 1.5V

Jitter, Cycle-to-Cycle

Measured on the rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.

250

Output Skew

Measured on the rising edge at 1.5V

500

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on the rising
edge at 1.5V. CPU leads PCI output.

1.5

Frequency Stabilization
from Power-up (cold
start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.

AC Output Impedance

Average value during switching transition. Used for
determining series termination value.

REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Frequency generated by the crystal oscillator

14.318

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on the rising and falling edges at 1.5V

Frequency Stabilization from
Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008

MHz

Deviation from 48 MHz

(48.008 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on the rising and falling edges at 1.5V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

CY28316

Document #: 38-07125 Rev. **

Page 17 of 20

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

24.004

MHz

Deviation from 24 MHz

(24.004 24)/24

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/34 = 24.004 MHz)

57/34

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on the rising and falling edges at 1.5V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

Ordering Information

Ordering Code

Package Name

Package Type

Operating Range

CY28316

PVC

48-pin SSOP (300 mils)

Commercial

CY28316

Document #: 38-07125 Rev. **

Page 19 of 20

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

48-Pin Small Shrink Outline Package (SSOP, 300 mils)

Summary of nominal dimensions in inches:

Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102

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