PRELIMINARY
FTG for VIA Pentium
4 Chipsets
CY28325-2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07119 Rev. *A
Revised Decemeber 27, 2002
Features
Spread Spectrum Frequency Timing Generator for VIA
Pentium
4 Chipsets
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog Timer for system
recovery
Automatically switch to hardware-selected or software-
programmed clock frequency when Watchdog Timer
time-out
Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus Byte Read/Write and Block Read/Write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable-drive strength support
Programmable-output skew support
Three copies of 66-MHz output
Power management control inputs
Available in 48-pin SSOP
CPU
AGP
PCI
REF
APIC
48M
24_48M
x 3
x 3
x 9
x 1
x 2
x 1
x 1
~
Block Diagram
Pin Configuration
[1]
VDD_REF
XTAL
PLL Ref Freq
X2
X1
VDD_PCI
OSC
SCLK
PLL 1
SMBus
Logic
VDD_48MHz
SDATA
VDD_AGP
Divider
Network
VDD_CPU (3.3V)
Stop
Clock
Control
Stop
Clock
Control
PLL2
*(FS0:4)
2
*CPU_STOP#
PD#
*PCI_STOP#
SSOP-48
REF
VTT_PWRGD#
*FS4/REF
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS3/48MHz
*FS2/24_48MHz
GND_48MHz
*FS0/PCI_F
*FS1/PCI1
*MULT_SEL1/PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*PD#
AGP0
VDD_AGP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
32
31
30
29
VDD_APIC
GND_APIC
APIC0
APIC1
GND_CPU
VDD_CPU_CS(2.5V)
CPUT_CS_F
CPUC_CS_F
CPUT_0
CPUC_0
VDD_CPU(3.3V)
IREF
GND_CPU
CPUT_1
CPUC_1
VTT_PWRGD#
CPU_STOP#*
PCI_STOP#*
RST#
SDATA
SCLK
AGP2
AGP1
GND_AGP
CY
28
32
5
-
2
*MULTSEL1
AGP0:2
PCI_F
PCI1:8
48MHz
24_48MHz
RST#
VDD_APIC
APIC0:1
CPUT_CS, CPUC_CS
VDD_CPU_CS (2.5V)
CPUT_0, CPUC_0
Note:
1.
Pins marked with [*] have internal pull-up resistors. Pins
marked with[^] have internal pull-down resistors.
PRELIMINARY
CY28325-2
Document #: 38-07119 Rev. *A
Page 2 of 19
Pin Definitions
Pin Name
Pin No.
Pin
Type Pin Description
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
5
O
Crystal Connection: Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
REF/FS4
1
I/O
Reference Clock Output/Frequency Select 4: 3.3V 14.318-MHz output. This
pin also serves as a power-on strap option to determine device operating fre-
quency as described in the Frequency Selection Table.
CPUT_0:1
CPUC_0:1
40, 39, 35, 34
O
CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial
input interface.
CPUT_CS_F
CPUC_CS_F
42, 41
O
CPU Clock Outputs for Chipset: Frequency is set by the FS0:4 inputs or
through serial input interface.
APIC0:1
46, 45
O
APIC Clock Output: APIC clock outputs running at half of PCI output frequency.
AGP 0:2
23, 26, 27
O
AGP Clock Output: 3.3V AGP clock.
PCI_F/FS0
10
I/O
Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine device operating
frequency as described in the Frequency Selection Table.
PCI1/FS1
11
I/O
PCI Output 1 /Frequency Select 1: 3.3V PCI output. This pin also serves as a
power-on strap option to determine device operating frequency as described in
the Frequency Selection Table.
PCI2/MULTSEL
1
12
I/O
PCI Output 2/Current Multiplier Selection 1: 3.3V PCI output. This pin also
serves as a power-on strap option to determine the current multiplier for the CPU
clock outputs. The MULTSEL definitions are as follows:
MULTISEL
0 = Ioh is 4 IREF
1 = Ioh is 6 IREF
PCI3:8
14, 15, 17, 18,
19, 21
O
PCI Clock Output 3 to 8: 3.3V PCI clock outputs.
48MHz/FS3
7
I/O
48-MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in the Frequency Selection Table.
24_48MHz/FS2
8
I/O
24- or 48-MHz Output/Frequency Select 2: 3.3V fixed 24- or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Frequency Selection
Table.
CPU_STOP#
32
I
CPU Output Control: 3.3V LVTTL-compatible input that disables CPUT_CS,
CPUC_CS, CPUT_0:1 and CPUC_0:1.
PCI_ST0P#
31
I
PCI Output Control: 3.3V LVTTL-compatible input that disables PCI1:8.
PD#
22
I
Power-down Control: 3.3V LVTTL-compatible input that places the device in
power down mode when held LOW.
SCLK
28
I
SMBus Clock Input: Clock pin for serial interface.
SDATA
29
I/O
SMBus Data Input: Data pin for serial interface.
RST#
30
O
(open-d
rain)
System Reset Output: Open-drain system reset output.
IREF
37
I
Current Reference for CPU output: A precision resistor is attached to this pin,
which is connected to the internal current reference.
PRELIMINARY
CY28325-2
Document #: 38-07119 Rev. *A
Page 3 of 19
VTT_PWRGD#
33
I
Power-good from Voltage Regulator Module (VRM): 3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and
MULTSEL inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
VDD_CPU_CS,
VDD_APIC
43, 48
P
2.5V Power Connection: Power supply for CPU_CS outputs buffers and APIC
output buffers. Connect to 2.5V.
VDD_REF,
VDD_48MHz,
VDD _PCI,
VDD_AGP,
VDD_CPU
2, 6, 16, 24, 38
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
GND_REF
GND_48MHz,
GND_PCI,
GND_AGP,
GND_CPU,
GND_APIC
3, 9, 13, 20, 25,
36, 44, 47
G
Ground Connection: Connect all ground pins to the common system ground
plane.
Pin Definitions
(continued)
Pin Name
Pin No.
Pin
Type Pin Description
Swing Select Functions through Hardware
MULTSEL1
Board Target
Trace/Term Z
Reference R, IREF
= VDD/(3*Rr)
Output
Current
V
OH
@ Z,
0
50
Rr = 221 1%,
IREF = 5.00 mA
IOH = 4*Iref
1.0V @ 50
0
60
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 4*Iref
1.2V @ 60
1
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 6*Iref
1.5V @ 50
1
60
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 6*Iref
1.8V @ 60
0
50
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 4*Iref
0.47V @ 50
0
60
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 4*Iref
0.56V @ 60
1
50
Rr = 475 1%,
IREF = 2.32 mA
IOH = 6*Iref
0.7V @ 50
1
60
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 6*Iref
0.84V @ 60
Swing Select Functions
MultSEL1
MultSEL0
Board Target
Trace/Term Z
Reference R, IREF =
VDD/(3*Rr)
Output
Current
V
OH
@ Z
0
0
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 4*Iref
1.0V @ 50
0
0
60
Rr = 221 1%,
IREF = 5.00
I
OH
= 4*Iref
1.2V @ 60
0
1
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 5*Iref
1.25V @ 50
PRELIMINARY
CY28325-2
Document #: 38-07119 Rev. *A
Page 4 of 19
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to it's default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code, as
described in Table 1.
The Block Write and Block Read protocol is outlined in Table
2, while Table 3 outlines the corresponding Byte Write and
Byte Read protocol.
The slave receiver address is 11010010 (D2h).
0
1
60
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 5*Iref
1.5V @ 60
1
0
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 6*Iref
1.5V @ 50
1
0
60
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 6*Iref
1.8V @ 60
1
1
50
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 7*Iref
1.75V @ 50
1
1
60
Rr = 221 1%,
IREF = 5.00 mA
I
OH
= 7*Iref
2.1V @ 60
0
0
50
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 4*Iref
0.47V @ 50
0
0
60
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 4*Iref
0.56V @ 60
0
1
50
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 5*Iref
0.58V @ 50
0
1
60
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 5*Iref
0.7V @ 60
1
0
50
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 6*Iref
0.7V @ 50
1
0
60
Rr = 475 1%,
IREF = 2.32 mA
I
OH
= 6*Iref
0.84V @ 60
1
1
50 Ohm
Rr = 475 1%,
IREF = 2.32mA
I
OH
= 7*Iref
0.81V @ 50
1
1
60 Ohm
Rr = 475 1%,
IREF = 2.32mA
I
OH
= 7*Iref
0.97V @ 60
Swing Select Functions
(continued)
MultSEL1
MultSEL0
Board Target
Trace/Term Z
Reference R, IREF =
VDD/(3*Rr)
Output
Current
V
OH
@ Z
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
6:0
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations,
these bits should be "0000000."
PRELIMINARY
CY28325-2
Document #: 38-07119 Rev. *A
Page 5 of 19
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
"00000000" stands for block operation
11:18
Command Code 8 bits
"00000000" stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29:36
Data byte 0 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 8 bits
30:37
Byte count from slave 8 bits
46
Acknowledge from slave
38
Acknowledge
...
Data byte N/Slave acknowledge...
39:46
Data byte from slave 8 bits
...
Data Byte N 8 bits
47
Acknowledge
...
Acknowledge from slave
48:55
Data byte from slave 8 bits
...
Stop
56
Acknowledge
...
Data bytes from slave/acknowledge
...
Data byte N from slave 8 bits
...
Not acknowledge
...
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
"1xxxxxxx" stands for byte operation; bit[6:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code 8 bits
"1xxxxxxx" stands for byte operation; bit[6:0] of the
command code represents the offset of the byte to
be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29
Stop
28
Read
29
Acknowledge from slave
30:37
Data byte from slave 8 bits
38
Not acknowledge
39
Stop