Universal Clock Chip for VIATMP4M/KT/KM400

DDR Systems

CY28341-2

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07471 Rev. *B

Revised April 22, 2003

Features

· Supports VIA

P4M/KM/KT/266/333/400 chipsets

· Supports Pentium

4, AthlonTM processors

· Supports two DDR DIMMS
· Supports three SDRAM DIMMS at 100 MHz
· Provides:

-- two different programmable CPU clock pairs

-- six differential SDRAM DDR pairs

-- three low-skew/-jitter AGP clocks

-- seven low-skew/-jitter PCI clocks

-- one 48M output for USB

-- one programmable 24M or 48M for SIO

· Dial-a-Frequency

and Dial-a-dB

features

· Spread Spectrum for best electromagnetic interference

(EMI) reduction

· Watchdog feature for system recovery
· SMBus-compatible for programmability
· 56-pin SSOP and TSSOP packages

Note:

Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.

Table 1. Frequency Selection Table

FS(3:0)

CPU

AGP

PCI

0000

66.80

33.40

0001

100.00

66.80

33.40

0010

120.00

60.00

30.00

0011

133.33

66.67

33.33

0100

72.00

36.00

0101

105.00

70.00

35.00

0110

160.00

64.00

32.00

0111

140.00

70.00

35.00

1000

77.00

38.50

1001

110.00

73.33

36.67

1010

180.00

60.00

30.00

1011

166.6

66.6

33.3

1100

90.00

60.00

30.00

1101

100.00

66.67

33.33

1110

200.00

66.67

33.33

1111

133.33

66.67

33.33

Block Diagram

Pin Configuration

[1]

PLL1

S2D

CONVERT

SMBus

CPUCS_T/C

VDDC

VDDI

CPU(0:1)/CPU0D_T/C

SELP4_K7#

PCI(3:6)

PCI_F

FS1

REF(0:1)

VDDR

FS0

48M

24_48M

FBOUT

DDRT(0:5)/SDRAM(0,2,4,6,8,10)

SCLK

SDATA

PD#

AGP(0:2)

VDDAGP

VDD48M

VDDD

XTAL

XOUT

XIN

FS2

PCI2

PCI1

VDDPCI

PLL2

SRESET#

/ 2

Buf_IN

REF0

FS3

MULTSEL

SELSDR_DDR

DDRC(0:5)/SDRAM(1,3,5,7,9,11)

WDEN

56 pin SSOP

VSSR

*FS0/REF0

XIN

XOUT

VDDAGP

AGP0

*SELP4_K7/AGP1

VSSAGP

AGP2

**SELSDR_DDR/PCI1

*MULTSEL/PCI2

VSSPCI

PCI3
PCI4

VDDPCI

PCI5

PCI6

VSS48M

**FS3/48M

**FS2/24_48M

VDD48M

VDD

VSS

IREF

*PD#/SRESET#

SCLK

SDATA

**FS1/PCI_F

VDDR

VTTPWRGD#/REF1

VSSC

CPUT/CPUOD_T

CPUC/CPUOD_C

VDDC
VDDI

CPUCS_T

CPUCS_C

FBOUT
BUF_IN

DDRT0/SDRAM0
DDRC0/SDRAM1
DDRT1/SDRAM2
DDRC1/SDRAM3

VDDD
VSSD

DDRT2/SDRAM4
DDRC2/SDRAM5
DDRT3/SDRAM6
DDRC3/SDRAM7

VDDD
VSSD

DDRT4/SDRAM8
DDRC4/SDRAM9
DDRT5/SDRAM10

DDRC5/SDRAM11

VSSI

CY28

341-2

8
9

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

1
2
3
4
5
6
7

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

CY28341-2

Document #: 38-07471 Rev. *B

Page 2 of 19

Pin Description

[2]

Pin Number

Pin Name

PWR

I/O

Pin Description

XIN

Oscillator Buffer Input. Connect to a crystal or to an external clock.

XOUT

VDD

Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.

FS0/REF0

VDDR

I/O
PU

Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS0 state is
latched and this pin becomes REF0, buffered copy of signal applied at XIN.
(1-2 x strength, selectable by SMBus. Default value is 1 x strength.)

VTTPWRGD#

VDDR

If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up,
VTT_PWRGD# is an input. When this input transitions to a logic low, the FS
(3:0) and MULTSEL are latched and all output clocks are enabled. After the
first high to low transition on VTT_PWRGD#, this pin is ignored and will not
effect the behavior of the device thereafter. When the VTT_PWRGD# feature
is not used, please connect this signal to ground through a 10K

resistor.

REF1

VDDR

If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin
becomes REF1 and is a buffered copy of the signal applied at XIN.

44,42,38,
36,32,30

DDRT
(0:5)/SDRAM
(0,2,4,6,8,10)

VDDD

These pins are programmable through strapping pin11, SELSDR_DDR#.
If SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are "True" copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must
be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase
with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V

43,41,37
35,31,29

DDRC
(0:5)/SDRAM
(1,3,5,7,9,11)

VDDD

These pins are programmable through strapping pin11, SELSDR_DDR#.
If SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are "Complementary" copies of signal applied at Pin45, BUF_IN. In this mode,
VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(1,3,5,7,9,11) single ended clock outputs, copies of (and in phase with)
signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.

SELP4_K7 /
AGP1

VDDAGP

I/O
PU

Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input.
When the power supply voltage crosses the input threshold voltage,
SELP4_K7 state is latched and this pin becomes AGP1 clock output.
SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode.

MULTSEL/PCI2

VDDPCI

I/O
PU

Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input.
When the power supply voltage crosses the input threshold voltage, MULTSEL
state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is
4 x IREFMULTSEL = 1, Ioh is 6 x IREF

CPUT/CPUOD_T

VDDC

3.3V CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock
Output. See Table 1

CPUC/CPUOD_C

VDDC

3.3V CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock
Output. See Table 1

48,49

CPUCS_T/C

VDDI

2.5V CPU Clock Outputs for Chipset. See Table 1.

14,15,17,18 PCI (3:6)

VDDPCI

PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1

FS1/PCI_F

VDDPCI

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS1 state is
latched and this pin becomes PCI_F clock output.

FS3/48M

VDD48M

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When
the power supply voltage crosses the input threshold voltage, FS3 state is
latched and this pin becomes 48M, a USB clock output.

Note:

PU = internal pull-up. PD = internal pull-down. Typically =250 kW (range 200 k

to 500 k

CY28341-2

Document #: 38-07471 Rev. *B

Page 3 of 19

SELSDR_DDR#/
PCI1

VDDPCI

I/O
PD

Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the
input. When the power supply voltage crosses the input threshold voltage,
SELSDR_DDR state is latched and this pin becomes PCI clock output.
SelSDR_DDR#.= 0, DDR Mode. SelSDR_DDR#.= 1, SDR Mode.

FS2/24_48M

VDD48M

I/O
PD

Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
the power supply voltage crosses the input threshold voltage, FS2 state is
latched and this pin becomes 24_48M, a SIO programmable clock output.

AGP0

VDDAGP

AGP Clock Output. Is synchronous to CPU clocks. See Table 1

AGP2

VDDAGP

AGP Clock Output. Is synchronous to CPU clocks. See Table 1

IREF

Current reference programming input for CPU buffers. A precise resistor
is attached to this pin, which is connected to the internal current reference.

SDATA

I/O

Serial Data Input. Conforms to the Phillips I2C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.

SCLK

Serial Clock Input. Conforms to the Philips I2C specification.

PD#/SRESET#

I/O
PU

Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default),
this pin becomes a SRESET# open drain output. See system reset description.
If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When
PD# is asserted low, the device enters power down mode. See power
management function.

BUF_IN

If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential
buffers. If SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.

FBOUT

If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the
signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If
SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the SDRAM(0:11) signals

VDDAGP

3.3V power supply for AGP clocks

VDDC

3.3V power supply for CPUT/C clocks

VDDPCI

3.3V power supply for PCI clocks

VDDR

3.3V power supply for REF clock

VDDI

2.5V power supply for CPUCS_T/C clocks

VDD_48M

3.3V power supply for 48M

VDD

3.3V Common power supply

34,40

VDDD

If SelSDR_DDR#.= 0, 2.5V power supply for DDR clocksIf
SelSDR_DDR#.= 1, 3.3V power supply for SDR clocks.

VSSAGP

Ground for AGP clocks

VSSPCI

Ground for PCI clocks

VSSC

Ground for CPUT/C clocks

33,39

VSSD

Ground for DDR clocks

VSS_48M

Ground for 48M clock

VSSI

Ground for ICPUCS_T/C clocks

VSSR

Ground for REF

VSS

Common Ground

Pin Description

[2]

(continued)

Pin Number

Pin Name

PWR

I/O

Pin Description

CY28341-2

Document #: 38-07471 Rev. *B

Page 4 of 19

Power Management Functions

All clocks can be individually enabled or stopped via the
two-wire control interface. All clocks are stopped in the low
state. All clocks maintain a valid high period on transitions from
running to stop and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs
will stabilize to the correct pulse widths within about 0.5 mS.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.

The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.

The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol.The slave receiver address is 11010010 (D2h).

Table 2. Command Code Definition

Bit

Description

0 = Block read or block write operation.
1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be `0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code 8-bit `00000000' stands for
block operation

11:18

Command Code 8-bit `00000000' stands for
block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 0 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

....

Data Byte N/Slave Acknowledge...

39:46

Data byte from slave 8 bits

....

Data Byte N 8 bits

Acknowledge

....

Acknowledge from slave

48:55

Data byte from slave 8 bits

....

Stop

Acknowledge

....

Data bytes from slave/Acknowledge

....

Data byte N from slave 8 bits

....

Not Acknowledge

....

Stop

CY28341-2

Document #: 38-07471 Rev. *B

Page 5 of 19

Serial Control Registers

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code 8-bit `1xxxxxxx' stands for byte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed

11:18

Command Code 8-bit `1xxxxxxx' stands for byte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

stop

Read

Acknowledge from slave

30:37

Data byte from slave 8 bits

Not Acknowledge

stop

Byte 0: Frequency Select Register

Bit

@Pup

Pin#

Name

Description

Reserved

H/W Setting

FS2

For Selecting Frequencies in Frequency Selection Table on page 1

H/W Setting

FS1

For Selecting Frequencies in Frequency Selection Table on page 1

H/W Setting

FS0

For Selecting Frequencies in Frequency Selection Table on page 1

If this bit is programmed to "1", it enables WRITE to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a "0" it enable only READ of bits (6:4,1),
which reflect the hardware setting of FS(0:3).

H/W Setting

SELSDR_DDR Only for reading the hardware setting of the SDRAM interface mode,

status of SELSDR_DDR# strapping.

H/W Setting

FS3

For Selecting frequencies in Frequency Selection Table on page 1

H/W Setting

SELP4_K7

Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.

Byte 1: CPU Clocks Register

Bit

@Pup

Pin#

Name

Description

MODE

0 = Down Spread. 1 = Center Spread. See Table 9 on page 9

SSCG

1 = Enable (default). 0 = Disable

SST1

Select spread bandwidth. See Table 9 on page 9

SST0

Select spread bandwidth. See Table 9 on page 9

48,49 CPUCS_T, CPUCS_C

1 = output enabled (running). 0 = output disabled asynchronously in a low
state.

53,52 CPUT/CPUOD_T

CPUC/CPUOD_C

1 = output enabled (running). 0 = output disable.

53,52 CPUT/C

In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,
CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when
PD# asserted LOW, CPUT and CPUC stop in High-Z.

MULT0

Only for reading the hardware setting of the Pin11 MULT0 value.

CY28341-2

Document #: 38-07471 Rev. *B

Page 6 of 19

Byte 2: PCI Clock Register

Bit

@Pup

Pin#

Name

Description

PCI_DRV

PCI clock output drive strength 0 = Low strength, 1 = High strength

PCI_F

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI6

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI5

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI4

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI3

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI2

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

PCI1

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

Byte 3: AGP/Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

24_48M

0 = pin21 output is 24 MHz. Writing a '1' into this register asynchronously
changes the frequency at pin21 to 48 MHz.

48MHz

1 = output enabled (running). 0 = output disabled asynchronously in a low

24_48M

1 = output enabled (running). 0 = output disabled asynchronously in a low

6,7,8

DASAG1

Programming these bits allow shifting skew of the AGP(0:2) signals
relative to their default value. See Table 5.

6,7,8

DASAG0

AGP2

1 = output enabled (running). 0 = output disabled asynchronously in a low

AGP1

1 = output enabled (running). 0 = output disabled asynchronously in a low

AGP0

1 = output enabled (running). 0 = output disabled asynchronously in a low

Table 5. Dial-a-Skew

AGP(0:2)

DASAG (1:0)

AGP(0:2) Skew Shift

Default

280 ps

+280 ps

+480 ps

Byte 4: Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

48M

1 = Low strength, 0 = High strength

24_48M

1 = Low strength, 0 = High strength

6,7,8

DARAG1

Programming these bits allow modifying the frequency ratio of the
AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6.

6,7,8

DARAG0

REF0

1 = output enabled (running). 0 = output disabled asynchronously in a low

REF1

1 = output enabled (running). 0 = output disabled asynchronously in a low

REF0

1 = Low strength, 0 = High strength

REF1

1 = Low strength, 0 = High strength (K7 Mode only)

Table 6. Dial-A-Ratio

AGP(0:2)

DARAG (1:0)

CU/AGP Ratio

Frequency Selection Default

2/1

2.5/1

3/1

CY28341-2

Document #: 38-07471 Rev. *B

Page 7 of 19

Byte 5: SDR/DDR Clock Register

Bit @Pup Pin#

Name

Description

BUF_IN threshold

voltage

DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN
threshold setting. 0 = 1.35V, 1 = 1.25V

FBOUT

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

29,30 DDRT/C5/SDRAM(10,1

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

31,32 DDRT/C4/SDRAM(8,9) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.

35,36 DDRT/C3/SDRAM(6,7) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.

37,38 DDRT/C2/SDRAM(4,5) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.

41,42 DDRT/C1/SDRAM(2,3) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.

43,44 DDRT/C0/SDRAM(0,1) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.

Byte 6: Watchdog Register

Bit @Pup Pin#

Name

Description

SRESET#

1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET#
signal.

Frequency Revert

This bit allows setting the Revert Frequency once the system is rebooted due to
Watchdog time out only.0 = selects frequency of existing H/W setting1 = selects
frequency of the second to last S/W setting. (the software setting prior to the one that
caused a system reboot).

WDTEST

For IMI Test - WD-Test, ALWAYS program to '0'

WD Alarm

This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system
clears the WD time stamps (WD3:0).

WD3

This bit allows the selection of the time stamp for the Watchdog timer. See Table 7

WD2

This bit allows the selection of the time stamp for the Watchdog timer. See Table 7

WD1

This bit allows the selection of the time stamp for the Watchdog timer. See Table 7

WD0

This bit allows the selection of the time stamp for the Watchdog timer. See Table 7

Table 7. Watchdog Time Stamp

WD3

WD2

WD1

WD0

FUNCTION

Off

1 second

2 seconds

3 seconds

4 seconds

5 seconds

6 seconds

7 seconds

8 seconds

9 seconds

10 seconds

11 seconds

12 seconds

13 seconds

14 seconds

15 seconds

CY28341-2

Document #: 38-07471 Rev. *B

Page 8 of 19

Dial-a-Frequency Feature

SMBus Dial-a-Frequency feature is available in this device via
Byte7 and Byte9.

P is a PLL constant that depends on the frequency selection
prior to accessing the Dial-a-Frequency feature.

Byte 7: Dial-a-Frequency Control Register N

Bit

@Pup

Pin#

Name

Description

Reserved

Reserved for device function test.

N6, MSB

These bits are for programming the PLL's internal N register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.

N0, LSB

Byte 8: Silicon Signature Register (all bits are read-only)

Bit

@Pup

Pin#

Name

Description

Revision_ID3

Revision ID bit [3]

Revision_ID2

Revision ID bit [2]

Revision_ID1

Revision ID bit [1]

Revision_ID0

Revision ID bit [0]

Vendor_ID3

Cypress's Vendor ID bit [3].

Vendor_ID2

Cypress's Vendor ID bit [2].

Vendor_ID1

Cypress's Vendor ID bit [1].

Vendor_ID0

Cypress's Vendor ID bit [0].

Byte9: Dial-A-Frequency Control Register R

Bit

@Pup

Pin#

Name

Description

Reserved

R5, MSB

These bits are for programming the PLL's internal R register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.

DAF_ENB

R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is load from DAF (SMBus) registers.

Table 8.

FS(4:0)

XXXXX

96016000

CY28341-2

Document #: 38-07471 Rev. *B

Page 9 of 19

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is enabled/disabled via SMBus register Byte
1, Bit 7.

System Self Recovery Clock Management

This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.

When the system sends an SMBus command requesting a
frequency change through Byte 4 or through bytes 13 and 14,
it must have previously sent a command to byte 12, for
selecting which time out stamp the Watchdog must perform,
otherwise the System Self Recovery feature will not be appli-
cable. Consequently, this device will change frequency and
then the Watchdog timer starts timing. Meanwhile, the system
BIOS is running its operation with the new frequency. If this
device receives a new SMBus command to clear the bits origi-
nally programmed in Byte 12, bits (3:0) (reprogram to 0000),

before the Watchdog times out, then this device will keep
operating in its normal condition with the new selected
frequency. If the Watchdog times out the first time before the
new SMBus reprograms Byte 12, bits (3:0) to (0000), then this
device will send a low system reset pulse, on SRESET# (see
byte12, bit7), and changes WD alarm (Byte12, Bit4) status to
"1" then restarts the Watchdog timer again. If the Watchdog
times out a second time, then this device will send another low
pulse on SRESET#, will relatch original hardware strapping
frequency (or second to last software selected frequency, see
byte12, bit6) selection, set WD alarm bit (Byte12, bit4) to `1,'
then start WD timer again. The above-described sequence will
keep repeating until the BIOS clears the SMBus byte12 bits
(3:0). Once the BIOS sets Byte 12 bits (3:0) = 0000, then the
Watchdog timer is turned off and the WD alarm bit (Byte 12,
bit4) is reset to `0.'

Table 9. Spread Spectrum Table

Mode

SST1

SST0

% Spread

+0.14, 1.23

+0, 1.00

+0, 0.60

+0, 0.52

+0.72, 0.71

+0.47, 0.49

+0.34, 0.33

+0.30, 0.28

Swing Select Functions Through Hardware

MULTSEL

Board Target
Trace/Term Z

Reference R,

IREF = VDD/(3*Rr)

Output Current

VOH@Z

50 Ohm

Rr = 221 1%,

IREF = 5.00mA

IOH = 4* Iref

1.0V@50

50 Ohm

Rr = 475 1%,

IREF = 2.32mA

IOH = 6* Iref

0.7V@50

CY28341-2

Document #: 38-07471 Rev. *B

Page 10 of 19

P4 Processor SELP4_K7# = 1

Power-down Assertion (P4 Mode):

When PD# is sampled low by two consecutive rising edges of
CPU# clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x
Iref, and CPU# undriven. Note that Figure 1 shows CPU =

133 MHz. This diagram and description are applicable for all
valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state
of internal logic, stopping and holding the REF clock outputs
in the LOW state may require more than one clock cycle to
complete.

S y s t e m r u n n i n g w i t h
o r i g i n a l l y s e l e c t e d
f r e q u e n c y v i a
h a r d w a r e s t r a p p i n g .

R e c e i v e F r e q u e n c y

C h a n g e R e q u e s t v i a

S M B u s B y t e 4 o r V i a D i a l -

a - f r e q u e n c y ?

S t a r t i n t e r n a l w a t c h d o g t i m e r .

W a t c h D o g t i m e o u t ?

T u r n o f f w a t c h d o g t i m e r .
K e e p n e w f r e q u e n c y s e t t i n g . S e t W D a l a r m
b i t ( b y t e 1 2 , b i t 4 ) t o ' ' 0 '

1 ) S e n d a n o t h e r 3 m S l o w p u l s e o n S R E S E T
2 ) R e l a t c h o r i g i n a l h a r d w a r e s t r a p p i n g s e l e c t i o n
f o r r e t u r n t o o r i g i n a l f r e q u e n c y s e t t i n g s .
3 ) S e t W D A l a r m b i t ( b y t e 1 2 , B i t 4 ) t o " 1 "
4 ) S t a r t W D t i m e r

F r e q u e n c y w i l l c h a n g e b u t S y s t e m S e l f
R e c o v e r y n o t a p p l i c a b l e ( n o t i m e s t a m p
s e l e c t e d a n d b y t e 1 2 , b i t ( 3 : 0 ) i s s t i l l =
" 0 0 0 0 "

N o

Y e s

N o

Y e s

S M B u s b y t e 1 2 t i m e
o u t s t a m p d i s a b l e d ?

I s S M B u s B y t e 9 , t i m e o u t

s t a m p e n a b l e d - ( b y t e 1 2 , b i t

( 3 : 0 ) 0 0 0 0 ) ?

C h a n g e t o a n e w

f r e q u e n c y

Y e s

1 ) S e n d S R E S E T
p u l s e
2 ) S e t W D b i t
( b y t e 1 2 , b i t 4 ) t o ' 1 '
3 ) S t a r t W D t i m e r

Y e s

W a t c h D o g t i m e o u t ?

N o

Y e s

S M B u s b y t e 9 t i m e o u t

s t a m p d i s a b l e d , B y t e
1 2 , b i t ( 3 : 0 ) = ( 0 0 0 0 ) ?

Y e s

N o

Figure 1. Watchdog Recovery Clock

P C I 3 3 M H z

P W R D W N #

C P U T 1 3 3 M H z

C P U T # 1 3 3 M H z

R E F 1 4 .3 1 8 M H z

U S B 4 8 M H z

S D R A M 1 3 3 M H z

D D R T 1 3 3 M H z

D D R C 1 3 3 M H z

A G P 6 6 M H z

Figure 2. Power-down Assertion Timing Waveform (in P4 mode)

CY28341-2

Document #: 38-07471 Rev. *B

Page 11 of 19

Power-down Deassertion (P4 Mode)

The power-up latency needs to less than 3 mS.

AMD K7 processor SELP4_K7# = 0

Power-down Assertion (K7 Mode):

When the PD# signal is asserted low, all clocks are disabled
to a low level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) low, the device
transitions to a shutdown (power down) mode and all power
supplies may then be removed. When PD# is sampled low by
two consecutive rising edges of CPU clock, then all affected

clocks are stopped in a low state as soon as possible. When
in power down (and before power is removed), all outputs are
synchronously stopped in a low state (see Figure 3 below), all
PLL's are shut off, and the crystal oscillator is disabled. When
the device is shutdown, the I

C function is also disabled.

P C I 3 3 M H z

P W R D W N #

C P U 1 3 3 M H z

C P U # 1 3 3 M H z

A G P 6 6 M H z

R E F 1 4 .3 1 8 M H z

U S B 4 8 M H z

< 1 .5 m s e c

S D R A M 1 3 3 M H z

D D R T 1 3 3 M H z

D D R C 1 3 3 M H z

Figure 3. Power-down Deassertion Timing Waveform (in P4 mode)

P C I 33 M H z

P W R D W N #

R E F 14 .318 M H z

U S B 48 M H z

S D R A M 133 M H z

D D R T 133M H z

D D R C 133 M H z

A G P 66 M H z

C P U O D _C 133M H z

C P U C S _C 133M H z

C P U O D _ T 133M H z

C P U C S _T 133M H z

Figure 4. Power-down Assertion Timing Waveform (in K7 mode)

CY28341-2

Document #: 38-07471 Rev. *B

Page 12 of 19

Power-down Deassertion (K7 Mode):

When deasserted PD# to high level, all clocks are enabled and
start running on the rising edge of the next full period in order
to guarantee a glitch-free operation, no partial clock pulses.

Note:

This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device
is not affected, VTT_PWRGD# is ignored.

P C I 3 3 M H z

P W R D W N #

C P U 1 3 3 M H z

C P U # 1 3 3 M H z

A G P 6 6 M H z

R E F 1 4 .3 1 8 M H z

U S B 4 8 M H z

< 1 .5 m s e c

S D R A M 1 3 3 M H z

D D R T 1 3 3 M H z

D D R C 1 3 3 M H z

Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)

VID (0:3),

SEL (0,1)

VTT_PW RGD#

PW RGD

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3m S

Delay

State 0

State 2

State 3

W ait for

VTT _GD#

Sam ple Sels

Off

State 1

(Note A)

Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)

[3]

CY28341-2

Document #: 38-07471 Rev. *B

Page 13 of 19

Connection Circuit DDRT/C Signals

For open-drain CPU output signals (with K7 processor SELP4_K7#=0)

For Differential CPU Output Signals (with P4 Processor
SELP4_K7= 1)

The following diagram shows lumped test load configurations
for the differential Host Clock outputs.

D e la y 0 .2 5 m S

S 1

P o w e r O f f

S 0

V D D A = 2 . 0 V

S a m p le

I n p u t s

F S ( 3 : 0 )

S 2

V D D 3 .3 = O f f

N o r m a l

O p e r a t io n

S 3

W a it f o r

1 .1 4 6 m s

E n a b le

O u t p u te s

Figure 7. Clock Generator Power-up/Run State Diagram (with P4 processor SELP4_K7#=1)

Figure 8. K7 Load Termination

Measurem ent Point

20 pF

680 pF

47 Ohm

150

Ohm

CPUOD_T

CPUOD_C

VDDCPU(1.5V)

500 Ohm

VDDCPU(1.5V)

500 Ohm

60.4 Ohm

301 Ohm

500 Ohm

Ohm

3.3V

Ohm

150

Ohm

VDDCPU(1.5V)

Figure 9. CS Load Termination

Table 10. Signal Loading Table

Clock Name

Max Load (in pF)

REF (0:1), 48MHz (USB), 24_48MHz

AGP(0:2), SDRAM (0:11)

PCI_F(0:5)

DDRT/C (0:5), FBOUT

CPUT/C

See Figure 10

CPUOD_T/C

See Figure 8

CPUCS_T/C

See Figure 9

CY28341-2

Document #: 38-07471 Rev. *B

Page 14 of 19

Note:

Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
length transmission line should be added to the other signal of the pair (e.g., AGP).

Table 11. Lumped Test Load Configuration

Component

0.7V Amplitude Value

1.0V Amplitude Value

tA1

, R

tA2

LA1

, R

LA2

49.9

PCB

3" 50

LB1

, R

LB2

470

tB1

, R

tB2

, C

2 pF

ref

475

w/mult0 = 1

221

w/mult0 = 0

Group Timing Relationships and Tolerances

[4]

Offset (ps)

Tolerance (ps)

Conditions

CSAGP

CPUCS to AGP

750

500

CPUCS Leads

AGP to PCI

1,250

500

AGP Leads

CLK Measurement Point

ref

tA1

CPUT

MULTSEL

CLK Measurement Point

LA1

LB1

LA2

LB2

tA2

tB1

tB2

PCB

CPUT#

Figure 10. P4 Load Termination

0ns

10ns

20ns

30ns

AGP CLOCK 66.6MHz

PCI CLOCK 33.3MHz

CPU CLOCK 66.6MHz

CPU CLOCK 100MHz

CPU CLOCK 133.3MHz

CSAGP

CY28341-2

Document #: 38-07471 Rev. *B

Page 15 of 19

Maximum Ratings

[5]

Input Voltage Relative to V

:.............................. V

0.3V

Input Voltage Relative to V

DDQ

or AV

: ............. V

+ 0.3V

Storage Temperature: ................................ 65

C to + 150

Operating Temperature: .................................... 0

C to +70

Maximum ESD .............................................................2000V

Maximum Power Supply: ................................................5.5V

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, V

and V

OUT

should be constrained to the

range:

< (V

or V

OUT

) < V

Unused inputs must always be tied to an appropriate logic
voltage level (either V

or V

DC Parameters

(

VDD=VDDPCI=VDDAGP=VDDR=VDD48M=VDDC= 3.3v±5%, VDDI = VDD=2.5±5%, TA=0°C TO +70°C)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

IL1

Input Low Voltage

Applicable to PD#, F S(0:4)

0.8

Vdc

IH1

Input High Voltage

2.0

Vdc

IL2

Input Low Voltage

Applicable to SDATA and SCLK

1.0

Vdc

IH2

Input High Voltage

2.2

Vdc

Output Low Voltage for SRESET# I

0.4

Pull-down current for SRESET#

= 0.4V

Three-state leakage Current

DD3.3V

Dynamic Supply Current

CPU frequency set at 133.3 MHz, Note 6

150

190

DD2.5V

Dynamic Supply Current

CPU frequency set at 133.3 MHz, Note 6

175

195

Power-down Supply current

PD# = 0

600

PUP

Internal Pull-up Device Current

Input @ V

PDWN

Internal Pull-down Device Current Input @ V

Input pin capacitance

OUT

Output pin capacitance

Pin Inductance

XTAL

Crystal pin capacitance

Measured from the Xin or Xout to V

AC Parameters

Parameter

Description

100 MHz

133 MHz

200 MHz

Unit

Notes

Min.

Max.

Min.

Max

Min.

Max.

XTAL
T

Xin Duty Cycle

% 7,14

PERIOD

Xin Period

69.84

71.00

69.84

71.0

69.84

71.0

ns 7,14

HIGH

Xin High Voltage

.7V

LOW

Xin Low Voltage

.3V

Xin Rise and Fall Times

10.0

ns 13

CCJ

Xin Cycle to Cycle Jitter

500

ps 8,11

Crystal Start-up Time

ms 10,12

P4 Mode CPU at 0.7V
T

CPUT/C Duty Cycle

% 7,8,9,15, 16

PERIOD

CPUT/C Period

9.85

10.2

7.35

7.65

4.85

5.1

ns 7,8,9,15, 16

Notes:

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

All outputs loaded as per maximum capacitive load table.

This parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 MHz.

All outputs loaded as per loading specified in theTable 11.

Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.

10. Probes are placed on the pins, and measurements are acquired at 0.4V.
11.

When Xin is driven from and external clock source (3.3V parameters apply).

12. When crystal meets minimum 40-ohm device series resistance specification.
13. Measured between 0.2V

and.7V

14. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock

duty cycle will not be within data sheet specifications.

15. Measured at VX, or where subtraction of CLK-CLK# crosses 0V.
16. See Figure 10 for 0.7V loading specification.

CY28341-2

Document #: 38-07471 Rev. *B

Page 16 of 19

CPUT/C Rise and Fall Times

175

700

175

700

175

700

ps 24

Rise/Fall Matching

20%

24,26

Rise/Fall Time Variation

125

ps 8,24,16

SKEW

CPUCS_T/C to CPUT/C Clock Skew

200

150

200

ps 8,18,15,16

CCJ

CPUT/C Cycle to Cycle Jitter

150

+150

150

+150

200

+200

ps 8,18,15,16

CROSS

Crossing Point Voltage at 0.7V Swing

280

430

280

430

280

430

mV 16

P4 Mode CPU at 1.0V
T

CPUT/C Duty Cycle

% 8,9,15

PERIOD

CPUT/C Period

9.85

10.2

7.35

7.65

4.85

5.1

nS 8,9,15

Differential
T

CPUT/C Rise and Fall times

175

467

175

467

175

467

ps 7,14,27

SKEW

CPUCS_T/C to CPUT/C Clock Skew

200

150

200

8,14,11

CCJ

CPUT/C Cycle to Cycle Jitter

150

+150

150

+150

200

+200

ps 8,14,11

CROSS

Crossing Point Voltage at 1V Swing

510

760

510

760

510

760

mV 27

SE-DeltaSlew Absolute Single-ended Rise/Fall

Waveform Symmetry

325

ps 26

K7 Mode
T

CPUOD_T/C Duty Cycle

% 8,9

PERIOD

CPUOD_T/C Period

9.98

10.5

7.5

8.0

5.5

ns 8,9

LOW

CPUOD_T/C Low Time

2.8

1.67

2.8

ns 8,9

CPUOD_T/C Fall Time

0.4

1.6

0.4

1.6

0.4

1.6

ns 8,13

SKEW

CPUCS_T/C to CPUT/C Clock Skew

200

150

200

8,14,11

CCJ

CPUOD_T/C Cycle-to-Cycle Jitter

150

+150

150

+150

200

+200

ps 8,9

Differential Voltage AC

Vp+.6V

Differential Crossover Voltage

500

1100

500

1100

500

1100

mV 23

CHIPSET CLOCK
T

CPUCS_T/C Duty Cycle

% 7,8,9

PERIOD

CPUCS_T/C Period

10.0

10.5

15.5

10.0

10.5

ns 7,8,9

/ T

CPUCS_T/C Rise and Fall Times

0.4

1.6

0.4

1.6

0.4

1.6

ns 7,8,13

Differential Voltage AC

Vp+.6V

Differential Crossover Voltage

0.5*V

I0.2

0.5*V

+0.2

0.5*V

I0.2

0.5*V

I+0.2

0.5*V

I0.2

0.5*V

I+0.2

AGP
T

AGP(0:2) Duty Cycle

% 7,8,9

PERIOD

AGP(0:2) Period

ns 7,8,9

HIGH

AGP(0:2) High Time

5.25

ns 8,21

LOW

AGP(0:2) Low Time

5.05

ns 8,10

/ T

AGP(0:2) Rise and Fall Times

0.4

1.6

0.4

1.6

0.4

1.6

ns 8,13

Notes:

17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and

between 20% and 80% for differential signals.

18. This measurement is applicable with Spread ON or spread OFF.
19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs.
21. The typical value of VX is expected to be 0.5*V

DDD

(or 0.5*V

DDC

for CPUCS signals) and will track the variations in the DC level of the same.

22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its comple-

mentary DDRC (and CPUCS_C) one.

23. Measured at VX between the rising edge and the following falling edge of the signal.
24. Measured from V

= 0.175V to V

= 0.525V.

25. Measurement taken from differential waveform, from 0.35V to +0.35V.
26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as "the instantaneous

difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time". This parameter is
designed for waveform symmetry.

27. Measured in absolute voltage, i.e., single-ended measurement.

AC Parameters

(continued)

Parameter

Description

100 MHz

133 MHz

200 MHz

Unit

Notes

Min.

Max.

Min.

Max

Min.

Max.

CY28341-2

Document #: 38-07471 Rev. *B

Page 17 of 19

SKEW

Any AGP to Any AGP Clock Skew

250

ps 8,14

CCJ

AGP(0:2) Cycle-to-Cycle Jitter

500

ps 8,9,14

PCI
T

PCI(_F,1:6) Duty Cycle

% 7,8,9

PERIOD

PCI(_F,1:6) Period

30.0

ns 7,8,9

HIGH

PCI(_F,1:6) High Time

12.0

ns 8,21

LOW

PCI(_F,1:6) Low Time

12.0

ns 8,10

/ T

PCI(_F,1:6) Rise and Fall Times

0.5

2.5

0.5

2.5

0.5

2.5

ns 8,13

SKEW

Any PCI to Any PCI Clock Skew

500

ps 8,14

CCJ

PCI(_F,1:6) Cycle-to-Cycle Jitter

500

ps 8,9,14

48 MHz
T

48-MHz Duty Cycle

% 7,8,9

PERIOD

48-MHz Period

20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,8,9

/ T

48-MHz Rise and Fall Times

1.0

4.0

1.0

4.0

1.0

4.0

ns 8,13

CCJ

48-MHz Cycle-to-Cycle Jitter

500

ps 8,9,14

24 MHz
T

24-MHz Duty Cycle

% 7,8,9

PERIOD

24-MHz Period

41.660

41.667

41.660 41.667 41.660 41.667

ns 7,8,9

/ T

24-MHz Rise and Fall Times

1.0

4.0

1.0

4.0

1.0

4.0

ns 8,13

CCJ

24-MHz Cycle-to-Cycle Jitter

500

ps 8,9,14

REF
T

REF Duty Cycle

% 7,8,9

PERIOD

REF Period

69.841

71.0

69.841

71.0

69.841

71.0

ns 7,8,9

/ T

REF Rise and Fall Times

1.0

4.0

1.0

4.0

1.0

4.0

ns 8,13

CCJ

REF Cycle-to-Cycle Jitter

1000

ps 8,9,14

DDR
V

Crossing Point Voltage of DDRT/C

0.5*V

0.2

0.5*V

DDD

+0.2

0.5*V

0.2

0.5*V

+0.2

0.5*V

0.2

0.5*V

+0.2

Differential Voltage Swing

0.7

VDDD +

0.6

0.7

VDDD

+ 0.6

0.7

VDDD

+ 0.6

DDRT/C(0:5) Duty Cycle

% 11

PERIOD

DDRT/C(0:5) Period

9.85

10.2

14.85

15.3

9.85

10.2

ns 11

/ T

DDRT/C(0:5) Rise/Fall Slew Rate

V/n

SKEW

DDRT/C to any DDRT/C Clock Skew

100

ps 8,14,11

CCJ

DDRT/C(0:5) Cycle-to-Cycle Jitter

±75

ps 8,14,11

HPJ

DDRT/C(0:5) Half-period Jitter

±100

ps 8,14,11

DELAY

BUF_IN to Any DDRT/C Delay

ns 8,9

SKEW

FBOUT to Any DDRT/C Skew

100

ps 8,9

STABLE

All-Clock Stabilization from Power-up

ms 22

AC Parameters

(continued)

Parameter

Description

100 MHz

133 MHz

200 MHz

Unit

Notes

Min.

Max.

Min.

Max

Min.

Max.

CY28341-2

Document #: 38-07471 Rev. *B

Page 18 of 19

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Drawing and Dimensions

Purchase of I

C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips

C Patent Rights to use these components in an I

C system, provided that the system conforms to the I

C Standard Specification

as defined by Philips. VIA is a trademark of VIA Technologies, Inc. Pentium 4 is a registered trademark of Intel Corporation. Athlon
is a trademark of AMD Corporation, Inc. Dial-a-Frequency is a registered trademark, and Dial-a-Skew, Dial-a-dB, and Dial-a-Ratio
are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of
their respective holders.

Ordering Information

Part Number

Package Type

Product Flow

CY28341OC2

56-pin Shrunk Small Outline package (SSOP)

Commercial, 0

to 70

CY28341OC2T

56-pin Shrunk Small Outline package (SSOP)Tape and Reel

Commercial, 0

to 70

CY28341ZC2

56-pin Thin Shrunk Small Outline package(TSSOP)

Commercial, 0

to 70

CY28341ZC2T

56-pin Thin Shrunk Small Outline package(TSSOP)Tape and Reel

Commercial, 0

to 70

51-85060-*B

56-pin Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

56-Lead Shrunk Small Outline Package O56

51-85062-*C

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28341ZC-2

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28341ZC-2