PRELIMINARY

FTG for Intel Pentium 4 CPU and Chipsets

CY28344

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07113, Rev. *A

Revised December 26, 2002

Features

· C

ompatible to Intel® CK-Titan and CK-408 Clock

Synthesizer/Driver Specifications

· System frequency synthesizer for Intel Brookdale (845)

and Brookdale G Pentium® 4 Chipsets

· Programmable clock output frequency with less than

1MHz increment

· Integrated fail-safe Watchdog timer for system

recovery

· Automatically switch to HW-selected or

SW-programmed clock frequency when Watchdog

timer time-out

· Capable of generating system RESET after a Watchdog

timer time-out occurs or a change in output frequency

via SMBus interface

· Support SMBus byte Read/Write and block Read/Write

operations to simplify system BIOS development

· Vendor ID and Revision ID support
· Programmable drive strength support

· Programmable output skew support

· Power management control inputs

· Available in 48-pin SSOP

CPU

3V66

PCI

REF

48M

×3

×4

×9

×1

×2

Block Diagram

VDD_REF

CPU0:2, CPU0:2#,

XTAL

PLL Ref Freq

VDD_PCI

OSC

SCLK

PLL 1

SMBus

Logic

VDD_48MHz

SDATA

VDD_3V66

Divider

Network

VDD_CPU

PLL2

FS0:4

VTTPWRGD/PD#

REF_2X

VDD_REF

X1
X2

GND_REF

^FS0/PCI_F0
^FS1/PCI_F1

VDD_PCI

GND_PCI

PCI0
PCI1
PCI2
PCI3

VDD_PCI

GND_PCI

PCI4
PCI5
PCI6

VDD_3V66

GND_3V66

3V66_1
3V66_2
3V66_3

RST#

VDD_CORE

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

28
27
26
25

32
31
30
29

REF_2X/FS2^
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
VDD_CPU
CPU2
CPU2#
MULTSEL0
IREF
GND_CPU
48MHz/FS3^
24_48MHz
VDD_48MHz
GND_48MHz
3V66_0/VCH_CLK/FS4^
VDD_3V66
GND_3V66
SCLK
SDATA
VTTPWRGD/PD#*
GND_CORE

MULTSEL0

3V66_1:3

PCI_F0:1

PCI0:6

48MHz

24_48MHz

RST#

Note:

Signals marked with "*" and "^," respectively, have internal pull-up and

pull-down resistors.

VDD_3V66

3V66_0/VCH_CLK

CY2

834

SSOP-48

Pin Configuration

[1]

PRELIMINARY

CY28344

Document #: 38-07113, Rev. *A

Page 2 of 22

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an

external reference frequency input.

Crystal Connection: Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.

REF_2X/FS2

I/O

Reference Clock/Frequency Select 2: 3.3V 14.318-MHz clock output. This pin

also serves as a power-on strap option to determine device operating frequency as
described in the Frequency Selection Table.

MULTSEL0

Current Multiplier Selection 0: 3.3V input to select the current multiplier for CPU

clock outputs. The MULTSEL0 is as follows:
MULTSEL0

0 = Ioh is 4 × IREF

1 = Ioh is 6 × IREF

CPU0:2, CPU0:2#

47, 44, 40,

46, 43,39

CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input

interface.

3V66_1:3

20, 21, 22

66MHz Clock Outputs: 3.3V 66-MHz clock.

3V66_0/VCH_CLK/F

I/O

66MHz Clock Output/Frequency Select 4: 3.3V 66-MHz or 48-MHz clock output.

The selection is determined by the control byte register. This pin also serves as a

power-on strap option to determine device operating frequency as described in the
Frequency Selection Table.

PCI_F0/FS0

I/O

Free-running PCI Output 0/Frequency Select 0: 3.3V free-running PCI output.

This pin also serves as a power-on strap option to determine device operating
frequency as described in the Frequency Selection Table.

PCI_F1/FS1

I/O

Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output.

This pin also serves as a power-on strap option to determine device operating
frequency as described in the Frequency Selection Table.

PCI0:6

9, 10, 11,

12, 15, 16,

PCI Clock Output 0 to 6: 3.3V PCI clock outputs.

48MHz/FS3

I/O

48MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum

output. This pin also serves as a power-on strap option to determine device
operating frequency as described in the Frequency Selection Table.

24_48MHz

I/O

24 or 48MHz Output: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output.

SCLK

SMBus Clock Input: Clock pin for serial interface.

SDATA

I/O

SMBus Data Input: Data pin for serial interface.

RST#

(open-

drain)

System Reset Output: Open-drain system reset output.

IREF

Current Reference for CPU output: A precision resistor is attached to this pin,

which is connected to the internal current reference.

VTT_PWRGD/PD#

Powergood from Voltage Regulator Module (VRM)/PD#: 3.3V LVTTL input.

VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and

MULTSEL0 inputs are valid and OK to be sampled (Active HIGH).

VDD_REF,

VDD _PCI,

VDD_48MHz,
VDD_3V66,

VDD_CPU

1, 7, 13, 18,

30, 33, 41,

3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output

buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.

Connect to 3.3V.

VDD_48MHz

3.3V Power Connection: 48MHz output buffers. Connect to 3.3V.

GND_PCI,

GND_48MHz,

GND_3V66,
GND_CPU,

GND_REF,

4, 8, 14, 19,

29, 32, 36,

Ground Connection: Connect all ground pins to the common system ground

plane.

PRELIMINARY

CY28344

Document #: 38-07113, Rev. *A

Page 3 of 22

VDD_CORE

3.3V Analog Power Connection: Power supply for core logic, PLL circuitry.
Connect to 3.3V.

GND_CORE

Analog Ground Connection: Ground for core logic, PLL circuitry.

Pin Definitions

(continued)

Pin Name

Pin No.

Pin

Type

Pin Description

Swing Select Functions (SW control)

SW_MULTSEL1

SW_MULTSEL0

Board Target

Trace/Term Z

Reference R, IREF

VDD/(3*Rr)

Output Current

@ Z

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 4*Iref

1.0V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 4*Iref

1.2V @ 60

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 5*Iref

1.25V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 5*Iref

1.5V @ 60

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 6*Iref

1.5V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 6*Iref

1.8V @ 60

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 7*Iref

1.75V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 7*Iref

2.1V @ 60

50 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 4*Iref

0.47V @ 50

60 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 4*Iref

0.56V @ 60

50 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 5*Iref

0.58V @ 50

60 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 5*Iref

0.7V @ 60

50 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 6*Iref

0.7V @ 50

60 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 6*Iref

0.84V @ 60

50 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 7*Iref

0.81V @ 50

60 Ohm

Rr = 475 1%,

IREF = 2.32 mA

= 7*Iref

0.97V @ 60

Swing Select Functions (HW control)

MULTSEL0

Board Target

Trace/Term Z

Reference R, IREF

VDD/(3*Rr)

Output Current

@ Z

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 4*Iref

1.0V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 4*Iref

1.2V @ 60

50 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 6*Iref

1.5V @ 50

60 Ohm

Rr = 221 1%,

IREF = 5.00 mA

= 6*Iref

1.8V @ 60

PRELIMINARY

CY28344

Document #: 38-07113, Rev. *A

Page 4 of 22

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two signal serial interface is provided. Through the Serial

Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or

disabled.
The registers associated with the Serial Data Interface

initializes to it's default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are

required. The interface can also be used during system

operation for power management functions.

Data Protocol
The clock driver serial protocol accepts byte Write, byte Read,

block Write and block Read operation from the controller. For

block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte Write and byte Read operations, the
system controller can access individual indexed bytes. The

offset of the indexed byte is encoded in the command code, as

described in Table 1.
The block Write and block Read protocol is outlined in Table 2

while Table 3 outlines the corresponding byte Write and byte
Read protocol.
The slave receiver address is 11010010 (D2h).

Table 1. Command Code Definition

Bit

Descriptions

0 = Block Read or block Write operation

1 = Byte Read or byte Write operation

6:0

Byte offset for byte Read or byte Write operation. For block Read or block Write operations,

these bits should be "0000000"

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bit

2:8

Slave address 7 bit

Write

Acknowledge from slave

11:18

Command Code 8 bit

"00000000" stands for block operation

11:18

Command Code 8 bit

"00000000" stands for block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 0 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

...

Data Byte N/Slave Acknowledge...

39:46

Data byte from slave 8 bits

...

Data Byte N 8 bits

Acknowledge

...

Acknowledge from slave

48:55

Data byte from slave 8 bits

...

Stop

Acknowledge

...

Data bytes from slave/acknowledge

...

Data byte N from slave 8 bits

...

Not acknowledge

...

Stop

PRELIMINARY

CY28344

Document #: 38-07113, Rev. *A

Page 5 of 22

Data Byte Configuration Map

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bit

2:8

Slave address 7 bit

Write

Acknowledge from slave