Differential Clock Buffer/Driver
DDR400- and DDR333-Compliant
CY28351
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07370 Rev. *B
Revised May 23, 2003
Features
Supports 333-MHz and 400-MHz DDR SDRAM
60- 200-MHz operating frequency
Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
Distributes one clock input to ten differential outputs
External feedback pin (FBIN) is used to synchronize the
outputs to the clock input
Conforms to the DDRI specification
Spread Aware for electromagnetic interference (EMI)
reduction
48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input
(CLKIN) to ten differential pairs of clock outputs (YT[0:9],
YC[0:9]) and one feedback clock output (FBOUT). The clock
outputs are individually controlled by the serial inputs SCLK
and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AV
DD
is grounded, the PLL is
turned off and bypassed for the test purposes.
The PLL in this device uses the input clock (CLKIN) and the
feedback clock (FBIN) to provide high-performance, low-skew,
low-jitter output differential clocks.
Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
YC0
YT0
VDDQ
YT1
YC1
VSS
VSS
YC2
YT2
VDD
SCLK
CLKIN
NC
VDDI
AVDD
AVSS
VSS
YC3
YT3
VDDQ
YT4
YC4
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
YC5
YT5
VDDQ
YT6
YC6
VSS
VSS
YC7
YT7
VDDQ
SDATA
NC
FBIN
VDDQ
FBOUT
NC
VSS
YC8
YT8
VDDQ
YT9
YC9
VSS
C
Y
28351
YT0
YC0
YT1
YC1
YT2
YC2
YT3
YC3
YT4
YC4
YT5
YC5
YT6
YC6
YT7
YC7
YT8
YC8
YT9
YC9
FBOUT
Serial
Interface
Logic
PLL
FBIN
CLKIN
SDATA
SCLK
AVDD
10
CY28351
Document #: 38-07370 Rev. *B
Page 2 of 8
Zero Delay Buffer
When used as a zero delay buffer, the CY28351 will likely be
in a nested clock tree application. For these applications the
CY28351 offers a clock input as a PLL reference. The
CY28351 then can lock onto the reference and translate with
near zero delay to low skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
When V
DDA
is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Pin Description
[1]
Pin Number
Pin Name
I/O
Pin Description
Electrical Characteristics
13
CLKIN
I
Clock Input.
Input
35
FBIN
I
Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
Input
3, 5, 10, 20, 22
46, 44, 39, 29, 27
YT(0:9)
O
Clock Outputs.
Differential Outputs
2, 6, 9, 19, 23
47, 43, 40, 30, 26
YC(0:9)
O
Clock Outputs.
33
FBOUT
O
Feedback Clock Output. Connect to FBIN for
normal operation. A bypass delay capacitor at this
output will control Input Reference/Output Clocks
phase relationships.
Output
12
SCLK
I
Serial Clock Input. Clocks data at SDATA into the
internal register.
Data Input for the two-line serial
bus
37
SDATA
I/O
Serial Data Input. Input data is clocked to the
internal register to enable/disable individual outputs.
This provides flexibility in power management.
Data Input and Output for the
two-line serial bus
11
VDD
2.5V Power Supply for Logic.
2.5V Nominal
4, 21, 28, 34, 38,
45
VDDQ
2.5V Power Supply for Output Clock Buffers.
2.5V Nominal
16
AVDD
2.5V Power Supply for PLL.
2.5V Nominal
15
VDDI
2.5V Power Supply for Two-line Serial Interface. 2.5V Nominal
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
VSS
Common Ground.
0.0V Ground
17
AVSS
Analog Ground.
0.0V Analog Ground
14, 32,36
NC
Not Connected.
Function Table
Input
Outputs
PLL
V
DDA
CLKIN
YT(0:9)
[2]
YC(0:9)
[2]
FBOUT
GND
L
L
H
L
BYPASSED/OFF
GND
H
H
L
H
BYPASSED/OFF
2.5V
L
L
H
L
On
2.5V
H
H
L
H
On
2.5V
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
Off
Notes:
1.
A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins
their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2.
Each output pair can be three-stated via the two-line serial interface.
CY28351
Document #: 38-07370 Rev. *B
Page 3 of 8
Power Management
The individual output enable/disable control of the CY28351
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set LOW in Byte0 and Byte1 registers. The feedback output
(FBOUT) cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial "runt" clocks.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
Command Code byte
Byte Count byte.
Byte0: Output Register 1 (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
3, 2
YT0, YC0
6
1
5, 6
YT1, YC1
5
1
10, 9
YT2, YC2
4
1
20, 19
YT3, YC3
3
1
22, 23
YT4, YC4
2
1
46, 47
YT5, YC5
1
1
44, 43
YT6, YC6
0
1
39, 40
YT7, YC7
Byte1: Output Register 2 (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
1
29, 30
YT8, YC8
6
1
27, 26
YT9, YC9
5
0
Reserved
4
0
Reserved
3
0
Reserved
2
0
Reserved
1
0
Reserved
0
0
Reserved
Byte2: Test Register 3
Bit
@Pup
Pin#
Description
7
1
0 = PLL leakage test, 1 = disable test
6
1
Reserved
5
1
Reserved
4
1
Reserved
3
1
Reserved
2
1
Reserved
1
1
Reserved
0
1
Reserved
CY28351
Document #: 38-07370 Rev. *B
Page 4 of 8
Maximum Ratings
[3]
Input Voltage Relative to V
SS
:.............................. V
SS
0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................. 65
C to +150
C
Operating Temperature: .................................... 0
C to +70
C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= V
DDA
= V
DDQ
= V
DDI
= 2.5V + 5%, T
A
= 0
C to +70
C
[4]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
SDATA , SCLK
1.0
V
V
IH
Input High Voltage
SDATA , SCLK
2.2
V
V
IL
Input Voltage Low
CLKIN, FBIN
0.4
V
V
IH
Input Voltage High
CLKIN, FBIN
2.1
V
I
IN
Input Current
V
IN
= 0V or V
IN
= V
DDQ
, CLKT, FBIN
10
10
A
I
OL
Output Low Current
V
DDQ
= 2.375V, V
OUT
= 1.2V
26
35
mA
I
OH
Output High Current
V
DDQ
= 2.375V, V
OUT
= 1V
18
32
mA
V
OL
Output Low Voltage
V
DDQ
= 2.375V, I
OL
= 12 mA
0.6
V
V
OH
Output High Voltage
V
DDQ
= 2.375V, I
OH
= 12 mA
1.7
V
V
OUT
Output Voltage Swing
[5]
1.1
V
DDQ
0.4
V
V
OC
Output Crossing Voltage
[6]
(V
DDQ
/2)
0.2
V
DDQ
/2
(V
DDQ
/2)
+ 0.2
V
I
OZ
High-Impedance Output Current
V
O
= GND or V
O
= V
DDQ
10
10
A
I
DDQ
Dynamic Supply Current
[7]
All V
DDQ
and V
DDI
, F
O
= 170 MHz
235
300
mA
ID
STAT
Static Supply Current
1
mA
I
DD
PLL Supply Current
V
DDA only
9
12
mA
C
IN
Input Pin Capacitance
4
6
pF
AC Parameters
V
DD
= V
DDQ
= 2.5V 5%, T
A
= 0
C to + 70
C
[8,9]
Parameter
Description
Condition
Min. Typ. Max. Unit
fCLK
Operating Clock Frequency
60
200 MHz
tDC
Input Clock Duty Cycle
40
60
%
tLOCK
Maximum PLL lock Time
100
s
Tr/Tf
Output Clocks Slew Rate
20% to 80% of VOD
1
2.5
V/ns
tpZL, tpZH
Output Enable Time (all outputs)
[10]
3
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
[10]
3
ns
tCCJ
Cycle to Cycle Jitter
[12]
f > 66 MHz
100
100
ps
tjit(h-per)
Half-period jitter
[12]
f > 66 MHz
100
100
ps
tPLH
LOW-to-HIGH Propagation Delay, CLKIN to YT
1.5
3.5
6
ns
tPHL
HIGH-to-LOW Propagation Delay, CLKIN to YT
1.5
3.5
6
ns
tSKEW
Any Output to Any Output Skew
[11]
100
ps
tPHASE
Phase Error
[11]
150
150
ps
tPHASEJ
Phase Error Jitter
f > 66 MHz
50
50
ps
Notes:
3.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
unused inputs must be held HIGH or LOW to prevent them from floating.
5.
For load conditions, see Figure 7.
6.
The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120
resistor. See Figure 7.
7.
All outputs switching loaded with 16 pF in 60
environment. See Figure 7.
8.
Parameters are guaranteed by design and characterization. Not 100% tested in production
9.
PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of 0.5%.
10. Refers to transition of non-inverting output.
11.
All differential input and output terminals are terminated with 120
/16 pF, as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
CY28351
Document #: 38-07370 Rev. *B
Page 5 of 8
Parameter Measurement Information
t
(
)
n =
n =N
t
(
)
n
(N is large number of samples)
1
t
(
)
n
t
(
)
n+1
CLKIN
FBIN
1.25V
1.25V
1.25V
1.25V
Figure 1. Static Phase Offset
td(
)
td(
)
t(
)
t(
)
td(
)
td(
)
CLKIN
FBIN
1.25V
1.25V
Figure 2. Dynamic Phase Offset
YT[0:9], FBOUT
tsk(o)
YC[0:9]
YT[0:9], FBOUT
YC[0:9]
Figure 3. Output Skew
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