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Universal Single Chip Clock Solution for SiS658 Pentium

CY28373

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07460 Rev. *A

Revised December 18, 2002

Features

· Supports SiS658 Pentium

4 chipsets

· Supports Pentium

4 processor

· Provides:

-- 4 Differential programmable CPU clock pairs

-- 2 MREF clocks for DMCG

-- 2 ZCLK for MuTIOL

-- 2 Low-skew/jitter AGP clocks

-- 8 Low-skew/jitter PCI clocks

-- 2 Low-skew/jitter fixed PCI clocks

-- 1 48M output for USB

-- 1 Programmable 24M or 48M for SIO

-- 2 REF 14.318 MHz

· Dial-a-Frequency

and Dial-a-dB

features

· Spread spectrum for best EMI reduction
· SMBus compatible for programmability
· 56-pin SSOP package

Note:

Pins marked with [*] have 200-K

internal pull-up resistors. Pins marked with [**] have 200-K

internal pull-down resistors

Block Diagram

Pin Configuration

[1]

*MULSEL/REF0

VSSREF

**FS2/REF1

VDDREF

XIN

XOUT

VSSPCI

**FS4/PCI_F0

VSSPCI

PCI0
PCI1
PCI2

VDDPCI

VSSPCI

PCI3

PCI4

PCI5

VDDPCI

PCI6/*PCI_STP#

PCI7/*CPU_STP#

SDATA

VSS48

**FS0/48M

**FS1/24_48M

VDD48

*VTT_PWRGD/*PD#

VDDPCI

MREF

VDDMREF

MREF_B
VSSMREF
SCLK
CPUT3
CPUC3

CPUT2

VDDCPU

VSSCPU
CPUT1
CPUC1

VDDCPU

CPUT0
CPUC0
VSSCPU
IREF
VDDA
VSSA
VDDAGP
AGP1
AGP0
VSSAGP
VDDZ
ZCLK1
ZCLK0/*MODE
VSSZ

CPUC2

CY28

8
9

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

1
2
3
4
5
6
7

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

**FS3/PCI_F1

PLL1

PLL2

PwrDn

Logic

XIN

XOUT

CPU_STP#

IREF

FS(0:4)

MULSEL

VTTPWRGD

PCI_STP#

PD#

SDATA

SCLK

48M_24M

48M

PCI_F(0:1)

PCI(0:7)

ZCLK(0:1)

AGP(0:1)

CPUC(0:3)

CPUT(0:3)

REF(0:1)

I2C

Logic

Power

Latch

MREF/
MREFB

CY28373

Document #: 38-07460 Rev. *A

Page 2 of 20

Pin Description

Pin

Name

PWR

I/O

Description

XIN

VDD

Oscillator Buffer Input. Connect to a crystal or to an external
clock.

XOUT

VDD

Oscillator Buffer Output. Connect to a crystal. Do not connect
when an external clock is applied at XIN.

MULSEL/REF0

VDD

I/O
PU

200K

Power-on Bidirectional Input/Output. At power-up, MULSEL
is an input. When the power supply voltage crosses the input
threshold voltage, the MULSEL state is latched and this pin
becomes REF0, which is a buffered copy of signal applied at
XIN. When Byte 12, bit 1 = 1 (default), REF0 is normal strength.
When Byte 12 bit 1 = 0, REF0 is high strength. When MULSEL
= 0, Ioh is 4 x IREF, When MULSEL = 1, Ioh is 6 x IREF.

FS2/REF1

VDD

I/O
PD

200K

Power-on Bidirectional Input/Output. At power-up, FS2 is the
input. When the power supply voltage crosses the input
threshold voltage, the FS2 state is latched and this pin becomes
When Byte 12, bit 0 = 1 (default), REF1 is normal strength.
When Byte 12 bit 0= 0, REF1 is high strength.

VTTPWRGD VDD

200K

When Byte 9 bit 7 = 0, this pin becomes a VTT_PWRGD/PD#
input. When this input is sampled HIGH when VDD transitions
beyond the threshold voltage, the FS(4:0) and MULSEL are
latched. After the first high observance any other transitions are
ignore.

PD# VDD

200K

When Byte 9 bit 7 = 1, this pin becomes a PD# input with an
internal pull-up. When PD# is asserted LOW, the device enters
power-down mode. See power management function.

42, 45, 48, 51 CPUT(0:3)

VDDCPU

True Clocks of the Differential CPU outputs.

41, 44, 47, 50 CPUC(0:3)

VDDCPU

Complementary Clocks of the Differential CPU outputs.

12, 13, 14,
17,18, 19

PCI(0:5)

VDDPCI

PCI Clock Outputs.

ZCLK0/MODE

VDDZ

I/O

200K

Power-on Bidirectional Input/Output. At power-up, MODE is
an input. When the power supply voltage crosses the input
threshold voltage, the MODE state is latched and this pin
becomes ZCLK0. When MODE = 1, pin21 is PCI6 and pin 22 is
PCI7. When MODE = 0, pin 21 is PCI_STP# and pin 22 is
CPU_STP#.

ZCLK1

VDDZ

MuTIOL Clock Output.

PCI7

VDDPCI

When MODE = 1, this pin becomes a PCI clock output.

CPU_STP#

VDDPCI

200K

When MODE = 0, this pin becomes a CPU Clock Disable Input.
When asserted LOW, CPUT(0:3) clocks are synchronously
disabled in a HIGH state and CPUC(0:3) clocks are synchro-
nously disabled in a LOW state.

PCI6

VDDPCI

When MODE = 1, this pin becomes a PCI clock output.

PCI_STP#

VDDPCI

200K

When MODE = 0, this pin becomes a PCI Clock Disable Input.
When PCI_STP# is asserted LOW, PCI (0:7) clocks are
synchronously disabled in a LOW state. This pin does not affect
PCI_F (0:1) if they are programmed to be Free-running clocks
via the device's SMBus interface.

FS4/PCI_F0

VDDPCI

I/O

200K

Power-on Bidirectional Input/Output. At power-up, FS4 is an
input. When the power supply voltage crosses the input
threshold voltage, the FS4 state is latched and this pin becomes
PCI_F0 clock output.

CY28373

Document #: 38-07460 Rev. *A

Page 3 of 20

FS3/PCI_F1

VDDPCI

I/O

200K

Power-on Bidirectional Input/Output. At power-up, FS3 is an
input. When the power supply voltage crosses the input
threshold voltage, the FS3 state is latched and this pin becomes
PCI_F1 clock output.

FS0/48M

VDD48M

I/O
PD

200K

Power-on Bidirectional Input/Output. At power-up, FS0 is an
input. When the power supply voltage crosses the input
threshold voltage, the FS0 state is latched and this pin becomes
48M, a USB clock output.

FS1/24_48M

VDD48M

I/O
PD

200K

Power-on Bidirectional Input/Output. At power-up, FS1 is an
input. When the power supply voltage crosses the input
threshold voltage, the FS1 state is latched and this pin becomes
24_48M, a SIO programmable clock output.

34,35

AGP(0:1)

VDDAGP

AGP Clock Outputs.

IREF

This pin establishes the reference current for the host clocks.

MREF_B

VDDMREF

DMCG Clock Output.

MREF

VDDMREF

DMCG Clock Output.

SDATA

VDD

I/O

Serial Data Input. Conforms to the SMBus specification of a
Slave Receive/Transmit device. It is an input when receiving
data. It is an open drain output when acknowledging or trans-
mitting data.

SCLK

VDD

Serial Clock Input. Conforms to the SMBus specification.

VDD48

3.3V Power Supply for 48-/24-MHz Clocks

10, 15, 20

VDDPCI

3.3V Power Supply for PCI Clocks

VDDAGP

3.3V Power Supply for AGP Clocks

43, 49

VDDCPU

3.3V Power Supply for CPU Clocks

VDDA

3.3V Power Supply for Analog Circuitry

VDDMREF

3.3V Power Supply for MREF Clocks

VDDZ

3.3V Power Supply for ZCLK Clocks

VDDREF

3.3V Power Supply for REF Clocks

VSS48

Ground for 48-/24-MHz Clocks

7, 11, 16

VSSPCI

Ground for PCI Clocks

VSSAGP

Ground for AGP Clocks

40, 46

VSSCPU

Ground for CPU Clocks

VSSA

Ground for Analog Circuitry

VSSMREF

Ground for MREF Clocks

VSSZ

Ground for ZCLK Clocks

VSSREF

Ground for REF Clocks

Pin Description

(continued)

Pin

Name

PWR

I/O

Description

CY28373

Document #: 38-07460 Rev. *A

Page 4 of 20

Table 1. Frequency Selection Table

FS(4:0)

CPU (MHz)

MREF (MHz)

ZCLK (MHz)

AGP (MHz)

PCI (MHz)

VCO (MHz)

00000

100.0

66.7

33.3

400.0

00001

100.0

66.7

80.0

66.7

33.3

400.0

00010

105.0

75.0

131.3

65.6

32.8

525.0

00011

100.0

66.7

133.3

66.7

33.3

400.0

00100

133.3

66.7

33.3

400.0

00101

133.3

66.7

80.0

66.7

33.3

400.0

00110

133.3

66.7

100.0

33.3

400.0

00111

133.3

66.7

133.3

66.7

33.3

400.0

01000

166.7

66.7

33.3

666.7

01001

166.7

66.7

83.3

66.7

33.3

666.7

01010

166.7

66.7

111.1

66.7

33.3

666.7

01011

166.7

66.7

133.3

66.7

33.3

666.7

01100

200.0

66.7

33.3

400.0

01101

200.0

66.7

80.0

66.7

33.3

400.0

01110

200.0

66.7

100.0

66.7

33.3

400.0

01111

200.0

66.7

133.3

66.7

33.3

400.0

10000

66.7

33.3

66.7

50.0

33.3

400.0

10001

105.0

84.0

140.0

70.0

35.0

420.0

10010

110.0

82.5

132.0

66.0

33.0

660.0

10011

100.0

80.0

133.3

66.7

33.3

400.0

10100

138.0

82.8

138.0

69.0

34.5

414.0

10101

142.0

85.2

142.0

71.0

35.5

426.0

10110

150.0

75.0

150.0

60.0

30.0

600.0

10111

133.3

80.0

133.3

66.7

33.3

400.0

11000

166.7

83.3

66.7

33.3

666.7

11001

166.7

83.3

66.7

33.3

666.7

11010

166.7

71.4

125.0

62.5

31.3

500.0

11011

166.7

83.3

133.3

66.7

33.3

666.7

11100

200.0

80.0

66.7

33.3

400.0

11101

200.0

80.0

66.7

33.3

400.0

11110

200.0

80.0

100.0

66.7

33.3

400.0

11111

200.0

80.0

133.3

66.7

33.3

400.0

Table 2. Swing Select Functions Through Hardware

MULSEL

Board Target Trace/Term Z

Reference R,IREF = VDD/(3*Rr)

Output Current

VOH@Z

50 Ohm

Rr = 221 1%, IREF = 5.00 mA

IOH = 4* Iref

1.0V@50

50 Ohm

Rr = 475 1%, IREF = 2.32 mA

IOH = 6* Iref

0.7V@50

CY28373

Document #: 38-07460 Rev. *A

Page 5 of 20

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
ize to their default setting upon power-up, and therefore use of
this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.

Data Protocol

The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operations from the controller.
For Block Write/Read operation, the bytes must be accessed
in sequential order from lowest to highest byte (most signifi-
cant bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individually indexed bytes.
The offset of the indexed byte is encoded in the command
code, as described in Table 3.

The Block Write and Block Read protocol is outlined in Table
4 while Table 5 outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).

Table 3. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 bits
'00000000' stands for block operation

11:18

Command Code 8 bits
'00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 1 8 bits

Read = 1

Acknowledge from slave

38:45

Data byte 2 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

....

......................

39:46

Data byte from slave 8 bits

....

Data Byte (N1) 8 bits

Acknowledge

....

Acknowledge from slave

48:55

Data byte from slave 8 bits

....

Data Byte N 8 bits

Acknowledge

....

Acknowledge from slave

....

Data bytes from slave/Acknowledge

....

Stop

....

Data byte N from slave 8 bits

....

Not Acknowledge

....

Stop

CY28373

Document #: 38-07460 Rev. *A

Page 6 of 20

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed

11:18

Command Code 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed

Acknowledge from slave

20:27

Data byte from master 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

Stop

Read = 1

Acknowledge from slave

30:37

Data byte from slave 8 bits

Not Acknowledge

Stop

Byte 4: Frequency Select Register

Bit

@Pup

Pin#

Name

Description

FSELECT

0 = Frequency selected by HW latched inputs. 1 = Frequency selected
by Byte 4, bits (4:0)

Spread Enable

0 = No spread, 1 = Spread spectrum enable

Reserved, set = 0

FS4

Software Frequency Select (4:0)

FS3

FS2

FS1

FS0

Byte 5: Clock Register

Bit

@Pup

Pin#

Name

Description

Reserved, set = 0

Master Output

Control

0 = Running, 1 = Three-state all outputs

MULSEL

MULSEL latched read back

FS4

FS(4:0) hardware latched read back

FS3

FS2

FS1

FS0

CY28373

Document #: 38-07460 Rev. *A

Page 7 of 20

Byte 6: CPU Clock Control Register

Bit

@Pup

Pin#

Name

Description

PCI_F0

0 = Free running, 1 = Stop when the PCI_STP# is LOW.

PCI_F1

0 = Free running, 1 = Stop when the PCI_STP# is LOW.

42, 41

CPU0T/C

0 = Free running, 1 = Stop when the CPU_STP# is LOW.

45, 44

CPU1T/C

0 = Free running, 1 = Stop when the CPU_STP# is LOW.

48, 47
51, 50

CPU2T/C
CPU3T/C

0 = Free running, 1 = Stop when the CPU_STP# is LOW.

48, 47
51, 50

CPU2T/C
CPU3T/C

1 = Running, 0 = Three-state.

45, 44

CPU1T/C

1 = Running, 0 = Three-state.

42, 41

CPU0T/C

1 = Running, 0 = Three-state.

Byte 7: PCI Clock Control Register

Bit

@Pup

Pin#

Name

Description

PCI_F1

1 = Running, 0 = Stopped LOW.

PCI_F0

1 = Running, 0 = Stopped LOW.

PCI5

1 = Running, 0 = Stopped LOW.

PCI4

1 = Running, 0 = Stopped LOW.

PCI3

1 = Running, 0 = Stopped LOW.

PCI2

1 = Running, 0 = Stopped LOW.

PCI1

1 = Running, 0 = Stopped LOW.

PCI0

1 = Running, 0 = Stopped LOW.

Byte 8: Vendor/Device ID Register (all bits are read only)

Bit

@Pup

Name

Description

Vender_ID3

Cypress Semiconductor's Vendor ID bit [3].

Vender_ID2

Cypress Semiconductor's Vendor ID bit [2].

Vender_ID1

Cypress Semiconductor's Vendor ID bit [1].

Vender_ID0

Cypress Semiconductor's Vendor ID bit [0].

Revision_ID3

Revision ID bit [3]

Revision_ID2

Revision ID bit [2]

Revision_ID1

Revision ID bit [1]

Revision_ID0

Revision ID bit [0]

CY28373

Document #: 38-07460 Rev. *A

Page 8 of 20

Byte 9: Peripheral Clock Control Register

Bit

@Pup

Pin#

Name

Description

1 = VTT_PWRGD; 0 = 28 is PD#

Reserved, set = 0

48M

1 = Running, 0 = Stopped LOW.

24_48M

1 = Running, 0 = Stopped LOW.

24_48M

Select 24_48M 0 = 24 MHz, 1 = 48 MHz

55,54

MREF,MREF_B MREF and MREF_B output multiplexer. 0: MREF = MREFB = from frequency

table Table 1, 1: MREF = from frequency table Table 1 and MREFB = 66.6 MHz.

MREF_B

1 = Running, 0 = Stopped LOW.

MREF

1 = Running, 0 = Stopped LOW.

Byte 10: AGP/REF/ZCLK Clock Control Register

Bit

@Pup

Pin#

Name

Description

PCI6

1 = Running, 0 = Stopped LOW.

PCI7

1 = Running, 0 = Stopped LOW.

REF1

1 = Running, 0 = Stopped LOW.

REF0

1 = Running, 0 = Stopped LOW.

ZCLK1

1 = Running, 0 = Stopped LOW.

ZCLK0

1 = Running, 0 = Stopped LOW.

AGP1

1 = Running, 0 = Stopped LOW.

AGP0

1 = Running, 0 = Stopped LOW.

Byte 11: AGP Ratio/Skew Control Register

Bit

@Pup

Pin#

Name

Description

PCI_DRV

PCI clock output drive strength: 0 = Low drive, 1 = High drive.

SSMODE

0 = Down Spread. 1 = Center Spread. See Table 6

SST1

Select spread bandwidth. See Table 6

SST0

Select spread bandwidth. See Table 6

34, 35

DASAG1

Programming these bits allow shifting skew of the AGP(0:2)
signals relative to their default value. See Table 7.

DASAG0

DARAG1

Programming these bits allow modifying the frequency ratio of
the AGP clocks relative to the VCO frequency. See Table 8.

DARAG0

Table 6. Spread Spectrum Table

Mode

SST1

SST0

% Spread

1.5%

1.0%

0.75%

0.5%

±0.75%

±0.5%

±0.35%

±0.25%

Table 7. Dial-a-SkewTM AGP(0:1)

DASAG(1:0)

AGP(0:1) Skew Shift

Default

280 ps

+280 ps

+480 ps

Table 8. Dial-A-RatioTM AGP(0:1)

DARAG(1:0)

VCO/AGP Ratio

Frequency Selection Default

CY28373

Document #: 38-07460 Rev. *A

Page 9 of 20

Byte 12: Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

48M

1= Low drive, 0 = High drive

24_48M

1= Low drive, 0 = High drive

Reserved, set = 0

34, 35

DARZCLK2

Programming these bits allow modifying the frequency ratio of the
ZCLK clocks relative to the VCO frequency. See Table 9.

DARZCLK1

DARZCLK0

REF0

1= Low drive, 0 = High drive

REF1

1= Low drive, 0 = High drive

Table 9. Dial-A-Ratio ZCLK(0:1)

DARZCLK(2:0)

VCO/ZCLK Ratio

000

Frequency Selection Default

001

010

011

100

101

110

111

Byte 13: Dial-a-Frequency Control Register N

Bit

@Pup

Name

Description

Reserved

Reserved, set = 0. 1 = Test mode.

N6, MSB

These bits are for programming the PLL's internal N register. This access allows the user
to modify the CPU frequency at very high resolution (accuracy). All other synchronous
clocks (clocks that are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.

N0, LSB

Byte 14: Dial-A-Frequency Control Register R

Bit

@Pup

Name

Description

Reserved

Reserved, set = 0

R5, MSB

These bits are for programming the PLL's internal R register. This access allows the user
to modify the CPU frequency at very high resolution (accuracy). All other synchronous
clocks (clocks that are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.

DAF_ENB

R and N register mux selection. 0 = R and N values come from the ROM. 1 = Data is
load from DAF (I2C) registers.

CY28373

Document #: 38-07460 Rev. *A

Page 10 of 20

Dial-a-Frequency

Feature

Dial-a-Frequency

gives the designer direct access to the ref-

erence divider (M) and the feedback divider (N) of the internal
Phase-Locked Loop (PLL). The algorithm is the same for all P
values, which is F

cpu

= (P

N) / M with the following conditions.

M = (20..56), N = (21..127) and N > M > N/2. `P' is a large value
constant that translates the output of the PLL into the CPU
frequency. The Value of `P' is relative to the latest frequency
selected in the device prior to enabling the Dial-a-Frequency
feature. Furthermore, P is an indication that the frequency ra-
tios between the CPU, SDRAM. AGP (3V66), PCI, and DRCG
(CPU/2) clock outputs remains unchanged when the
Dial-a-Frequency

feature is enabled.

Table 10. P Constants

FS(4:0)

00000, 00001, 00010, 00011, 01000, 01001,
01010, 01011, 10001, 10011, 10110, 11000,
11001, 11011

96000000

00100, 00101, 00110, 00111, 10100, 10101,
10111, 11010

128,000,000

01100, 01101, 01110, 01111, 11100, 11101,
11110, 11111

192,000,000

00010

76,800,000

10000

64,000,000

Table 11. Signal Loading

Clock Name

Max Load

(in pF)

REF, 48MHz, 24_48MHz, ZCLK, MREF,
MREFB

AGP, PCI_F, PCI

CPUT/C

See Figure 1

CY28373

Document #: 38-07460 Rev. *A

Page 11 of 20

For Differential CPU Output Signals

Figure 1 shows the test load configuration for the differential
Host Clock Outputs.

Figure 1. 0.7V Configuration

Figure 2. MREF/MREF_B Phase - Same Frequency, Byte 9 bit 2 = 0

Figure 3. MREF/MREF_B Phase - Different Frequencies, Byte 9 bit 2 = 1

C P U T

M U L T S E L

P C B

C P U C

49.9

M e a s u re m e n t P o in t

2 p F

475

IR E F

M e a s u re m e n t P o in t

2 p F

Table 12.

Group Timing Relationships and Tolerances

Parameter

Description

Offset (ns)

Tolerance/Range (ns)

Conditions

AGPPCI

AGP to PCI

0.5

±0.5

AGP Leads

CPUAGP

CPU to AGP

2.0

CPU Leads

CPUZCLK

CPU to ZCLK

2.0

CPU Leads

CPUPCI

CPU to PCI

2.0

CPU Leads

MREF_B = 66MHz

MREF = 66 MHz

MREF_B = 66MHz

MREF = 83 MHz

CY28373

Document #: 38-07460 Rev. *A

Page 12 of 20

Power Management Functions

All clocks can be individually enabled or stopped via the 2-wire
control interface. All clocks maintain a valid high period on
transitions from running to stop and on transitions from
stopped to running when the chip was not powered OFF.

Power Down Assertion

When PD# is sampled LOW by two consecutive rising edges
of CPUC clock then all clocks must be held LOW on their next
HIGH-to-LOW transition. CPUT clocks must be held with a
value of 2 x Iref.

Figure 4. Power Down Assertion Timing Waveform

Power Down Deassertion

The Power-up latency is less than 1.5 ms.

Figure 5. Power Down Deassertion Timing Waveform

P C I 3 3 M H z

P D #

C P U T

C P U C

R E F 1 4 . 3 1 8 M H z

U S B 4 8 M H z

Z C L K

M R E F /M R E F _ B

A G P 6 6 M H z

R E F 14.318M H z

P C I 33M H z

P D #

C P U T

C P U C

A G P 66M H z

U S B 48M H z

<1.5 m sec

Z C LK

M R E F /M R E F _B

CY28373

Document #: 38-07460 Rev. *A

Page 13 of 20

Figure 6. VTT_PWGD Timing Diagram

[2]

Figure 7. Clock Generator Power-Up/ Run State Diagram

Note:

This timing diagram shows that when VTT_PWRGD transitions to a logic HIGH the first time at power up. After the first transition of VTT_PWRGD to HIGH, the
device is not affected by additional transitions of VTT_PWRGD.

VID (0:3),

SEL (0,1)

VTT_PWRGD

PWRGD

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.25 mS

Delay

State 0

State 2

State 3

W ait for

VTT_GD

Sample
FS(4:0)

Off

State 1

(see note)

D e la y 0 .2 5 m S

S 1

P o w e r O f f

S 0

V D D A = 2 .0 V

S a m p le

I n p u t s

F S ( 3 :0 )

S 2

V D D 3 . 3 = O f f

N o r m a l

O p e r a tio n

S 3

W a it f o r 1 .2 m s

E n a b le

O u tp u t e s

CY28373

Document #: 38-07460 Rev. *A

Page 14 of 20

CPU_STP# Assertion

When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by 2 rising CPUC clock edges.
The final state of the stopped CPU signal is CPUT = HIGH and
CPUC = LOW. There is no change to the output drive current

values during the stopped state. The CPUT is driven HIGH
with a current value equal to (Mult 0 `select') x (Iref), and the
CPUC signal will not be driven. Due to external pull-down cir-
cuitry CPUC will be LOW during this stopped state.

Figure 8. CPU_STP# Assertion Waveform

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.

Figure 9. CPU_STP# Deassertion Waveform

CPU_STP#

CPUT

CPUC

CPUCS_T

CPUCS_C

CPU_STP#

CPUCS_T

CPUCS_C

CPUT

CPUC

CY28373

Document #: 38-07460 Rev. *A

Page 15 of 20

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for syn-
chronous stopping and starting the PCI outputs while the rest
of the clock generator continues to function. The set-up time

for capturing PCI_STP# going LOW is 10 ns (t

setup

). The

PCI_F clock will not be affected by this pin.

Figure 10. PCI_STP# Assertion Waveform

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal will cause all PCI
clocks to resume running in a synchronous manner within 1
PCI clocks period after PCI_STP# transitions to a HIGH level.

Figure 11. PCI_STP# Deassertion Waveform

PCI_STP#

PCI_F

PCI

setup

PCI_STP#

PCI_F

PCI

setup

CY28373

Document #: 38-07460 Rev. *A

Page 16 of 20

Maximum Ratings

[3]

Input Voltage Relative to V

:...............................V

0.3V

Input Voltage Relative to V

DDQ

or AV

: ............. V

+ 0.3V

Storage Temperature: ................................. 65

C to +150

Operating Temperature: .................................... 0

C to +70

Maximum ESD .............................................................2000V

Maximum Power Supply: ................................................5.5V

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, V

and V

OUT

should be constrained to the

range.

< (V

or V

OUT

) < V

Unused inputs must always be tied to an appropriate logic volt-
age level (either V

or V

Note:

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

All outputs loaded as per maximum. See Table 11.

DC Parameters

= V

DDPCI

= V

DDAGP

= V

DD48M

= V

DDCPU

= V

DDA

= V

DDMREF

= V

DDZ

= V

DDREF

= 3.3V±5%, T

= 0°C TO +70°C)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

IL1

Input Low Voltage

Applicable to all input exclusive of
the SMBus control lines

1.0

Vdc

IH1

Input High Voltage

2.0

Vdc

IL2

Input Low Voltage

Applicable to SDATA and SCLK

1.0

Vdc

IH2

Input High Voltage

2.2

Vdc

Dynamic Supply Current

CPU frequency set at 133.3 MHz

[4]

156

180

Power Down Supply current

PD# = 0

3.8

4.0

PUP

Internal Pull-up Device Current

Input @ V

PWRDN

Internal Pull-down Device Current

Input @ V

Input Pin Capacitance

OUT

Output Pin Capacitance

Pin Inductance

XTAL

Crystal Pin Capacitance

Measured from the Xin or Xout to
V

CY28373

Document #: 38-07460 Rev. *A

Page 17 of 20

AC Parameters

Parameter

Description

Min.

Typ.

Max.

Unit

Notes

Crystal
T

Xin Duty Cycle

5, 6

PERIOD

Xin Period

69.84

71.0

5, 6

HIGH

Xin High Voltage

0.7V

Volts

LOW

Xin Low Voltage

0.3V

Volts

RISE/TFALL

Xin Rise and Fall Times

10.0

CCJ

Xin Cycle-to-Cycle Jitter

500

5, 8

Txs

Crystal Start-up Time

P4 CPU at 0.7V
T

CPUT/C Duty Cycle

8, 10

RISE/TFALL

CPUT/C Rise and Fall Times

175

700

10, 11

SKEW

CPUT/C to CPUCS_T/C Clock Skew

100

8, 10

CCJ

CPUT/C Cycle-to-Cycle Jitter

150

8, 10

CROSS

Crossing Point Voltage

280

430

MREF/MREFB
T

MREF/MREFB Duty Cycle

8, 10

RISE/TFALL

MREF/MREFB Rise and Fall Times

0.4

1.6

10, 13

SKEW

MREF/MREFB to CPUCS_T/C Clock Skew

100

8, 10

CCJ

MREF/MREFB Cycle-to-Cycle Jitter

350

8, 10

ZCLK
T

ZCLK Duty Cycle

8, 10

RISE/TFALL

ZCLK Rise and Fall Times

0.4

1.6

10, 13

SKEW

ZCLK to CPUCS_T/C Clock Skew

175

8, 10

CCJ

ZCLK Cycle-to-Cycle Jitter

400

8, 10

AGP
T

AGP Duty Cycle

8, 10

PERIOD

AGP Period

8, 10

HIGH

AGP High Time

5.25

10, 14

LOW

AGP Low Time

5.05

10, 15

RISE/TFALL

AGP Rise and Fall Times

0.4

1.6

10, 13

SKEW

Any AGP to Any AGP Clock Skew

175

8, 10

CCJ

AGP Cycle-to-Cycle Jitter

500

8, 10

PCI
T

PCI Duty Cycle

8, 10

PERIOD

PC Period

30.0

8, 10

HIGH

PCI High Time

12.0

10, 14

LOW

PCI Low Time

12.0

10, 15

RISE/TFALL

PCI Rise and Fall Times

0.5

2.5

10, 13

SKEW

Any PCI to Any PCI Clock Skew

550

8, 10

CCJ

PCI, PCI_F Cycle-to-Cycle Jitter

500

8, 10

CY28373

Document #: 38-07460 Rev. *A

Page 18 of 20

Notes:

When Xin is driven from and external clock source.

This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.

Measured between 0.2V

and 0.7V

Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals and at zero-crossing for differential signals.

When Crystal meets minimum 40-ohm device series resistance specification.

10. All outputs loaded as per loading specified in the loading table. See Table 11.

11. Measured from Vol = 0.175V to Voh = 0.525V.

12. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts.
13. Probes are placed on the pins and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 20% and 80% for differential signals.
14. Probes are placed on the pins and measurements are acquired at 2.4V.
15. Probes are placed on the pins and measurements are acquired at 0.4V.
16. The time specified is measured from when all V

s reach their respective supply rail, until the frequency output is stable and operating within the specifications.

48 MHz
T

48-MHz Duty Cycle

8, 10

PERIOD

48-MHz Period

20.829

20.833

8, 10

RISE/TFALL

48-MHz Rise and Fall Times

1.0

4.0

10, 13

CCJ

48-MHz Cycle-to-Cycle Jitter

500

8, 10

24 MHz
T

24-MHz Duty Cycle

8, 10

PERIOD

24-MHz Period

41.660

41.667

8, 10

RISE/TFALL

24-MHz Rise and Fall Times

1.0

4.0

10, 13

CCJ

24-MHz Cycle-to-Cycle Jitter

500

8, 10

REF
T

REF Duty Cycle

8, 10

PERIOD

REF Period

69.8

71.0

8, 10

RISE/TFALL

REF Rise and Fall Times

1.0

4.0

10,13

CCJ

REF Cycle-to-Cycle Jitter

1000

8, 10

MISC
T

STABLE

Output Clock Stabilization

3.0

AC Parameters

(continued)

Parameter

Description

Min.

Typ.

Max.

Unit

Notes

CY28373

Document #: 38-07460 Rev. *A

Page 19 of 20

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Drawing and Dimensions

Dial-a-dB and Dial-a-Frequency are registered trademarks of Cypress Semiconductor Corporation. Dial-a-Skew and Dial-a-Ratio
are trademarks of Cypress Semiconductor Corporation. Pentium is a registered trademark of Intel Corporation.

Ordering Information

Part Number

Package Type

Product Flow

CY28373OC

56 Pin Shrunk Small Outline package (SSOP)

Commercial, 0

to 70

CY28373OCT

56 Pin Shrunk Small Outline package (SSOP) - Tape and Reel

Commercial, 0

to 70

56-Lead Shrunk Small Outline Package O56

51-85062-*C

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28373OC

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28373OC