Clock Synthesizer with Differential SRC and CPU Outputs

CY28405-2

CypressSemiconductorCorporation

3901NorthFirstStreet

SanJose

CA 95134

408-943-2600

Document #: 38-07511 Rev. *C

Revised Spetember 29, 2003

Features

· Supports Intel

Pentium

4-type CPUs

· Selectable CPU frequencies
· 3.3V power supply
· Nine copies of PCI clocks
· Four copies of 3V66 with one optional VCH
· Two copies 48-MHz clock

· Three differential CPU clock pairs
· One differential SRC clock
· Support SMBus/I

C Byte, Word and Block Read/ Write

· Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

· 48-pin SSOP package

Note:

Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.

CPU

SRC

3V66

PCI

REF

48M

x 3

x 1

x 4

x 9

x 2

Block Diagram

Pin Configuration

SSOP-48

VDD_REF

XTAL

PLL Ref Freq

XOUT

XIN

VDD_PCI

OSC

SCLK

PLL 1

Logic

VDD_48MHz

SDATA

VDD_3V66

Divider

Network

VDD_CPU

FS_(A:B)

PD#

REF(0:1)

VTT_PWRGD#

IREF

3V66_(0:2)

PCIF(0:2)

PCI(0:5)

DOT_48

3V66_3/VCH

PLL2

CPUT(0:1, ITP), CPUC(0:1, ITP)

VDD_SRCT
SRCT, SRCC

USB_48

*FS_A/REF_0
*FS_B/REF_1

XIN

XOUT

VSS_REF

PCIF0
PCIF1
PCIF2

VDD_PCI

VSS_PCI

PCI0
PCI1
PCI2
PCI3

VDD_PCI

VSS_PCI

PCI4
PCI5

P D #

DOT_48
USB_48

VSS_48

VDD_48

VDDA
VSSA

VDD_SRC

SRCT
SRCC

VSS_SRC

C P U T 0
CPUC0

VDD_CPU

C P U T 1
CPUC1

VSS_CPU

CPUT_ITP
CPUC_ITP

SCLK*

SDATA*

3V66_0

VTT_PWRGD#

IREF

VDD_3V66

3V66_2
3V66_3/VCH

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

4
0

-
2

VDD_REF

3V66_1
VSS_3V66

* 100k Internal Pull-up

[1]

CY28405-2

Document #: 38-07511 Rev. *C

Page 2 of 16

Frequency Select Pins (FS_A, FS_B)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels

of FS_A and FS_B VTT_PWRGD# employs a one-shot

functionality in that once a valid low on VTT_PWRGD# has
been sampled low, all further VTT_PWRGD#, FS_A, and

FS_B transitions will be ignored. Once "Test Clock Mode" has

been invoked, all further FS_B transitions will be ignored and
FS_A will asynchronously select between the Hi-Z and REF/N

mode. Exiting test mode is accomplished by cycling power

with FS_B in a high or low state.

Pin Description

Pin No.

Name

Type

Description

FS_A/REF_0

I/O, SE

This pin is the FS_A at power-up and VTT_PWRGD# = 0, then it

becomes REF_0 output. (3.3V 14.318-MHz clock output.)

FS_B/REF_1

I/O, SE

This pin is the FS_B at power-up and VTT_PWRGD# = 0, then it

becomes REF_1 output. (3.3V 14.318-MHz clock output.)

XIN

Crystal Connection or External Reference Frequency Input. This

pin has dual functions. It can be used as an external 14.318-MHz

crystal connection or as an external reference frequency input.

XOUT

O, SE

Crystal Connection. Connection for an external 14.318-MHz crystal

output.

39, 42,

38, 41,
45, 44

CPUT(0:1),

CPUC(0:1),
CPUT_ITP,

CPUC_ITP

O, DIF

CPU Clock Output. Differential CPU clock outputs, see Table1 for

frequency configuration.l

36, 35

SRCT, SRCC

O, DIF

Differential Serial Reference Clock.

26, 29, 30

3V66(2:0)

O, SE

66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.

3V66_3/VCH

O, SE

48- or 66-MHz Clock Output. 3.3V selectable through SMBUS to be

66 MHz or 48 MHz. Default is 66-MHz.

7, 8, 9

PCI_F(0:2)

O, SE

Free Running PCI Output. 33-MHz clocks divided down from 3V66.

12, 13, 14, 15, 18,

PCI(0:5)

O, SE

PCI Clock Output. 33MHz clocks divided down from 3V66.

USB_48

O, SE

Fixed 48-MHz clock output.

DOT_48

O, SE

Fixed 48-MHz clock output.

IREF

Current Reference. A precision resistor is attached to this pin which

is connected to the internal current reference.

PD#

I, PU

3.3V LVTTL input for PowerDown# active low.

VTT_PWRGD#

3.3V LVTTL input is a level sensitive strobe used to latch the

FS[A:E] input (active low).

SDATA

I/O, PU

SMBus compatible SDATA.

SCLK

I, PU

SMBus compatible SCLOCK.

VDDA

PWR

3.3V power supply for PLL.

VSSA

GND

Ground for PLL.

3, 10, 16, 24, 27,
34, 40

VDD

PWR

3.3V Power supply for outputs.

6, 11, 17, 23, 28,
37, 43

VSS

GND

Ground for outputs.

CY28405-2

Document #: 38-07511 Rev. *C

Page 3 of 16

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface initial-

izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are

normally made upon system initialization, if any are required.

The interface cannot be used during system operation for pow-
er management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit

first) with the ability to stop after any complete byte has been

transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-

set of the indexed byte is encoded in the command code, as

described in Table3.
The block write and block read protocol is outlined in Table4

while Table5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).

Table 1. Frequency Select Table (FS_A FS_B)

FS_A

FS_B

CPU

SRC

3V66

PCIF/PCI

REF0

REF1

USB/DOT

100 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

B6b7

REF/N

200 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

133 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

B6b7

Hi-Z

Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1

FS_A

FS_B

CPU

SRC

3V66

PCIF/PCI

REF0

REF1

USB/DOT

200 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

400 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

266 MHz

100/200 MHz

66 MHz

33 MHz

14.3 MHz

14.31 MHz

48 MHz

Table 3. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave

11:18

Command Code 8 Bit

'00000000' stands for block operation

11:18

Command Code 8 Bit

'00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 1 8 bits

Read = 1

Acknowledge from slave

38:45

Data byte 2 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge from master

....

......................

39:46

Data byte from slave 8 bits

CY28405-2

Document #: 38-07511 Rev. *C

Page 4 of 16

Byte Configuration Map

....

Data Byte (N1) 8 bits

Acknowledge from master

....

Acknowledge from slave

48:55

Data byte from slave 8 bits

....

Data Byte N 8 bits

Acknowledge from master

....

Acknowledge from slave

....

Data byte N from slave 8 bits

....

Stop

....

Acknowledge from master

....

Stop

Table 4. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write = 0

Acknowledge from slave