Clock Synthesizer with Differential SRC and CPU Outputs
CY28405-2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07511 Rev. **
Revised April 14, 2003
Features
Supports Intel
Pentium
4-type CPUs
100-/133-/166-/200-MHz selectable CPU frequencies
3.3V power supply
Nine copies of PCI clocks
Four copies of 3V66 with one optional VCH
Two copies 48-MHz USB clock
Three differential CPU clock pairs
One differential SRC clock
Support SMBus/I
2
C Byte, Word and Block Read/ Write
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
48-pin SSOP Package
Note:
1.
Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
CPU
SRC
3V66
PCI
REF
48M
x 3
x 1
x 4
x 9
x 2
x 2
Block Diagram
Pin Configuration
SSOP-48
~
VDD_REF
XTAL
PLL Ref Freq
XOUT
XIN
VDD_PCI
OSC
SCLK
PLL 1
I
2
C
Logic
VDD_48MHz
SDATA
VDD_3V66
Divider
Network
VDD_CPU
FS_(A:B)
PD#
REF(0:1)
VTT_PWRGD#
IREF
3V66_(0:2)
PCIF(0:2)
PCI(0:5)
DOT_48
3V66_3/VCH
2
PLL2
CPUT(0:1, ITP), CPUC(0:1, ITP)
VDD_SRCT
SRCT, SRCC
USB_48
*FS_A/REF_0
*FS_B/REF_1
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PD#
DOT_48
USB_48
VSS_48
VDD_48
VDDA
VSSA
VDD_SRC
SRCT
SRCC
VSS_SRC
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
CPUT_ITP
CPUC_ITP
SCLK
SDATA
3V66_0
VTT_PWRGD#
IREF
VDD_3V66
3V66_2
3V66_3/VCH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C
Y
284
05-2
VDD_REF
3V66_1
VSS_3V66
* 150k Internal Pull-up
[1]
CY28405-2
Document #: 38-07511 Rev. **
Page 2 of 19
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A & FS_B input values. For all logic levels of
FS_A and FS_B VTT_PWRGD# employs a one-shot function-
ality in that once a valid low on VTT_PWRGD# has been
sampled low, all further VTT_PWRGD#, FS_A, and FS_B
transitions will be ignored. Once "Test Clock Mode" has been
invoked, all further FS_B transitions will be ignored and FS_A
will asynchronously select between the Hi-Z and REF/N mode.
Exiting test mode is accomplished by cycling power with FS_B
in a high or low state.
Pin Description
Pin No.
Name
Type
Description
1, 2
REF(0:1)
O, SE
Reference Clock. 3.3V 14.318-MHz clock output.
1, 2
FS_A, FS_B
I
3.3V LVTTL latched input for CPU frequency selection.
4
XIN
I
Crystal Connection or External Reference Frequency Input. This
pin has dual functions. It can be used as an external 14.318-MHz
crystal connection or as an external reference frequency input.
5
XOUT
O, SE
Crystal Connection. Connection for an external 14.318-MHz crystal
output.
39, 42,
38, 41,
45, 44
CPUT(0:1),
CPUC(0:1),
CPUT_ITP,
CPUC_ITP
O, DIF
CPU Clock Output. Differential CPU clock outputs, see Table 1 for
frequency configuration.
36, 35
SRCT, SRCC
O, DIF
Differential Serial Reference Clock.
26, 29, 30
3V66(2:0)
O, SE
66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
25
3V66_3/VCH
O, SE
48- or 66-MHz Clock Output. 3.3V selectable through SMBUS to be
66 MHz or 48 MHz. Default is 66-MHz.
7, 8, 9
PCI_F(0:2)
O, SE
Free Running PCI Output. 33-MHz clocks divided down from 3V66.
12, 13, 14, 15, 18,
19
PCI(0:5)
O, SE
PCI Clock Output. 33MHz clocks divided down from 3V66.
22
USB_48
O, SE
Fixed 48-MHz clock output.
21
DOT_48
O, SE
Fixed 48-MHz clock output.
46
IREF
I
Current Reference. A precision resistor is attached to this pin which
is connected to the internal current reference.
20
PD#
I, PU
3.3V LVTTL input for PowerDown# active low.
33
VTT_PWRGD#
I
3.3V LVTTL input is a level sensitive strobe used to latch the
FS[A:E] input (active low).
32
SDATA
I/O
SMBus compatible SDATA.
31
SCLK
I
SMBus compatible SCLOCK.
48
VDDA
PWR
3.3V power supply for PLL.
47
VSSA
GND
Ground for PLL.
3, 10, 16, 24, 27,
34, 40
VDD
PWR
3.3V Power supply for outputs.
6, 11, 17, 23, 28,
37, 43
VSS
GND
Ground for outputs.
Table 1. Frequency Select Table (FS_A FS_B)
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
100 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
B6b7
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
0
1
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
133 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
1
166 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
CY28405-2
Document #: 38-07511 Rev. **
Page 3 of 19
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from any external I
2
C
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For byte write and byte read opera-
tions, the system controller can access individual indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol.The slave receiver address is 11010010 (D2h).
1
B6b7
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
1
400 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
266 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
1
333 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
Table 1. Frequency Select Table (FS_A FS_B) (continued)
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For
block read or block write operations, these bits should
be '0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 Bit'00000000' stands for
block operation
11:18
Command Code 8 Bit'00000000' stands for
block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29:36
Data byte 0 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 8 bits
30:37
Byte count from slave 8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte N/Slave Acknowledge...
39:46
Data byte from slave 8 bits
....
Data Byte N 8 bits
47
Acknowledge
....
Acknowledge from slave
48:55
Data byte from slave 8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data byte N from slave 8 bits
....
Not Acknowledge
....
Stop
CY28405-2
Document #: 38-07511 Rev. **
Page 4 of 19
Byte Configuration Map
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
Command Code 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte from master 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave 8 bits
38
Not Acknowledge
39
Stop
Byte 0: Control Register
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Allow drive selection through Byte 9, bits 6 and 7
5
0
Reserved
Reserved, set = 0
4
0
Reserved
Reserved, set = 0
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
HW
FS_B
Power up latched value of FS_B pin
0
HW
FS_A
Power up latched value of FS_A pin
Byte 1: Control Register
Bit
@Pup
Name
Description
7
0
SRCT
SRCC
Allow control of SRC during SW PCI_STP assertion
0 = Free Running, 1 = Stopped with SW PCI_STP
6
1
SRCT
SRCC
SRC Output Enable
0 = Disabled (three-state), 1 = Enabled
5
1
Reserved
Reserved
4
1
Reserved
Reserved
3
1
Reserved
Reserved
2
1
CPUT_ITP, CPUC_ITP
CPU_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
CY28405-2
Document #: 38-07511 Rev. **
Page 5 of 19
Byte 2: Control Register
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
6
0
SRCT, SRCC
SRC Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power down
5
0
CPUT_ITP, CPUC_ITP
CPU(T/C)_ITP Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
4
0
CPUT1, CPUC1
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
3
0
CPUT0, CPUC0
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
2
0
Reserved
Reserved, set = 0
1
0
Reserved
Reserved, set = 0
0
0
Reserved
Reserved, set = 0
Byte 3: Control Register
Bit
@Pup
Name
Description
7
1
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
1
Reserved
Reserved
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register
Bit
@Pup
Name
Description
7
0
USB_48
USB_48MHz Drive Strength Control
0 = Low Drive Strength, 1 = High Drive Strength
6
1
USB_48
USB_48MHz Output Enable
0 = Disabled, 1 = Enabled
5
0
PCIF2
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
CY28405-2
Document #: 38-07511 Rev. **
Page 6 of 19
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register
Bit
@Pup
Name
Description
7
1
DOT_48
DOT_48MHz Output Enable
0 = Disabled, 1 = Enabled
6
1
Reserved
Reserved
5
0
3V66_3/VCH
3V66_3/VCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
4
1
3V66_3/VCH
3V66_3/VCH Output Enable
0 = Disabled, 1 = Enabled
3
1
Reserved
Reserved
2
1
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
1
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 6: Control Register
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
0
Reserved
Reserved, set = 0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUT_ITP,CPUC_ITP
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRCT/C Frequency Select
0 = 100Mhz, 1 = 200MHz
3
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Mode
0 = down (default), 1 = center
2
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Control Register
Bit
@Pup
Name
Description
7
0
Revision ID Bit 3
Revision ID Bit 3
6
1
Revision ID Bit 2
Revision ID Bit 2
5
0
Revision ID Bit 1
Revision ID Bit 1
4
0
Revision ID Bit 0
Revision ID Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
Byte 4: Control Register (continued)
Bit
@Pup
Name
Description
CY28405-2
Document #: 38-07511 Rev. **
Page 7 of 19
Byte Configuration Map
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 7: Control Register
Bit
@Pup
Name
Description
Byte 7: Control Register
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Allow drive selection through Byte 9, bits 6 and 7
5
0
Reserved
Reserved, set = 0
4
0
Reserved
Reserved, set = 0
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
HW
FS_B
Power-up latched value of FS_B pin
0
HW
FS_A
Power-up latched value of FS_A pin
Byte 8: Control Register
Bit
@Pup
Name
Description
7
0
SRCT
SRCC
Allow control of SRC during SW PCI_STP assertion
0 = Free Running, 1 = Stopped with SW PCI_STP
6
1
SRCT
SRCC
SRC Output Enable
0 = Disabled (three-state), 1 = Enabled
5
1
Reserved
Reserved
4
1
Reserved
Reserved
3
1
Reserved
Reserved
2
1
CPUT_ITP, CPUC_ITP
CPU_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 9: Control Register
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
6
0
SRCT, SRCC
SRC Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power down
5
0
CPUT_ITP, CPUC_ITP
CPU(T/C)_ITP Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
4
0
CPUT1, CPUC1
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
3
0
CPUT0, CPUC0
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power down, 1 = Three-state in power down
2
0
Reserved
Reserved, set = 0
1
0
Reserved
Reserved, set = 0
CY28405-2
Document #: 38-07511 Rev. **
Page 8 of 19
0
0
Reserved
Reserved, set = 0
Byte 10: Control Register
Bit
@Pup
Name
Description
7
1
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP de-assert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
1
Reserved
Reserved
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 11: Control Register
Bit
@Pup
Name
Description
7
0
USB_48
USB_48MHz Drive Strength Control
0 = Low Drive Strength, 1 = High Drive Strength
6
1
USB_48
USB_48MHz Output Enable
0 = Disabled, 1 = Enabled
5
0
PCIF2
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 12: Control Register
Bit
@Pup
Name
Description
7
1
DOT_48
DOT_48MHz Output Enable
0 = Disabled, 1 = Enabled
6
1
Reserved
Reserved
5
0
3V66_3/VCH
3V66_3/VCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
4
1
3V66_3/VCH
3V66_3/VCH Output Enable
0 = Disabled, 1 = Enabled
Byte 9: Control Register
Bit
@Pup
Name
Description
CY28405-2
Document #: 38-07511 Rev. **
Page 9 of 19
Crystal Recommendations
The CY28405-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28405-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
3
1
Reserved
Reserved
2
1
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
1
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 13: Control Register
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
0
Reserved
Reserved, set = 0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUT_ITP,CPUC_ITP
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRCT/C Frequency Select
0 = 100Mhz, 1 = 200MHz
3
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Mode
0 = down (default), 1 = center
2
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 14: Control Register
Bit
@Pup
Name
Description
7
0
Revision ID Bit 3
Revision ID Bit 3
6
1
Revision ID Bit 2
Revision ID Bit 2
5
0
Revision ID Bit 1
Revision ID Bit 1
4
0
Revision ID Bit 0
Revision ID Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 12: Control Register
Bit
@Pup
Name
Description
CY28405-2
Document #: 38-07511 Rev. **
Page 10 of 19
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It's a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be 2 times the specified
load capacitance(CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tative loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
XTAL
C e2
C e1
C s1
C s2
X1
X2
C i1
C i2
C lock C hip
(C Y28405-2)
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
CY28405-2
Document #: 38-07511 Rev. **
Page 11 of 19
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
......................................using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs..............................................Stray capacitance (trace,etc)
Ci ............. Internal capacitance (lead frame, bond wires etc)
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low `stopped' state.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of
CPUC clock then all clock outputs (except CPU) clocks must
be held low on their next high to low transition. CPU clocks
must be hold with CPU clock pin driven high with a value of 2x
Iref and CPUC undriven.
Due to the state of itnernal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete
PD# Deassertion
The power-up latency between PD# rising to a valid logic `1'
level and the starting of all clocks is less than 3.0 ms.
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL - (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
PW RDW N#
3V66, 66M Hz
USB, 48M Hz
PCI, 33M Hz
REF, 14.131818
SRC 100M Hz
SRC# 100M Hz
CPU#, 133M Hz
CPU, 133M Hz
Figure 3. Power-down Assertion Timing Waveforms
CY28405-2
Document #: 38-07511 Rev. **
Page 12 of 19
REF, 14.131818
Tdrive_PW RDN#
<300
S, >200m V
PW RDW N#
CPU#, 133M Hz
CPU, 133M Hz
SRC# 100M Hz
3V66, 66M Hz
USB, 48M Hz
PCI, 33M Hz
SRC 100M Hz
Tstable
<1.8nS
Figure 4. Power-down Deassertion Timing Waveforms
FS_A, FS_B
VTT_PW RGD#
PW RGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
W ait for
VTT_PW RGD#
Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PW RGD# is ignored
Figure 5. VTT_PWRGD# Timing Diagram
CY28405-2
Document #: 38-07511 Rev. **
Page 13 of 19
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDD_A = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD_A = off
Figure 6. Clock Generator Power-up/Run State Diagram
CY28405-2
Document #: 38-07511 Rev. **
Page 14 of 19
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
Core Supply Voltage
0.5
4.6
V
V
DDA
Analog Supply Voltage
0.5
4.6
V
V
IN
Input Voltage
Relative to V
SS
0.5
V
DD
+ 0.5
VDC
T
S
Temperature, Storage
Non Functional
65
+150
C
T
A
Temperature, Operating Ambient
Functional
0
70
C
T
J
Temperature, Junction
Functional
150
C
ESD
HBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
V
JC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
15
C/W
JA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
45
C/W
UL94
Flammability Rating
At 1/8 in.
V0
MSL
Moisture Sensitivity Level
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
, V
DDA
3.3 Operating Voltage
3.3V 5%
3.135
3.465
V
V
ILI2C
Input Low Voltage
SDATA, SCLK
1.0
V
IHI2C
Input High Voltage
SDATA, SCLK
2.2
V
IL
Input Low Voltage
V
SS
0.5
0.8
V
V
IH
Input High Voltage
2.0
V
DD
+0. 5
V
I
IL
Input Leakage Current
except Pull-ups or Pull downs
0 < V
IN
< V
DD
5
5
A
V
OL
Output Low Voltage
I
OL
= 1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1 mA
2.4
V
I
OZ
High-Impedance Output Current
10
10
A
C
IN
Input Pin Capacitance
2
5
pF
C
OUT
Output Pin Capacitance
3
6
pF
L
IN
Pin Inductance
7
nH
V
XIH
Xin High Voltage
0.7V
DD
V
DD
V
V
XIL
Xin Low Voltage
0
0.3V
DD
V
I
DD
Dynamic Supply Current
At 200 MHz and all outputs
loaded per Table 10 and Figure 7
280
mA
I
PD
Power-down Supply Current
PD# Asserted
1
mA
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
T
DC
XIN Duty Cycle
The device will operate
reliably with input duty cycles
up to 30/70 but the REF clock
duty cycle will not be within
specification
47.5
52.5
%
T
PERIOD
XIN period
When Xin is driven from an
external clock source
69.841
71.0
ns
CY28405-2
Document #: 38-07511 Rev. **
Page 15 of 19
T
R
/ T
F
XIN Rise and Fall Times
Measured between 0.3V
DD
and 0.7V
DD
10.0
ns
T
CCJ
XIN Cycle to Cycle Jitter
As an average over 1
s
duration
500
ps
L
ACC
Long Term Accuracy
Over 150 ms
300
ppm
CPU at 0.7V
T
DC
CPUT and CPUC Duty Cycle
Measured at crossing point V
OX
45
55
%
T
PERIOD
100-MHz CPUT and CPUC Period
Measured at crossing point V
OX
9.9970
10.003
ns
T
PERIOD
133-MHz CPUT and CPUC Period
Measured at crossing point V
OX
7.4978
7.5023
ns
T
PERIOD
166-MHz CPUT and CPUC Period
Measured at crossing point V
OX
5.9982
6.0018
ns
T
PERIOD
200-MHz CPUT and CPUC Period
Measured at crossing point V
OX
4.9985
5.0015
ns
T
SKEW
Any CPUT/C to CPUT/C Clock Skew
Measured at crossing point V
OX
100
ps
T
CCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point V
OX
125
ps
T
R
/ T
F
CPUT and CPUC Rise and Fall Times
Measured from Vol = 0.175 to
Voh = 0.525V
175
700
ps
T
RFM
Rise/Fall Matching
Determined as a fraction of
2*(T
R
-T
F
)/(T
R
+T
F
)
20
%
T
R
Rise Time Variation
125
ps
T
F
Fall Time Variation
125
ps
V
HIGH
Voltage High
Math averages Figure 7
660
850
mv
V
LOW
Voltage Low
Math averages Figure 7
150
mv
V
OX
Crossing Point Voltage at 0.7V Swing
250
550
mv
V
OVS
Maximum Overshoot Voltage
V
HIGH
+ 0.3
V
V
UDS
Minimum Undershoot Voltage
0.3
V
V
RB
Ring Back Voltage
See Figure 7. Measure SE
0.2
V
SRC
T
DC
SRCT and SRCC Duty Cycle
Measured at crossing point V
OX
45
55
%
T
PERIOD
100 MHz SRCT and SRCC Period
Measured at crossing point
V
OX
9.9970
10.003
ns
T
PERIOD
200 MHz SRCT and SRCC Period
Measured at crossing point
V
OX
4.9985
5.0015
ns
L
ACC
Long Term Accuracy
Measured at crossing point
V
OX
300
ppm
T
CCJ
SRCT/C Cycle to Cycle Jitter
Measured at crossing point
V
OX
125
ps
T
R
/ T
F
SRCT and SRCC Rise and Fall Times
Measured from Vol= 0.175 to
Voh = 0.525V
175
700
ps
T
RFM
Rise/Fall Matching
Determined as a fraction of
2*(T
R
-T
F
)/(T
R
+T
F
)
20
%
T
R
Rise Time Variation
125
ps
T
F
Fall Time Variation
125
ps
V
HIGH
Voltage High
Math averages Figure 7
660
850
mv
V
LOW
Voltage Low
Math averages Figure 7
150
mv
V
OX
Crossing Point Voltage at 0.7V Swing
250
550
mV
V
OVS
Maximum Overshoot Voltage
V
HIGH
+ 0.3
V
V
UDS
Minimum Undershoot Voltage
0.3
V
V
RB
Ring Back Voltage
See Figure 7. Measure SE
0.2
V
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
CY28405-2
Document #: 38-07511 Rev. **
Page 16 of 19
3V66
T
DC
3V66 Duty Cycle
Measurement at 1.5V
45
55
%
T
PERIOD
Spread Disabled 3V66 Period
Measurement at 1.5V
14.9955
15.0045
ns
T
PERIOD
Spread Enabled 3V66 Period
Measurement at 1.5V
14.9955
15.0799
ns
T
HIGH
3V66 High Time
Measurement at 2.4V
4.9500
ns
T
LOW
3V66 Low Time
Measurement at 0.4V
4.5500
ns
T
R
/ T
F
3V66 Rise and Fall Times
Measured between 0.4V and
2.4V
0.5
2.0
ns
T
SKEW
Any 3V66 to Any 3V66 Clock Skew
Measurement at 1.5V
250
ps
T
CCJ
3V66 Cycle to Cycle Jitter
Measurement at 1.5V
250
ps
PCI/PCIF
T
DC
PCI Duty Cycle
Measurement at 1.5V
45
55
%
T
PERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.0009
ns
T
PERIOD
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.1598
ns
T
HIGH
PCIF and PCI High Time
Measurement at 2.4V
12.0
nS
T
LOW
PCIF and PCI Low Time
Measurement at 0.4V
12.0
nS
T
R
/ T
F
PCIF and PCI Rise and Fall Times
Measured between 0.4V and
2.4V
0.5
2.0
nS
T
SKEW
Any PCI clock to Any PCI Clock Skew
Measurement at 1.5V
500
pS
T
CCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
250
ps
DOT
T
DC
Duty Cycle
Measurement at 1.5V
45
55
%
T
PERIOD
Period
Measurement at 1.5V
20.8271
20.8396
ns
T
HIGH
USB High Time
Measurement at 2.4V
8.094
10.036
nS
T
LOW
USB Low Time
Measurement at 0.4V
7.694
9.836
nS
T
R
/ T
F
Rise and Fall Times
Measured between 0.4V and
2.4V
1.0
2.0
ns
T
CCJ
Cycle to Cycle Jitter
Measurement at 1.5V
350
ps
T
SKEW
Any 48 MHz to 48 MHz clock skew
Measurement @1.5V
500
ps
USB
T
DC
Duty Cycle
Measurement at 1.5V
45
55
%
T
PERIOD
Period
Measurement at 1.5V
20.8271
20.8396
ns
T
HIGH
USB High Time
Measurement at 2.4V
8.094
10.036
nS
T
LOW
USB Low Time
Measurement at 0.4V
7.694
9.836
nS
T
R
/ T
F
Rise and Fall Times
Measured between 0.4V and
2.4V
1.0
2.0
ns
T
CCJ
Cycle to Cycle Jitter
Measurement at 1.5V
350
ps
T
SKEW
Any 48 MHz to 48 MHz Clock Skew
Measurement @1.5V
500
ps
REF
T
DC
REF Duty Cycle
Measurement at 1.5V
45
55
%
T
PERIOD
REF Period
Measurement at 1.5V
69.827
69.855
ns
T
R
/ T
F
REF Rise and Fall Times
Measured between 0.4V and
2.4V
1.0
4.0
V/ns
T
CCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
1000
ps
T
SKEW
Any REF to REF clock skew
Measurement @1.5V
500
ps
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
CY28405-2
Document #: 38-07511 Rev. **
Page 17 of 19
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
ENABLE/DISABLE and SET-UP
T
STABLE
Clock Stabilization from Power-up
1.8
ms
T
SS
Stopclock Set-up Time
10.0
ns
T
SH
Stopclock Hold Time
0
ns
Table 7. Group Timing Relationship and Tolerances
Group
Conditions
Offset
Min.
Max.
3V66 to PCI
3V66 Leads PCI
1.5ns
3.5ns
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
Table 8. USB to DOT Phase Offset
Parameter
Typical
Value
Tolerance
DOT Skew
0
0.0ns
1000ps
USB Skew
180
0.0ns
1000ps
VCH SKew
0
0.0ns
1000ps
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
30
pF
3V66 Clocks
30
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
Table 10. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Units
PCI Clocks
30
pF
3V66 Clocks
30
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
C P U T
T
P C B
T
P C B
C P U C
33
33
49.9
49.9
M e a s u re m e n t
P o in t
2 p F
475
IR E F
M e a s u re m e n t
P o in t
2 p F
Figure 7. 0.7V Load Configuration
CY28405-2
Document #: 38-07511 Rev. **
Page 18 of 19
Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
Purchase of I
2
C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification
as defined by Philips.
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Table 11. CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, I
REF
V
DD
(3*R
REF
)
Output Current
V
OH
@ Z
50 Ohms
R
REF
= 475 1%, I
REF
= 2.32mA
I
OH
= 6*I
REF
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
CY28405OC-2
48-pin SSOP
Commercial, 0
to 70
C
CY28405OC-2T
48-pin SSOP Tape and Reel
Commercial, 0
to 70
C
2 .4 V
0 .4 V
3 .3 V
0 V
T r
T f
1 .5 V
3 .3 V s ig n a l s
tD C
P r o b e
O u tp u t u n d e r T e s t
L o a d C a p
-
-
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
48-lead Shrunk Small Outline Package O48
51-85061-*C
CY28405-2
Document #: 38-07511 Rev. **
Page 19 of 19
Document History Page
Document Title: CY28405-2 Clock Synthesizer with Differential SRC and CPU Outputs
Document Number: 38-07511
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
125353
04/15/03
RGL
New Data Sheet
PDF 
ZIP