Clock Generator for Intel

Alviso Chipset

CY28411

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07594 Rev. *B

Revised June 11, 2004

Features

· Compliant to Intel

CK410M

· Supports Intel Pentium-M CPU
· Selectable CPU frequencies
· Differential CPU clock pairs
· 100-MHz differential SRC clocks
· 96-MHz differential dot clock
· 48-MHz USB clocks

· 33-MHz PCI clock
· Low-voltage frequency select input
· I

C support with readback capabilities

· Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

· 3.3V power supply
· 56-pin SSOP and TSSOP packages

CPU

SRC

PCI

REF

DOT96

USB_48

x2 / x3

x7 / x8

x 6

x 1

Block Diagram

Pin Configuration

VDD_PCI

VSS_PCI

PCI4
PCI5

VSS_PCI

VDD_PCI

PCIF0/ITP_EN

PCIF1

VTT_PWRGD#/PD

VDD_48

USB_48/FS_A

VSS_48

DOT96T

DOT96C

FS_B/TEST_MODE

SRCT0

SRCC0

SRCT1

SRCC1

VDD_SRC

SRCT2

SRCC2

SRCT3

SRCC3

PCI2
PCI_STP#

SRCC5

CPUT2_ITP/SRCT7

VSSA
VDDA

IREF

CPUT1
CPUC1

VDD_CPU

CPUT0
CPUC0

VSS_CPU

SDATA
SCLK

VDD_REF

XIN

VSS_REF

FS_C/TEST_SEL
REF

CPU_STP#

CPUC2_ITP/SRCC7

SRC4_SATAT

SRC4_SATAC

VDD_SRC

VDD_SRC
SRCT6

SRCT5

VSS_SRC

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

32
31
30
29

VDD_REF

XTAL

PLL Ref Freq

XOUT

XIN

OSC

SCLK

PLL1

Logic

VDD_48 MHz

SDATA

VDD_PCI

Divider

Network

VDD_CPU

FS_[C:A]

REF

VTT_PWRGD#

IREF

PCI[2:5]

PLL2

CPUT[0:1], CPUC[0:1],

VDD_SRC

SRCT[0:6], SRCC[0:6]

USB_48

CPU_STP#

PCI_STP#

PCI3

SRCC6

XOUT

CY28

56 SSOP/TSSOP

DOT96T

DOT96C

VDD_PCIF

PCIF[0:1]

CPU(T/C)2_ITP]

CY28411

Document #: 38-07594 Rev. *B

Page 2 of 19

Pin Definitions

Pin No.

Name

Type

Description

CPU_STP#

I, PU 3.3V LVTTL input for CPU_STP# active low.

44,43,41,40 CPUT/C

O, DIF Differential CPU clock outputs.

36,35

CPUT2_ITP/SRCT7,

CPUC2_ITP/SRCC7

O, DIF Selectable differential CPU or SRC clock output.

ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7

ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2

14,15

DOT96T, DOT96C

O, DIF Fixed 96-MHz clock output.

FS_A/USB_48

I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

FS_B/TEST_MODE

3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when

in test mode

0 = Hi-Z, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

FS_C/TEST_SEL

3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled

to V

IMFS_C

when VTT_PWRGD# is asserted low.

Refer to DC Electrical Specifications table for V

ILFS_C

IMFS_C

IHFS_C

specifi-

cations.

IREF

A precision resistor is attached to this pin, which is connected to the internal

current reference.

56,3,4,5

PCI

O, SE 33-MHz clocks.

PCI_STP#

I, PU 3.3V LVTTL input for PCI_STP# active low.

PCIF0/ITP_EN

I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).

1 = CPU2_ITP, 0 = SRC7

PCIF1

O, SE 33-MHz clocks.

REF

O, SE Reference clock. 3.3V 14.318-MHz clock output.

SCLK

SMBus-compatible SCLOCK.

SDATA

I/O

SMBus-compatible SDATA.

26,27

SRC4_SATAT,

SRC4_SATAC

O, DIF Differential serial reference clock. Recommended output for SATA.

24,25,22,23,

19,20,17,18,

33,32,31,30

SRCT/C

O, DIF Differential serial reference clocks.

VDD_48

PWR 3.3V power supply for outputs.

VDD_CPU

PWR 3.3V power supply for outputs.

1,7

VDD_PCI

PWR 3.3V power supply for outputs.

VDD_REF

PWR 3.3V power supply for outputs.

21,28,34

VDD_SRC

PWR 3.3V power supply for outputs.

VDDA

PWR 3.3V power supply for PLL.

VSS_48

GND Ground for outputs.

VSS_CPU

GND Ground for outputs.

2,6

VSS_PCI

GND Ground for outputs.

VSS_REF

GND Ground for outputs.

VSS_SRC

GND Ground for outputs.

VSSA

GND Ground for PLL.

VTT_PWRGD#/PD

I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,

FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#

(active low) assertion, this pin becomes a real-time input for asserting power

down (active high).

XIN

14.318-MHz crystal input.

XOUT

O, SE 14.318-MHz crystal output.

CY28411

Document #: 38-07594 Rev. *B

Page 3 of 19

Frequency Select Pins (FS_A, FS_B and FS_C)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A, FS_B and FS_C input values. For all logic

levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a

one-shot functionality in that once a valid low on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B and FS_C transitions will be ignored, except in

test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 2.
The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 1. Frequency Select Table FS_A, FS_B and FS_C

FS_C

FS_B

FS_A

CPU

SRC

PCIF/PCI

REF0

DOT96

USB

MID

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

133 MHz

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

RESERVED

MID

Hi-Z

REF/2

REF/8

REF/24

REF

REF/2 REF/8

REF/24

REF

Table 2. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

8:2

Slave address 7 bits

8:2

Slave address 7 bits

Write 9

Write

Acknowledge from slave

18:11

Command Code 8 bits

18:11

Command Code 8 bits

Acknowledge from slave

27:20

Byte Count 8 bits

(Skip this step if I

C_EN bit set)

Repeat start

CY28411

Document #: 38-07594 Rev. *B

Page 4 of 19

Control Registers

Acknowledge from slave

27:21

Slave address 7 bits

36:29

Data byte 1 8 bits

Read = 1

Acknowledge from slave

45:38

Data byte 2 8 bits

37:30

Byte Count from slave 8 bits

Acknowledge from slave

Acknowledge

....

Data Byte /Slave Acknowledges

46:39

Data byte 1 from slave 8 bits

....

Data Byte N 8 bits

Acknowledge

....

Acknowledge from slave

55:48

Data byte 2 from slave 8 bits

....

Stop

Acknowledge

....

Data bytes from slave / Acknowledge

....

Data Byte N from slave 8 bits

....

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

8:2

Slave address 7 bits

8:2

Slave address 7 bits

Write

Acknowledge from slave

18:11

Command Code 8 bits

18:11

Command Code 8 bits

Acknowledge from slave

27:20

Data byte 8 bits

Repeated start

Acknowledge from slave

27:21

Slave address 7 bits

Stop

Read

Acknowledge from slave

37:30

Data from slave 8 bits

NOT Acknowledge

Stop

Table 3. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Byte 0:Control Register 0

Bit

@Pup

Name

Description

CPUT2_ITP/SRCT7

CPUC2_ITP/SRCC7

CPU[T/C]2_ITP/SRC[T/C]7 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]6

SRC[T/C]6 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]5

SRC[T/C]5 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]4

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]3

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z), 1 = Enable

CY28411

Document #: 38-07594 Rev. *B

Page 5 of 19

SRC[T/C]2

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]1

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]0

SRC[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Name

Description

PCIF0

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

DOT_96T/C

DOT_96 MHz Output Enable

0 = Disable (Hi-Z), 1 = Enabled

USB_48

USB_48 MHz Output Enable

0 = Disabled, 1 = Enabled

REF REF

Output

Enable

0 = Disabled, 1 = Enabled

Reserved

CPU[T/C]1 CPU[T/C]1

Output

Enable

0 = Disable (Hi-Z), 1 = Enabled

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enabled

CPUT/C

SRCT/C

PCIF

PCI

Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Byte 2: Control Register 2

Bit

@Pup

Name

Description

PCI5

PCI5 Output Enable

0 = Disabled, 1 = Enabled

PCI4

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2

PCI2 Output Enable

0 = Disabled, 1 = Enabled

Reserved

Reserved, Set = 1

Reserved

Reserved, Set = 1

Reserved

Reserved, Set = 1

PCIF1

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

Byte 3: Control Register 3

Bit

@Pup

Name

Description

SRC7

Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC6

Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC5

Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Byte 0:Control Register 0 (continued)

Bit

@Pup

Name

Description

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