ADVANCE

INFORMATION

Clock Generator for Intel

Alviso Chipset

CY28442

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07680 Rev. **

Revised June 24, 2004

Features

· Compliant to Intel

CK410M

· Supports Intel Pentium-M CPU
· Selectable CPU frequencies
· Differential CPU clock pairs
· 100-MHz differential SRC clocks
· 96-MHz differential dot clock
· 48-MHz USB clocks
· SRC clocks independently stoppable through

CLKREQ#[A:B]

· 96/100 MHz Spreadable differential clock.
· 33-MHz PCI clock
· Low-voltage frequency select input
· I

C support with readback capabilities

· Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

· 3.3V power supply
· 56-pin TSSOP package

CPU

SRC

PCI

REF

DOT96

USB_48

x2 / x3

x5/6

x 6

x 2

x 1

Block Diagram

Pin Configuration

USB

IREF
VDD_CPU

REF

VDD_REF

CPUT_ITP/SRCT7
CPUC_ITP/SRCC7

VDD_CPU

VDD_48MHz

96_100_SSCT
96_100_SSCC

DOT96T
DOT96C

VDD_48MHz

VDD_48

Divider

14.318MHz

Crystal

PLL1

CPU

PLL2

96MSS

PLL4

FIXED

I2C

Logic

PLL Reference

XIN

XOUT

PCI_STP#

FS_[C:A]

VTTPWR_GD#/PD

SDATA

SCLK

CPUT
CPUC

SRCT[1:5]
CPUC[1:5]

VDD_SRC

PCI

VDD_PCI

PCIF

VDD_PCI

CPU_STP#

CLKREQ[A:B]#

PCI2/SEL_CLKREQ**

**96_100_SEL/PCIF1

CY28442

56 pin TSSOP/SSOP

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

VSS_REF

VDD_REF

PCI3

PCI4
PCI5

VSS_PCI

VDD_PCI

ITP_EN/PCIF0

VDD_48

FS_A/48M_0

VSS_48

DOT96T

DOT96C

FS_B/TESTMODE

96_100_SSCT

96_100_SSCC

SRCT1

SRCC1

VDD_SRC

SRCT2

SRCC2

SRCT3

SRCC3

SRCT4_SATA

SRCC4_SATA

VDD_SRC

VTTPWRGD#/PD

8
9

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

1
2
3
4
5
6
7

PCI_STP#
CPU_STP#

FS_C(TEST_SEL)/REF0
REF1

VSSA2
XIN

VDDA2

XOUT

SCLK
VSS_CPU
CPUT0

CPUC0
VDD_CPU
CPUT1

CPUC1
IREF
VSSA
VDDA
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7

VDD_SRC_ITP

CLKREQA#/SRCT6
CLKREQB#/SRCC6
SRCT5
SRCC5

VSS_SRC

SDATA

ADVANCE INFORMATION

CY28442

Document #: 38-07680 Rev. **

Page 2 of 22

Pin Definitions

Pin No.

Name

Type

Description

VDD_REF

PWR 3.3V power supply for outputs.

VSS_REF

GND Ground for outputs.

33,32

CLKREQA#/SRCT6,

CLKREQB#,SRCC6

I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active low) or 100 MHz

Serial Reference Clock.

Selectable through

CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to

enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte

VDD_PCI

PWR 3.3V power supply for outputs.

VSS_PCI

GND Ground for outputs.

3,4,5

PCI

O, SE 33-MHz clock

ITP_EN/PCIF0

I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33 MHz clock output.

(sampled on the VTT_PWRGD# assertion).

1 = CPU2_ITP, 0 = SRC7

PCIF1/96_100_SEL

I/O,

PD,SE

33-MHz clock/3.3V-tolerant input for 96_100M frequency selection

(sampled on the VTT_PWRGD# assertion).

1 = 100MHz, 0 = 96MHz

VTT_PWRGD#/PD

I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,

FS_B, FS_C, and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After

VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for

asserting power down (active high).

VDD_48

PWR 3.3V power supply for outputs.

FS_A/48_M0

I/O

3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

VSS_48

GND Ground for outputs.

14,15

DOT96T, DOT96C

O, DIF Fixed 96-MHz clock output.

FS_B/TEST_MODE

3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state

when in test mode

0 = Tri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

17,18

96_100_SSC

O,DIF Differential 96/100 MHz SS clock for flat-panel display

19,20,22,23,

24,25,30,31

SRCT/C

O, DIF 100MHz Differential serial reference clocks.

21,28

VDD_SRC

PWR 3.3V power supply for outputs.

VDD_SRC_ITP

PWR 3.3V power supply for outputs.

26,27

SRC4_SATAT,

SRC4_SATAC

O, DIF Differential serial reference clock. Recommended output for SATA.

VSS_SRC

GND Ground for outputs.

36,35

CPUT2_ITP/SRCT7,

CPUC2_ITP/SRCC7

O, DIF Selectable differential CPU or SRC clock output.

ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7

ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2

VDDA

PWR 3.3V power supply for PLL.

VSSA

GND Ground for PLL.

IREF

A precision resistor is attached to this pin, which is connected to the internal

current reference.

VDD_CPU

PWR 3.3V power supply for outputs.

44,43,41,40 CPUT/C

O, DIF Differential CPU clock outputs.

VSS_CPU

GND Ground for outputs.

SCLK

SMBus-compatible SCLOCK.

SDATA

I/O

SMBus-compatible SDATA.

ADVANCE INFORMATION

CY28442

Document #: 38-07680 Rev. **

Page 3 of 22

Frequency Select Pins (FS_A, FS_B and FS_C)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A, FS_B and FS_C input values. For all logic

levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a

one-shot functionality in that once a valid low on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B and FS_C transitions will be ignored, except in

test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 2.
The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

VDDA2

PWR 3.3V power supply for PLL2.

XOUT

O, SE 14.318-MHz crystal output.

XIN

14.318-MHz crystal input.

VSSA2

GND Ground for PLL2.

REF1

Fixed 14.318 MHz clock output.

FS_C_TEST_SEL/

REF0

I/O

3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.

Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted

low.

Refer to DC Electrical Specifications table for V

IL_FS

IH_FS

specifications.

CPU_STP#

I, PU 3.3V LVTTL input for CPU_STP# active low.

PCI_STP#

I, PU 3.3V LVTTL input for PCI_STP# active low.

PCI2/SEL_CLKREQ

I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.

(sampled on the VTT_PWRGD# assertion).

0= pins 32,33 function as clk request pins, 1= pins 32,33 function as SRC outputs.

Pin Definitions

(continued)

Pin No.

Name

Type

Description

Table 1. Frequency Select Table FS_A, FS_B and FS_C

FS_C

FS_B

FS_A

CPU

SRC

PCIF/PCI

REF0

DOT96

USB

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

133 MHz

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

166 MHz

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

200 MHz

100 MHz

33 MHz

14.318 MHz

96 MHz

48 MHz

Table 2. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

ADVANCE INFORMATION

CY28442

Document #: 38-07680 Rev. **

Page 4 of 22

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

8:2

Slave address 7 bits

8:2

Slave address 7 bits

Write 9

Write

Acknowledge from slave

18:11

Command Code 8 bits

18:11

Command Code 8 bits

Acknowledge from slave

27:20

Byte Count 8 bits

(Skip this step if I

C_EN bit set)

Repeat start

Acknowledge from slave

27:21

Slave address 7 bits

36:29

Data byte 1 8 bits

Read = 1

Acknowledge from slave

45:38

Data byte 2 8 bits

37:30

Byte Count from slave 8 bits

Acknowledge from slave

Acknowledge

....

Data Byte /Slave Acknowledges

46:39

Data byte 1 from slave 8 bits

....

Data Byte N 8 bits

Acknowledge

....

Acknowledge from slave

55:48

Data byte 2 from slave 8 bits

....

Stop

Acknowledge

....

Data bytes from slave / Acknowledge

....

Data Byte N from slave 8 bits

....

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

8:2

Slave address 7 bits

8:2

Slave address 7 bits

Write

Acknowledge from slave

18:11

Command Code 8 bits

18:11

Command Code 8 bits

Acknowledge from slave

27:20

Data byte 8 bits

Repeated start

Acknowledge from slave

27:21

Slave address 7 bits

Stop

Read

Acknowledge from slave

37:30

Data from slave 8 bits

NOT Acknowledge

Stop

ADVANCE INFORMATION

CY28442

Document #: 38-07680 Rev. **

Page 5 of 22

Control Registers

Byte 0: Control Register 0

Bit

@Pup

Name

Description

CPUT2_ITP/SRCT7

CPUC2_ITP/SRCC7

CPU[T/C]2_ITP/SRC[T/C]7 Output Enable