2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
CY29774
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07479 Rev. **
Revised April 28, 2003
774
Features
Output frequency range: 8.3 MHz to 125 MHz
Input frequency range: 4.2 MHz to 62.5 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 ps max output-output skew
PLL bypass mode
Spread AwareTM
Output enable/disable
Pin compatible with MPC9774
Industrial temperature range: 40C to +85C
52-Pin 1.0-mm TQFP package
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see Functional
Table. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50
series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
P L L
20 0 -
5 00M H z
2 /
4
4 /
6 /
8 /
12
Q A 0
Q B 0
Q C 0
F B _O U T
S E L A
V C O _S E L
T C LK 0
T C LK _ S E L
F B _IN
S E LB
S E LC
M R #/O E
F B _S E L(1,0)
T C LK 1
2
C L K
S TO P
2 /
4
C L K
S T O P
4 /
6
C L K
S T O P
C LK _ S T P #
Q A 1
Q A 2
Q A 3
Q A 4
Q B 1
Q B 2
Q B 3
Q B 4
Q C 1
Q C 2
Q C 3
P L L_ E N
4
VSS
MR#/O E
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
VD
D
Q
A
QA0
VSS
QA1
VD
D
Q
A
QA2
F
B
_SEL1
VSS
QA3
VD
D
Q
A
QA4
AVSS
F
B
_SEL0
QB0
V
DDQ
B
NC
VSS
QC
3
VD
D
Q
C
QC
2
VSS
QC
1
VD
D
Q
C
QC
0
VSS
VC
O_SEL
VSS
Q B1
VDDQ B
Q B2
VSS
Q B3
VDDQ B
Q B4
FB_IN
VSS
FB_OUT
VDDFB
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29774
CY29774
Document #: 38-07479 Rev. **
Page 2 of 9
Notes:
1.
PU = Internal pull up, PD = Internal pull down
2.
A 0.1-
F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Pin Description
[1]
Pin
Name
I/O
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18, 21,
23, 25
QA(4:0)
O
LVCMOS
Clock output bank A
32, 34, 36,
38, 40
QB(4:0)
O
LVCMOS
Clock output bank B
44, 46, 48,
50
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input. See Table 2.
3
CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input. See Table 2.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input. See Table 2.
52
VCO_SEL
I, PD
LVCMOS
VCO divider select input. See Table 2.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 3.
20, 14
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select input. See Table 4.
17, 22, 26
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks
[2,3]
33, 37, 41
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks
[2,3]
45, 49
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks
[2,3]
28
VDDFB
Supply
VDD
2.5V or 3.3V Power supply for feedback output clock
[2,3]
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL
[2,3]
12
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs
[2,3]
15
AVSS
Supply
Ground
Analog Ground
1, 19, 24,
30, 35, 39,
43, 47, 51
VSS
Supply
Ground
Common Ground
11, 27, 42
NC
No Connection
CY29774
Document #: 38-07479 Rev. **
Page 3 of 9
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 33.3 MHz
16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 25 MHz
24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 16.6 MHz
32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 12.5 MHz
48
Input Clock * 48
4.2 MHz to 10.4 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
Default
0
1
TCLK_SEL
0
TCLK0
TCLK1
VCO_SEL
0
VCO
2 (high input frequency range)
VCO
4 (low input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
Outputs enabled
CLK_STP#
1
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
SELB
QB(4:0)
SELC
QC(3:0)
0
0
4
0
4
0
8
0
1
8
1
8
1
12
1
0
8
0
8
0
16
1
1
16
1
16
1
24
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
0
0
0
8
0
0
1
16
0
1
0
12
0
1
1
24
1
0
0
16
1
0
1
32
1
1
0
24
1
1
1
48
CY29774
Document #: 38-07479 Rev. **
Page 4 of 9
.
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
DC Supply Voltage
0.3
5.5
V
V
DD
DC Operating Voltage
Functional
2.375
3.465
V
V
IN
DC Input Voltage
Relative to V
SS
0.3
V
DD
+ 0.3
V
V
OUT
DC Output Voltage
Relative to V
SS
0.3
V
DD
+ 0.3
V
V
TT
Output termination Voltage
V
DD
2
V
LU
Latch Up Immunity
Functional
200
mA
R
PS
Power Supply Ripple
Ripple Frequency < 100 kHz
150
mVp-p
T
S
Temperature, Storage
Non Functional
65
+150
C
T
A
Temperature, Operating Ambient
Functional
40
+85
C
T
J
Temperature, Junction
Functional
150
C
JC
Dissipation, Junction to Case
Functional
23
C/W
JA
Dissipation, Junction to Ambient
Functional
55
C/W
ESD
H
ESD Protection (Human Body Model)
2000
Volts
FIT
Failure in Time
Manufacturing test
10
ppm
DC Electrical Specifications
(V
DD
= 2.5V 5%, T
A
= 40C to +85C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IL
Input Voltage, Low
LVCMOS
0.7
V
V
IH
Input Voltage, High
LVCMOS
1.7
V
DD
+0.3
V
V
OL
Output Voltage, Low
[4]
I
OL
= 15 mA
0.6
V
V
OH
Output Voltage, High
[4]
I
OH
= 15 mA
1.8
V
I
IL
Input Current, Low
[5]
V
IL
= V
SS
100
A
I
IH
Input Current, High
[5]
V
IL
= V
DD
A
I
DDA
PLL Supply Current
A
VDD
only
5
10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except A
VDD
1
mA
I
DD
Dynamic Supply Current
Outputs loaded @ 100 MHz
135
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
14
18
22
DC Electrical Specifications
(V
DD
= 3.3V 5%, T
A
= 40C to +85C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IL
Input Voltage, Low
LVCMOS
0.8
V
V
IH
Input Voltage, High
LVCMOS
2.0
V
DD
+0.3
V
V
OL
Output Voltage, Low
[4]
I
OL
= 24 mA
0.55
V
I
OL
= 12 mA
0.30
V
OH
Output Voltage, High
[4]
I
OH
= 24 mA
2.4
V
I
IL
Input Current, Low
[5]
V
IL
= V
SS
100
A
I
IH
Input Current, High
[5]
V
IL
= V
DD
100
A
Notes:
4.
Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
5.
Inputs have pull-up or pull-down resistors that affect the input current.
CY29774
Document #: 38-07479 Rev. **
Page 5 of 9
Note:
6.
AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
I
DDA
PLL Supply Current
A
VDD
only
5
10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except A
VDD
1
mA
I
DD
Dynamic Supply Current
Outputs loaded @ 100 MHz
225
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
12
15
18
AC Electrical Specifications
[6]
(V
DD
= 2.5V 5%, T
A
= 40C to +85C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
f
VCO
VCO Frequency
200
400
MHz
f
in
Input Frequency
8 Feedback
25
50
MHz
12 Feedback
16.6
33.3
16 Feedback
12.5
25
24 Feedback
8.3
16.6
32 Feedback
6.3
12.5
48 Feedback
4.2
8.3
Bypass mode (PLL_EN = 0)
0
200
f
refDC
Input Duty Cycle
25
75
%
t
r
, t
f
TCLK Input Rise/FallTime
0.7V to 1.7V
1.0
ns
f
MAX
Maximum Output Frequency
4 Output
50
100
MHz
8 Output
25
50
12 Output
16.6
33.3
16 Output
12.5
25
24 Output
8.3
16.6
DC
Output Duty Cycle
45
55
%
t
r
, t
f
Output Rise/Fall times
0.7V to 1.8V
0.1
1.0
ns
t
(
)
Propagation Delay (static phase
offset)
TCLK to FB_IN, does not
include jitter
100
100
ps
t
sk(O)
Output-to-Output Skew
Skew within Bank
150
ps
tsk(B)
Bank-to-Bank Skew
Banks at same frequency
150
ps
Banks at different frequency
225
t
PLZ, HZ
Output Disable Time
10
ns
t
PZL, ZH
Output Enable Time
10
ns
BW
PLL Closed Loop Bandwidth (3 dB)
0.5 - 1.0
MHz
t
JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
150
ps
Multiple frequencies
300
t
JIT(PER)
Period Jitter
100
ps
t
JIT(
)
I/O Phase Jitter
150
ps
t
LOCK
Maximum PLL Lock Time
1
ms
DC Electrical Specifications
(V
DD
= 3.3V 5%, T
A
= 40C to +85C) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
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