2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
CY29943
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07285 Rev. *C
Revised December 21, 2002
Features
200-MHz clock support
2.5V or 3.3V operation
LVPECL clock input
LVCMOS-/LVTTL-compatible inputs
18 clock outputs: drive up to 36 clock lines
200 ps max. output-to-output skew
Output Enable control
Pin compatible with MPC942P
Available in Industrial and Commercial
32-pin LQFP package
Description
The CY29943 is a low-voltage 200-MHz clock distribution
buffer with an LVPECL-compatible input clock. All other control
inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs
are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can
drive 50
series or parallel terminated transmission lines. For
series terminated transmission line, each output can drive one
or two traces giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29943 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Block Diagram
Pin Configuration
PECL_CLK
OE
VDD
18
Q0-Q17
PECL_CLK#
CY29943
Q0
Q1
Q2
VDD
Q3
Q4
Q5
VSS
Q1
7
Q1
6
Q1
5
VSS
Q1
4
Q1
3
Q1
2
VDD
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
OE
NC
PECL_CLK
PECL_CLK#
VDD
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
CY29943
Document #: 38-07285 Rev. *C
Page 2 of 7
Note:
1.
PD = internal pull-down, PU = internal pull-up.
Pin Description
[1]
Pin
Name
PWR
I/O
Description
5
PECL_CLK
I, PU
PECL Input Clock
6
PECL_CLK#
I, PD
PECL Input Clock
3
OE
I, PU
Output Enable. When HIGH, all the outputs are enabled. When set
LOW, the outputs are at high impedance.
9, 10, 11, 13,
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
Q(17:0)
VDD
O
Clock Outputs
7, 8, 16, 21, 29
VDD
3.3V or 2.5V Power Supply
1, 2, 12, 17, 25
VSS
Common Ground
4
NC
No Connection
CY29943
Document #: 38-07285 Rev. *C
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ 65C to + 150C
Operating Temperature: ................................ 40C to +85C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Notes:
2.
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3.
Inputs have pull-up/pull-down resistors that effect input current.
4.
The V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the V
CMR
range and the input lies within the VPP specification.
5.
Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
DC Parameters
(V
DD
= 3.3V 5% or 2.5V 5%, V
DDC
= 3.3V 5% or 2.5V 5%, over the specified temperature range)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
V
SS
0.8
V
V
IH
Input High Voltage
2.0
V
DD
V
I
IL
Input Low Current
[3]
200
A
I
IH
Input High Current
[3]
200
A
V
PP
Peak-to-Peak Input
Voltage
500
1000
mV
VCMR
Common Mode
Range
[4]
PECL_CLK
V
DD
= 3.3V
V
DD
1.4
V
DD
0.6
V
V
DD
= 2.5V
V
DD
1.0
V
DD
0.6
V
OL
Output Low Voltage
[5]
I
OL
= 20 mA
0.5
V
V
OH
Output High Voltage
[5]
I
OH
= 20 mA, V
DD
= 3.3V
2.4
V
I
OH
= 16 mA, V
DD
= 2.5V
2.0
I
DDQ
Quiescent Supply
Current
5
7
mA
I
DD
Dynamic Supply
Current
V
DD
= 3.3V, Outputs @ 150 MHz,
CL = 15 pF
285
mA
V
DD
= 3.3V, Outputs @ 200 MHz,
CL = 15 pF
335
V
DD
= 2.5V, Outputs @ 150 MHz,
CL = 15 pF
200
V
DD
= 2.5V, Outputs @ 200 MHz,
CL = 15 pF
240
Z
out
Output Impedance
V
DD
= 3.3V
8
12
16
V
DD
= 2.5V
10
15
20
C
in
Input Capacitance
4
pF
CY29943
Document #: 38-07285 Rev. *C
Page 4 of 7
Notes:
6.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7.
Outputs driving 50
transmission lines.
8.
Outputs loaded with 15 pF each.
9.
See Figure 1.
10. Across temperature and voltage ranges, includes output skew.
11. For a specific temperature and voltage, includes output skew.
AC Parameters
[6]
(V
DD
= 3.3V 5% or 2.5V 5%, V
DDC
= 3.3V 5% or 2.5V 5%, over the specified temperature range)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
200
MHz
Tpd
PECL_CLK to Q Delay
[7, 8]
V
DD
= 3.3V
2.0
3.5
4.0
ns
V
DD
= 2.5V
2.6
4.0
5.2
FoutDC
Output Duty Cycle
[7, 8, 9]
40
60
%
Tskew
Output-to-Output Skew
[7, 8]
200
ps
Tskew(pp)
Part-to-Part Skew
[10]
V
DD
= 3.3V
1.7
ns
V
DD
= 2.5V
2.2
Tskew(pp)
Part-to-Part Skew
[11]
1.0
ns
Tr/Tf
Output Clocks Rise/Fall
Time
[7, 8]
0.8V to 2.0V,
V
DD
= 3.3V
0.2
1.1
ns
0.5V to 1.8V,
V
DD
= 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
R
T
= 50 ohm
CY29943 DUT
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 1. PECL_CLK CY29943 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
t
PD
PECL_CLK
PECL_CLK
V
PP
Q
V
CMR
VCC
GND
VCC /2
Figure 2. Propagation Delay (TPD) Test Reference
CY29943
Document #: 38-07285 Rev. *C
Page 5 of 7
VCC
GND
VCC /2
t
P
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (FoutDC)
t
SK(0)
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 4. Output-to-Output Skew tsk(0)
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