2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer
CY29947
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07287 Rev. *C
Revised December 22, 2002
47
Features
2.5V or 3.3V operation
200-MHz clock support
LVCMOS-/LVTTL-compatible inputs
9 clock outputs: drive up to 18 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC947, MPC9447
Available in Industrial and Commercial temp. range
32-pin TQFP package
Description
The CY29947 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select one of two LVCMOS/LVTTL
compatible clock inputs. The two clock sources can be used
to provide for a test clock as well as the primary system clock.
All other control inputs are LVCMOS/LVTTL compatible. The 9
outputs are LVCMOS or LVTTL compatible and can drive 50
series or parallel terminated transmission lines.For series ter-
minated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:18. The out-
puts can also be three-stated via the three-state input TS#.
Low output-to-output skews make the CY29947 an ideal clock
distribution buffer for nested clock trees in the most demand-
ing of synchronous systems.
The CY29947 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
0
1
TCLK1
TCLK_SEL
SYNC_OE
TS#
VDD
VDDC
9
Q0-Q8
TCLK0
CY29947
VSS
VDDC
Q0
VSS
Q1
VDDC
Q2
VSS
VSS
VDDC
Q8
VSS
Q7
VDDC
Q6
VSS
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
CY29947
Document #: 38-07287 Rev. *C
Page 2 of 7
Note:
1.
PD = internal pull-down, PU = internal pull-up.
Output Enable/Disable
The CY29947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in Figure 1.
Pin Description
[1]
Pin
Name
PWR
I/O
Description
3
TCLK0
I, PU
Test Clock Input
4
TCLK1
I, PU
Test Clock Input
2
TCLK_SEL
I, PU
Test Clock Select Input. When LOW, TCLK0 is selected. When assert-
ed HIGH, TCLK1 is selected.
11, 13, 15, 19,
21, 23, 26, 28,
30
Q(8:0)
VDDC
O
Clock Outputs
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output buffers are
three-stated. When set HIGH, the output buffers are enabled.
10, 14, 18, 22,
27, 31
VDDC
3.3V or 2.5V Power Supply for Output Clock Buffers
7
VDD
3.3V or 2.5V Power Supply
1, 8, 9, 12, 16,
17, 20, 24, 25,
29, 32
VSS
Common Ground
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
CY29947
Document #: 38-07287 Rev. *C
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ 65C to + 150C
Operating Temperature: ................................ 40C to +85C
Maximum ESD protection ................................................ 2kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
Notes:
2.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3.
Inputs have pull-up/pull-down resistors that effect input current.
4.
Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
DC Parameters:
V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, Over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
V
SS
0.8
V
V
IH
Input High Voltage
2.0
V
DD
V
I
IL
Input Low Current
[3]
100
A
I
IH
Input High Current
[3]
10
A
V
OL
Output Low Voltage
[4]
I
OL
= 20 mA
0.4
V
V
OH
Output High Voltage
[4]
I
OH
= 20 mA, V
DD
= 3.3V
2.5
V
I
OH
= 20 mA, V
DD
= 2.5V
1.8
I
DDQ
Quiescent Supply
Current
5
7
mA
I
DD
Dynamic Supply
Current
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
120
mA
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
200
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
85
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
140
Zout
Output Impedance
V
DD
= 3.3V
12
15
18
V
DD
= 2.5V
14
18
22
C
in
Input Capacitance
4
pF
CY29947
Document #: 38-07287 Rev. *C
Page 4 of 7
Notes:
5.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6.
Outputs driving 50
transmission lines.
7.
50% input duty cycle.
8.
See Figure 2.
9.
Part-to-Part skew at a given temperature and voltage.
10. Set-up and hold times are relative to the falling edge of the input clock
AC Parameters
[5]
:
V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, Over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
[6]
V
DD
= 3.3V
200
MHz
V
DD
= 2.5V
170
Tpd
TCLK To Q Delay
[6]
V
DD
= 3.3V
4.75
9.25
ns
V
DD
= 2.5V
6.50
10.50
FoutDC
Output Duty Cycle
[6, 7]
Measured at V
DD
/2
45
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew
[6, 8]
150
250
ps
Tskew(pp)
Part-to-Part Skew
[9]
2.0
ns
Ts
Set-up Time
[6, 10]
SYNC_OE to TCLK
0.0
ps
Th
Hold Time
[6, 10]
TCLK to SYNC_OE
1.0
ps
Tr/Tf
Output Clocks Rise/Fall Time
[8]
0.8V to 2.0V,
V
DD
= 3.3V
0.20
1.0
ns
0.6V to 1.8V,
V
DD
= 2.5V
0.20
1.3
CY29947
Document #: 38-07287 Rev. *C
Page 5 of 7
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
R
T
= 50 ohm
R
T
= 50 ohm
CY29947 DUT
Figure 2. LVCMOS_CLK CY29947 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
t
PD
LVCMOS_CLK
Q
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 3. LVCMOS Propagation Delay (TPD) Test Reference
VCC
GND
VCC /2
t
P
T0
DC = tP / T0 x 100%
Figure 4. Output Duty Cycle (FoutDC)
t
SK(0)
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 5. Output-to-Output Skew tsk(0).
PDF 
ZIP