2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
CY29948
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07288 Rev. *B
Revised December 22, 2002
48
Features
2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC948, MPC948L, MPC9448
Available in Commercial and Industrial temp. range
32-pin TQFP package
Description
The CY29948 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The 12 outputs are LVCMOS or LVT-
TL compatible and can drive 50
series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:24. The outputs can also be three-stated
via the three-state input TS#. Low output-to-output skews
make the CY29948 an ideal clock distribution buffer for nested
clock trees in the most demanding of synchronous systems.
The CY29948 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
VDDC
12
Q0-Q11
CY29948
VSS
Q0
VDDC
Q1
VSS
Q2
VDDC
Q3
Q1
1
VDDC
Q1
0
VSS
Q9
VDDC
Q8
VSS
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
CY29948
Document #: 38-07288 Rev. *B
Page 2 of 7
Note:
1.
PD = Internal Pull-Down, PU = Internal Pull- UP
Output Enable/Disable
The CY29948 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in Figure 1.
Pin Description
[1]
Pin
Name
PWR
I/O
Description
3
PECL_CLK
I, PU
PECL Input Clock
4
PECL_CLK#
I, PD
PECL Input Clock
2
TCLK
I, PU
External Reference/Test Clock Input
9, 11, 13, 15,
17, 19, 21, 23,
25, 27, 29, 31
Q(11:0)
VDDC
O
Clock Outputs
1
TCLK_SEL
I, PU
Clock Select Input. When LOW, PECL clock is selected and when
HIGH TCLK is selected.
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output buffers
are three-stated. When set HIGH, the output buffers are enabled.
10, 14, 18, 22,
26, 30
VDDC
2.5V or 3.3V Power Supply for Output Clock Buffers
7
VDD
2.5V or 3.3V Power Supply
8, 12, 16, 20,
24, 28, 32
VSS
Common Ground
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
CY29948
Document #: 38-07288 Rev. *B
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ 65C to + 150C
Operating Temperature: ................................ 40C to +85C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
Notes:
2.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3.
Inputs have pull-up/pull-down resistors that effect input current.
4.
The V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the V
CMR
range and the input lies within the V
PP
specification.
5.
Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
DC Parameters:
V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, Over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
V
DD
= 3.3V, PECL_CLK single ended
1.49
1.825
V
V
DD
= 2.5V, PECL_CLK single ended
1.10
1.45
All other inputs
V
SS
0.8
V
IH
Input High Voltage
V
DD
= 3.3V, PECL_CLK single ended
2.135
2.42
V
V
DD
= 2.5V, PECL_CLK single ended
1.75
2.0
All other inputs
2.0
V
DD
I
IL
Input Low Current
[3]
100
A
I
IH
Input High Current
[3]
100
V
PP
Peak-to-Peak Input Voltage
PECL_CLK
300
1000
mV
V
CMR
Common Mode Range
[4]
PECL_CLK
V
DD
= 3.3V
V
DD
2.0
V
DD
0.6
V
V
DD
= 2.5V
V
DD
1.2
V
DD
0.6
V
OL
Output Low Voltage
[5]
I
OL
= 20 mA
0.4
V
V
OH
Output High Voltage
[5]
I
OH
= 20 mA, V
DD
= 3.3V
2.5
V
I
OH
= 20 mA, V
DD
= 2.5V
1.8
I
DDQ
Quiescent Supply
Current
5
7
mA
I
DD
Dynamic Supply
Current
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
180
mA
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
270
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
125
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
190
Zout
Output Impedance
V
DD
= 3.3V
12
15
18
V
DD
= 2.5V
14
18
22
C
in
Input Capacitance
4
pF
CY29948
Document #: 38-07288 Rev. *B
Page 4 of 7
Notes:
6.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7.
Outputs driving 50
transmission lines.
8.
50% input duty cycle.
9.
See Figures 2 and 3.
10. Setup and hold times are relative to the falling edge of the input clock
11. Part-to-Part skew at a given temperature and voltage.
AC Parameters
[6]
:
V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, Over the specified operating range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
[7]
V
DD
= 3.3V
200
MHz
V
DD
= 2.5V
170
Tpd
PECL_CLK to Q Delay
[7]
V
DD
= 3.3V
4.0
8.0
ns
TCLK to Q Delay
[7]
4.4
8.9
PECL_CLK to Q Delay
[7]
V
DD
= 2.5V
6.0
10.0
TCLK to Q Delay
[7]
6.4
10.9
FoutDC
Output Duty Cycle
[7, 8, 9]
Measured at V
DD
/2
45
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew
[7, 9]
150
250
ps
Tskew(pp)
Part-to-Part Skew
[11]
PECL_CLK to Q
1.5
ns
TCLK to Q
2.0
Ts
Set-up Time
[7, 10]
SYNC_OE to PECL_CLK
1.0
ns
SYNC_OE to TCLK
0.0
Th
Hold Time
[7, 10]
PECL_CLK to SYNC_OE
0.0
ns
TCLK to SYNC_OE
1.0
Tr/Tf
Output Clocks Rise/Fall Time
[9]
0.8V to 2.0V, V
DD
= 3.3V
0.20
1.0
ns
0.6V to 1.8V, V
DD
= 2.5V
0.20
1.3
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
R
T
= 50 ohm
R
T
= 50 ohm
CY29948 DUT
Figure 2. LVCMOS_CLK CY29948 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
R
T
= 50 ohm
CY29948 DUT
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 3. PECL_CLK CY29948 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
CY29948
Document #: 38-07288 Rev. *B
Page 5 of 7
t
PD
PECL_CLK
PECL_CLK
V
PP
Q
V
CMR
VCC
GND
VCC /2
Figure 4. Propagation Delay (TPD) Test Reference
t
PD
LVCMOS_CLK
Q
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 5. LVCMOS Propagation Delay (TPD) Test Reference
VCC
GND
VCC /2
t
P
T0
DC = tP / T0 x 100%
Figure 6. Output Duty Cycle (FoutDC)
t
SK(0)
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 7. Output-to-Output Skew tsk(0)
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