2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer
CY29949
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07289 Rev. *D
Revised November 6, 2003
Features
2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible outputs
15 clock outputs: drive up to 30 clock lines
1X and 1/2X configurable outputs
Output three-state control
350 ps max. output-to-output skew
Pin compatible with MPC949, MPC9449
Available in Commercial and Industrial temp. range
52-pin TQFP package
Description
The CY29949 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources can be used to provide for test clocks as well as the
primary system clocks. All other control inputs are
LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or
LVTTL compatible and can drive 50
series or parallel termi-
nated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
Block Diagram
Pin Configuration
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
NC
VDDC
QD4
VSS
QD3
VDDC
QD2
VSS
QD1
VDDC
QD0
VSS
NC
NC
VDDC
QB2
VSS
QB1
VDDC
QB0
VSS
VSS
QA1
VDDC
QA0
VSS
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29949
0
1
1
2
0
1
1
2
0
1
0
1
DSELA
DSELB
DSELC
DSELD
MR/OE#
1
2
1
2
0
1
0
1
2
3
4
6
QA(0:1)
QB(0:2)
QC(0:3)
QD(0:5)
PECL_SEL
TCLK_SEL
PECL_CLK
PECL_CLK#
R
R
R
R
CY29949
Document #: 38-07289 Rev. *D
Page 2 of 7
Note:
1. PD = internal pull-down, PU = internal pull-up.
Pin Description
[1]
Pin
Name
PWR
I/O
Description
6
PECL_CLK
I, PD PECL Input Clock
7
PECL_CLK#
I, PU PECL Input Clock
4, 5
TCLK(0,1)
I, PU External Reference/Test Clock Input
49, 51
QA(1,0)
VDDC
O
Clock Outputs
42, 44, 46
QB(2:0)
VDDC
O
Clock Outputs
31, 33, 35, 37 QC(3:0)
VDDC
O
Clock Outputs
16, 18, 20, 22,
24, 28
QD(5:0)
VDDC
O
Clock Outputs
9, 10, 11, 12
DSEL(A:D)
I, PD Divider Select Inputs. When HIGH, selects
2 input divider. When LOW,
selects
1 input divider.
2
TCLK_SEL
I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
8
PCLK_SEL
I, PD PECL Select Input. When HIGH, PECL clock is selected and when LOW
TCLK(0,1) is selected
1
MR/OE#
I, PD Output Enable Input. When asserted LOW, the outputs are enabled and
when asserted HIGH, internal flip-flops are reset and the outputs are
three-stated. If more than 1 bank is being used in /2 mode, a reset must
be performed (MR/OE# asserted high) after power-up to ensure that all
internal flip flops are set to the same state.
17, 21, 25, 32,
36, 41, 45, 50
VDDC
2.5V or 3.3V Power Supply for Output Clock Buffers
3
VDD
2.5V or 3.3V Power Supply
13, 15, 19, 23,
29, 30, 34, 38,
43, 47, 48, 52
VSS
Common Ground
14, 26, 27, 39,
40,
NC
Not Connected
CY29949
Document #: 38-07289 Rev. *D
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............ V
SS
0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ 65C to + 150C
Operating Temperature: ................................ 40C to +85C
Maximum ESD Protection............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
(V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, over the specified temperature range)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
V
DD
= 3.3V, PECL_CLK single ended
1.49
1.825
V
V
DD
= 2.5V, PECL_CLK single ended
1.10
1.45
All other inputs
V
SS
0.8
V
IH
Input High Voltage
V
DD
= 3.3V, PECL_CLK single ended
2.135
2.42
V
V
DD
= 2.5V, PECL_CLK single ended
1.75
2.0
All other inputs
2.0
V
DD
I
IL
Input Low Current
[3]
100
A
I
IH
Input High Current
[3]
100
V
PP
Peak-to-Peak Input Voltage
PECL_CLK
300
1000
mV
V
CMR
Common Mode Range
[4]
PECL_CLK
V
DD
= 3.3V
V
DD
2.0
V
DD
0.6
V
V
DD
= 2.5V
V
DD
1.2
V
DD
0.6
V
OL
Output Low Voltage
[5]
I
OL
= 20 mA
0.4
V
V
OH
Output High Voltage
[5]
I
OH
= 20 mA, V
DD
= 3.3V
2.5
V
I
OH
= 20 mA, V
DD
= 2.5V
1.8
I
DDQ
Quiescent Supply Current
5
7
mA
I
DD
Dynamic Supply Current
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
200
mA
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
330
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
140
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
235
Zout
Output Impedance
V
DD
= 3.3V
12
15
18
V
DD
= 2.5V
14
18
22
C
in
Input Capacitance
4
pF
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the V
CMR
range
and the input lies within the V
PP
specification.
5. Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
CY29949
Document #: 38-07289 Rev. *D
Page 4 of 7
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50
transmission lines.
8. 50% input duty cycle.
9. See Figures 1 and 2.
10. Part-to-Part skew at a given temperature and voltage.
AC Parameters
(V
DD
= V
DDC
= 3.3V 10% or 2.5V 5%, over the specified temperature range)
[6]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
[7]
V
DD
= 3.3V
200
MHz
V
DD
= 2.5V
170
Tpd
PECL_CLK to Q Delay
[7]
V
DD
= 3.3V
4.0
8.6
ns
TCLK to Q Delay
[7]
4.2
10.5
PECL_CLK to Q Delay
[7]
V
DD
= 2.5V
6.0
10.6
TCLK to Q Delay
[7]
6.2
10.5
FoutDC
Output Duty Cycle
[7, 8]
Measured at VDD/2
45
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew
[7, 9]
250
350
ps
Tskew(pp)
Part-to-Part Skew
[10]
PECL_CLK to Q
1.5
2.75
ns
TCLK to Q
2.0
4.0
Tr/Tf
Output Clocks Rise/Fall Time
[9]
0.8V to 2.0V,
V
DD
= 3.3V
0.10
1.0
ns
0.6V to 1.8V,
V
DD
= 2.5V
0.10
1.3
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
R
T
= 50 ohm
R
T
= 50 ohm
CY29949 DUT
Figure 1. LVCMOS_CLK CY29949 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
R
T
= 50 ohm
CY29949 DUT
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 2. PECL_CLK CY29949 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
CY29949
Document #: 38-07289 Rev. *D
Page 5 of 7
Ordering Information
Part Number
Package Type
Production Flow
CY29949AI
52 Pin TQFP
Industrial, 40C to +85C
CY29949AIT
52 Pin TQFP - Tape and Reel
Industrial, 40C to +85C
CY29949AC
52 Pin TQFP
Commercial, 0C to +70C
CY29949ACT
52 Pin TQFP - Tape and Reel
Commercial, 0C to +70C
t
PD
PECL_CLK
PECL_CLK
V
PP
Q
V
CMR
VCC
GND
VCC /2
Figure 3. Propagation Delay (TPD) Test Reference
t
PD
LVCMOS_CLK
Q
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
VCC
GND
VCC /2
t
P
T0
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (FoutDC)
t
SK(0)
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 6. Output-to-Output Skew tsk(0)
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