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1:10 Clock Fanout Buffer with Output Enable
COMLINKTM SERIES
CY2CC1810
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07055 Rev. *C
Revised December 14, 2002
Features
Low-voltage operation
V
DD
range from 2.5 to 3.3V
1:10 fanout
Drives either a 50-ohm or 75-ohm transmission line
Over voltage tolerant input hot swappable
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
High-speed operation > 200 MHz
LVTTL-/LVCMOS-compatible input
-- Output disable to three-state
Industrial versions available
Packages available include: SOIC/SSOP
Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching and eliminate the need for series-
damping resistors; they also reduce noise overall.
Block Diagram
Pin Configuration
OUTPUT
(AVCMOS)
OE#
IN
Q 5
Q 7
Q 6
Q 4
Q 1
Q 3
Q 2
Q 8
Q 9
Q 10
G N D
V D D
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 pin SOIC/SSOP
C
Y
2CC
1810
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
GND
Q10
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
VDD
Pin Description
Pin Number
Pin Name
Pin Description
1,7,8,12,13,17,20,24
G
ND
Ground
Power
3,10,15,22
V
DD
Power Supply
Power
5
OE#
Output Enable
LVTTL/LVCMOS
6
IN
Input
LVTTL/LVCMOS
2,4,9,11,14,16,18,19,21,23
Q10........Q1
Output
AVCMOS
COMLINKTM SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 2 of 8
Maximum Ratings
[1][2]
Storage Temperature: ................................ 65
C to + 150
C
Ambient Temperature:................................... 40
C to +85
C
Supply Voltage to Ground Potential
V
CC
.................................................................. 0.5V to 4.6V
Input ................................................................. 0.5V to 5.8V
Supply Voltage to Ground Potential
(Outputs only) ........................................ 0.5V to V
DD
+ 0.5V
DC Output Voltage................................. 0.5V to V
DD
+ 0.5V
Power Dissipation........................................................ 0.75W
DC Parameter
@ 3.3V V
DD
= 3.3V 5%, T
A
= 40
C to +85
C
(see Figure 6)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
OH
Output High Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= 12 mA
2.3
3.3
V
V
OL
Output Low Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA
0.2
0.5
V
V
IH
Input High Voltage
Guaranteed Logic High Level
2
5.8
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= 2.7V
1
uA
I
IL
Input Low Current
V
DD
= Max.
V
IN
= 0.5V
1
uA
I
I
Input High Current
V
DD
= Max., V
IN
=
V
DD
(Max)
20
uA
V
IK
Clamp Diode Voltage
V
DD
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OK
Continuous Clamp Current
V
DD
= Max., V
OUT
= GND
50
mA
O
OFF
Power-down Disable
V
DD
=
GND
,
V
OUT
= < 4.5V
100
uA
V
H
Input Hysteresis
80
mV
DC Parameter
@ 2.5V V
DD
= 2.5V 5%, T
A
= 40
C to +85
C (see Figure 1)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
OH
Output High Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= 7 mA
1.8
V
I
OH
= 12 mA
1.6
V
V
OL
Output Low Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA
0.65
V
V
IH
Input High Voltage
Guaranteed Logic High Level
1.6
5.0
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= 2.4V
1
uA
I
IL
Input Low Current
V
DD
= Max.
V
IN
= 0.5V
1
uA
I
I
Input High Current
V
DD
= Max., V
IN
= V
DD
(Max.)
20
uA
V
IK
Clamp Diode Voltage
V
DD
= Min., I
IN
= 18 mA
0.7
1.2
V
I
OK
Continuous Clamp Current
V
DD
= Max., V
OUT
= GND
50
mA
O
OFF
Power-down Disable
V
DD
= GND, V
OUT
= < 4.5V
100
uA
V
H
Input Hysteresis
80
mV
Capacitance
Symbol
Description
Test Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
2.5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
6.5
pF
Note:
1.
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
COMLINKTM SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 3 of 8
Power Supply Characteristics
(See Figure 1)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
ICC
Delta I
CC
Quiescent
Power Supply Current
(I
DD
@ V
DD
= Max. and V
IN
= V
DD
) (I
DD
@ V
DD
=
Max. and V
IN
= V
DD
0.6V)
50
uA
I
CCD
Dynamic Power Supply
Current
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
fL= fMAX
OE# = V
DD
0.63
mA/
MHz
I
C
Total Power Supply
Current
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open fL = 40 MHz
fL=100 MHz
OE# = GND
25
mA
High-frequency Parametrics
Parameter
Description
Test Conditions
Min.
Typ
Max
Unit
D
J
Jitter, Deterministic
50% duty cycle tW(5050)
The "point to point load circuit"
|Output Jitter Input Jitter|
See Figure 8
20
ps
F
max
Maximum frequency
V
DD
= 3.3V
50% duty cycle tW(5050)
Standard Load Circuit.
See Figure 6
160
MHz
50% duty cycle tW(5050)
The "point to point load circuit"
See Figure 8
200
F
max(20)
Maximum frequency
V
DD
= 3.3 V
20% duty cycle tW(2080)
The "point to point load circuit"
V
IN
= 3.0V/0.0V V
OUT
= 2.3V/0.4V
See Figure 8
200
MHz
Maximum frequency
V
DD
= 2.5 V
The "point to point load circuit"
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
See Figure 3
100
t
W
Minimum pulse
V
DD
= 3.3 V
The "point to point load circuit"
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
See Figure 7
2
ns
Minimum pulse
V
DD
= 2.5 V
The "point to point load circuit"
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
See Figure 2
1
AC Switching Characteristics
@ 3.3V V
DD
= 3.3V 5%, T
A
= 40
C to +85C (See Figure 6)
Parameter
Description
Min.
Typ.
Max.
Unit
t
PLH
Propagation Delay Low to High
See Figure 9
1.5
3
3.9
nS
t
PHL
Propagation Delay High to Low
1.5
3
3.9
nS
t
PHZ
Propagation Delay High to High Z
See Figure 10
4
nS
t
PLZ
Propagation Delay Low to High Z
3
nS
t
R
Output Rise Time
See Figure 9
0.8
V/nS
t
F
Output Fall Time
0.8
V/nS
t
SK(0)
Output Skew: Skew between outputs of the same package (in
phase)
See Figure 12
0.2
nS
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
t
PLH
)
See Figure 11
0.2
nS
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
See Figure 13
0.3
nS
t
OFF
Delay from OE to Driver Off
4.0
nS
t
ON
Delay from OE to Driver on
4.0
nS
COMLINKTM SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 4 of 8
Parameter Measurement Information: V
DD
@ 2.5V
[3,5,6
]
Notes:
3.
C
L
includes probe and jig capacitance.
4.
Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control.
5.
All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50
,
t
R
< 2.5 nS, t
F
< 2.5 nS.
6.
Outputs are measured one at a time with one transition per measurement.
7.
t
PLZ
and t
PHZ
are the same as t
DIS
.
8.
t
PZL
and t
PZH
are the same as t
EN
.
9.
t
PLH
and t
PHL
are the same as t
PD
.
AC Switching Characteristics
@ 2.5V V
DD
= 2.5V 5%, T
A
= 40
C to +85
C (See Figure 1)
Parameter
Description
Min.
Typ.
Max. Unit
t
PLH
Propagation Delay Low to High
See Figure 4
1.5
3.8
3.5
nS
t
PHL
Propagation Delay High to Low
1.5
3.8
3.5
nS
t
PHZ
Propagation Delay High to High Z
See Figure 5
5
nS
t
PLZ
Propagation Delay Low to High Z
4
nS
t
R
Output Rise Time
See Figure 4
0.4
V/nS
t
F
Output Fall Time
0.6
V/nS
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase) See Figure 12
0.2
nS
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
t
PLH
)
See Figure 11
0.2
nS
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
See Figure 13
0.3
nS
t
OFF
Delay from OE to Driver Off
5.0
nS
t
ON
Delay from OE to Driver on
5.0
nS
From O utput
Under Test
C
L
= 50 pF
500 ohm
V
SS
Open
2x VDD
500 ohm
Figure 1. Load Circuit
2.5 V
0 V
Input
t
w(20-80)
2.5 V
0 V
1.25 V
1.25 V
Input
t
w(50-50)
1.25 V
Figure 2. Voltage WaveformsPulse Duration
From Output
Under Test
C
L
= 3 pF
500 ohm
Figure 3. Point-to-Point Load Circuit
Table 1.
Test
S1
t
PLH
/t
PHL
Open
See Figure 4
t
PLZ
/t
PZL
2 V
DD
See Figure 5
t
PHZ
/t
PZH
V
SS
1.25 V
1.25 V
1.25 V
1.25 V
t
PLH
t
PHL
2.5 V
V
OH
V
OL
0 V
Input
Output
Figure 4. Voltage WaveformsPropagation Delay Times
[9]
Output Control
(low-level enabling)
Waveform 1
S1 at 2 x VDD
2.5 V
Waveform 2
S1 at GND
2.5 V
t
PLZ
t
PHZ
t
PZH
t
PZL
1.25 V
1.25V
0 V
~0 V
V
OL
+ 0.3V
V
OH
- 0.3V
V
OL
V
OH
Z
Z
1.25 V
VOH (min)
VOL
(max)
Figure 5. Voltage Waveforms
Enable and Disable Times
[4,7,8]
COMLINKTM SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 5 of 8
Parameter Measurement Information
:
V
DD
@ 3.3V
[10,12,13]
Notes:
10. C
L
includes probe and jig capacitance
11. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH, except when disabled by the output control.
12. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50
,
t
R
< 2.5 nS, t
F
< 2.5 nS.
13. The outputs are measured one at a time with one transition per measurement.
14. t
PLZ
and t
PHZ
are the same as t
DIS
.
15. t
PZL
and t
PZH
are the same as t
EN
.
16. tPLH and tPHL are the same as t
PD
.
From Output
Under Test
C
L
= 50 pF
500 ohm
V
SS
Open
2x VDD
500 ohm
Figure 6. Load Circuit
2.7 V
0 V
Input
t
w(20-80)
2.7 V
0 V
1.5 V
1.5 V
Input
t
w(50-50)
1.5 V
Figure 7. Voltage WaveformsPulse Duration
From Output
Under Test
C
L
= 3 pF
500 ohm
Figure 8. Point-to-Point Load Circuit
Table 2.
Test
S1
t
PLH
/t
PHL
Open
See Figure 9
t
PLZ
/t
PZL
2xVDD
See Figure 10
t
PHZ
/t
PZH
VSS
1.5 V
1.5 V
1.5 V
1.5 V
t
PLH
t
PHL
1.5 V
V
OH
V
OL
0 V
Input
Output
Figure 9. Voltage Waveforms
Propagation Delay Times
[16]
Output Control
(low-level enabling)
Waveform 1
S1 at 2 x VDD
3 V
Waveform 2
S1 at GND
3.3 V
t
PLZ
t
PHZ
t
PZH
t
PZL
1.5 V
1.5V
0 V
~0 V
V
OL
+ 0.3V
V
OH
- 0.3V
V
OL
V
OH
Z
Z
1.5 V
VOH (min)
VOL
(max)
Figure 10. Voltage Waveforms
Enable and Disable Times
[11,14,15]
INPUT
OUTPUT
t
PLH
t
PHL
tsk
(P)
=
l
t
PHL
- t
PLH
l
3V
1.5V
0V
VOH
1.5V
VOL
Figure 11. Pulse Skewtsk
(p)
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