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64K x 16 Static RAM
CY62126BV
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 14, 2000
Features
2.7V3.6V operation
CMOS for optimum speed/power
Low active power (70 ns, LL version)
-- 54 mW (max.) (15 mA)
Low standby power (70 ns, LL version)
-- 54
W (max.) (15
A)
Automatic power-down when deselected
Independent control of Upper and Lower Bytes
Available in 44-pin TSOP II (forward) and fBGA
Functional Description
The CY62126BV is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16
. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62126BV is available in standard 44-pin TSOP Type II
(forward pinout) and fBGA packages.
Logic Block Diagram
Pin Configurations
64K x 16
RAM Array
I/O
1
I/O
8
ROW
DE
CODE
R
A
10
A
9
A
7
A
6
A
3
A
0
COLUMN DECODER
A
5
A
8
A
13
A
14
A
15
1024 X 1024
SEN
SE
AM
PS
DATA IN DRIVERS
OE
A
2
A
1
I/O
9
I/O
16
CE
WE
BLE
BHE
A
4
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
A
4
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
A
11
A
12
62126BV1
62126BV2
CY62126BV
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied ............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
.....................................0.5V to V
CC
+0.5V
DC Input Voltage
[1]
..................................0.5V to V
CC
+0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "Instant On" case temperature.
Pin Configurations
(continued)
fBGA
Selection Guide
CY62126BV-55
CY62126BV-70
Units
Maximum Access Time
55
70
ns
Maximum Operating Current
20
15
mA
Maximum CMOS Standby Current
15
15
A
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
I/O
11
I/O
9
I/O
10
A
4
A
5
I/O
12
I/O
14
I/O
13
I/O
15
I/O
16
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
1
BHE
NC
NC
A
2
A
1
BLE
V
CC
I/O
3
I/O
2
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
A
15
A
14
A
13
A
12
NC
NC
NC
NC
62126BV3
3
2
6
5
4
1
D
E
B
A
C
F
G
H
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Industrial
40
C to +85
C
2.7V3.6V
CY62126BV
3
Electrical Characteristics
Over the Operating Range
Test Conditions
62126BV
Parameter
Description
Min.
Typ.
[3]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1.0 mA
2.2
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+
0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.4
V
I
IX
Input Load Current
GND
V
I
V
CC
1
+1
A
I
OZ
Output Leakage Current
GND
V
I
V
CC
,
Output Disabled
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
55 ns
20
mA
70 ns
15
mA
I
SB1
Automatic CE
Power-Down Current
-- TTL Inputs
Max. V
CC
, CE
V
IH
V
IN
V
IH
or
V
IN
V
IL
, f = f
MAX
2
mA
I
SB2
Automatic CE
Power-Down Current
-- CMOS Inputs
Max. V
CC
,
CE
V
CC
0.3V,
V
IN
V
CC
0.3V,
or V
IN
0.3V, f=0
0.5
15
A
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 3.3V
9
pF
C
OUT
Output Capacitance
9
pF
AC Test Loads and Waveforms
Notes:
3.
Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal
conditions (T
A
= 25
C, V
CC
=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested.
4.
Tested initially and after any design or process changes that may affect these parameters.
62126BV-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.0V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.0V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R1 1076
R2
1262
R2
581
Equivalent to:
THVENIN
EQUIVALENT
1.62V
R1 1076
1262
Rise TIme:
1 V/ns
Fall TIme
1 V/ns
CY62126BV
4
Switching Characteristics
[5]
Over the Operating Range
62126BV55
62126BV70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low Z
[7]
5
5
ns
t
HZOE
OE HIGH to High Z
[6, 7]
20
25
ns
t
LZCE
CE LOW to Low Z
[7]
10
10
ns
t
HZCE
CE HIGH to High Z
[6, 7]
20
25
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
55
70
ns
t
DBE
Byte Enable to Data Valid
25
35
ns
t
LZBE
Byte Enable to LOW Z
[7]
5
5
ns
t
HZBE
Byte Disable to HIGH Z
[6,7]
20
25
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-Up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
50
ns
t
SD
Data Set-Up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
5
5
ns
t
HZWE
WE LOW to High Z
[6,7]
25
25
ns
t
BW
Byte Enable to End of Write
45
60
ns
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6.
t
HZOE
, t
HZCE
, t
HZWE
, and t
HZBE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZWE
is less than t
LZWE
, and t
HZBE
is less than t
LZBE
, for any given device.
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for
further conditions from BHE and BLE.
CY62126BV
5
Data Retention Characteristics
(Over the Operating Range for "L" and "LL" version only)
Parameter
Description
Conditions
[9]
Min.
Typ
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
3.6
V
I
CCDR
Data Retention Current
V
CC
=V
DR
=2.0V,
CE
V
CC
0.3V,
V
IN
V
CC
0.3V or,
V
IN
0.3V
0.5
15
A
t
CDR
[4]
Chip Deselect to Data Retention Time
0
ns
t
R
Operation Recovery Time
t
RC
ns
Data Retention Waveform
Switching Waveforms
Read Cycle No.1
[10, 11]
Read Cycle No. 2 (OE Controlled)
[11, 12, 13]
Notes:
9.
No input may exceed V
CC
+ 0.3V.
10. Device is continuously selected. OE, CE, BHE, BLE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = V
IH
or BHE and BLE = V
IH
.
62126BV5
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
62126BV-6
ADDRESS
DATA OUT
62126BV-7
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
OE
DATA OUT
SUPPLY
CURRENT
BHE, BLE
I
CC
I
SB
HIGH
IMPEDANCE
ADDRESS
t
LZBE
t
DBE
t
HZBE
CE
V
CC
CY62126BV
6
Write Cycle No. 1 (CE Controlled)
[13, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[13,14]
Notes:
14. If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
62126BV-8
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
CE
ADDRESS
WE
DATA I/O
BHE, BLE
t
BW
62126BV-9
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 15
BHE, BLE
t
BW
CY62126BV
7
Write Cycle No.3 (WE Controlled, OE LOW)
[13, 14]
Switching Waveforms
(continued)
62126BV-10
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATAI/O
NOTE 15
BHE, BLE
t
BW
Truth Table
CE
OE
WE
BLE
BHE
I/O
1
I/O
8
I/O
9
I/O
16
Mode
Power
H
X
X
X
X
High Z
High Z
Power Down
Standby (I
SB
)
L
L
H
L
L
Data Out
Data Out
Read All bits
Active (I
CC
)
L
L
H
L
H
Data Out
High Z
Read Lower bits only
Active (I
CC
)
L
L
H
H
L
High Z
Data Out
Read Upper bits only
Active (I
CC
)
L
X
L
L
L
Data In
Data In
Write All bits
Active (I
CC
)
L
X
L
L
H
Data In
High Z
Write Lower bits only
Active (I
CC
)
L
X
L
H
L
High Z
Data In
Write Upper bits only
Active (I
CC
)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (I
CC
)
CY62126BV
8
Document #: 38-00584-**
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
55
CY62126BVLL-55ZI
Z44
44-Lead TSOP II
Industrial
CY62126BVLL-55BAI
BA48
48-ball Fine Pitch Ball Grid Array
70
CY62126BVLL-70ZI
Z44
44-Lead TSOP II
CY62126BVLL-70BAI
BA48
48-ball Fine Pitch Ball Grid Array
Package Diagrams
44-Pin TSOP II Z44
51-85087-A
CY62126BV
Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-C
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