38-05230.fm
1 Mb (64K x 16) Static RAM
CY62126DV30
MoBL
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05230 Rev. *A
Revised June 13, 2003
Features
Very high speed: 55 ns
Wide voltage range: 2.2V to 3.6V
Pin compatible with CY62126BV
Ultra-low active power
-- Typical active current: 0.5 mA @ f = 1 MHz
-- Typical active current: 5 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Functional Description
[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life
(MoBL
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable
(CE) HIGH. The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected Chip En-
able (CE) HIGH, outputs are disabled (OE HIGH), both Byte
High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH) or during a write operation (Chip Enable (CE) LOW and
Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) LOW and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/Oh A
15
). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location speci-
fied on the address pins (A
0
th
Reading from the device is accomplished by taking Chip En-
able (CE) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then O
7
. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. See the truth table at the
back of this data sheet for a complete description of re
Note:
1.
For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
I/O
0
I/O
7
ROW
DE
CODE
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 x 512
S
E
N
S
E AM
P
S
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
I/O
15
CE
WE
BLE
BHE
A
0
A
1
A
9
A
10
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 2 of 11
Pin Configuration
[2,3]
Notes:
2.
NC pins are not connected to the die.
3.
E3 (DNU) can be left as NC or Vss to ensure proper operation. (Expansion Pins E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC
DNU
V
CC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
A
4
A
3
OE
V
SS
A
5
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
NC
A
1
A
0
18
17
20
19
I/O
3
27
28
25
26
22
21
23
24
NC
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
6
A
7
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage to Ground
Potential ...........................................
-
0.3V to V
CCMAX
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[4]
....................................
-
0.3V to V
CC
+ 0.3V
DC Input Voltage
[4]
................................
-
0.3V to V
CC
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Range
Ambient Temper-
ature (T
A
)
V
CC
[5]
Industrial
-
40
o
C to +85
o
C
2.2V to 3.6V
Product Portfolio
Product
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating, Icc (mA)
Standby, I
SB2
(
A)
f = 1 MHz
f = f
MAX
Min.
Typ.
Max.
Typ.
[6]
Max.
Typ.
[6]
Max.
Typ.
[6]
Max.
CY62126DV30L
2.2
3.0
3.6
55
0.5
1.5
5
10
1.5
5
CY62126DV30LL
55
0.5
1.5
5
10
1.5
4
DC Electrical Characteristics
(Over the Operating Range)
Parameter
Description
Test Conditions
CY62126DV30-55
Unit
Min.
Typ.
[6]
Max.
V
OH
Output HIGH Voltage
2.2 < V
CC
< 2.7
I
OH
=
-
0.1 mA
2.0
V
2.7 < V
CC
< 3.6
I
OH
=
-
1.0 mA
2.4
V
OL
Output LOW Voltage
2.2 < V
CC
< 2.7
I
OL
= 0.1 mA
0.4
V
2.7 < V
CC
< 3.6
I
OL
= 2.1 mA
0.4
V
IH
Input HIGH Voltage
2.2 < V
CC
< 2.7
1.8
V
CC
+ 0.3
V
2.7 < V
CC
< 3.6
2.2
V
CC
+ 0.3
V
IL
Input LOW Voltage
2.2 < V
CC
< 2.7
-
0.3
0.6
V
2.7 < V
CC
< 3.6
-
0.3
0.8
I
IX
Input Leakage Current
GND < V
I
< V
CC
-
1
+1
A
I
OZ
Output Leakage Current
GND < V
O
< V
CC
, Output Disabled
-
1
+1
A
I
CC
V
CC
Operating Supply Cur-
rent
f = f
MAX
= 1/t
RC
Vcc = 3.6V,
I
OUT
= 0 mA,
CMOS level
5
10
mA
f = 1 MHz
0.5
1.5
I
SB1
Automatic CE Power-down
Current
-
CMOS Inputs
CE > V
CC
-
0.2V,
V
IN
> V
CC
-
0.2V, V
IN
< 0.2V,
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
L
1.5
5
A
LL
1.5
4
I
SB2
Automatic CE Power-down
Current
-
CMOS Inputs
CE > V
CC
-
0.2V,
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=3.6V
L
1.5
5
A
LL
1.5
4
Notes:
4.
V
IL(min.)
=
-
2.0V for pulse durations less than 20 ns., V
IH(max.)
= Vcc
+
0.75V for pulse durations less than 20 ns.
5.
Full device Operation Requires linear Ramp of Vcc from 0V to Vcc(min) & Vcc must be stable at Vcc(min) for 500
s.
6.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25C.
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 4 of 11
AC Test Loads and Waveforms
Data Retention Waveform
Notes:
7.
Tested initially and after any design or proces changes that may affect these parameters.
8.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
>100 us.
Capacitance
[8]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
TA = 25C, f = 1 MHz
V
CC
= V
CC(typ)
8
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Parameter
Description
Test Conditions
TSOP
FBGA
Unit
JA
Thermal Resistance (Junction to Ambient)
[7]
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
55
76
C/W
JC
Thermal Resistance (Junction to Case)
[7]
12
11
C/W
Data Retention Characteristics
Parameter
Description
Conditions
Min.
Typ.
[6]
Max.
Unit
V
DR
V
CC
for Data Retention
1.5
V
I
CCDR
Data Retention Current
V
CC
=1.5V, CE > V
CC
-
0.2V,
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V
L
4
A
LL
3
t
CDR
[7]
Chip Deselect to Data Reten-
tion Time
0
ns
t
R
[8]
Operation Recovery Time
100
s
V
CC
Typ
V
CC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
THVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
L
Parameters
3.0V (2.7 3.6V)
Unit
R1
1103
R2
1554
R
TH
645
V
TH
1.75
V
2.5V (2.2 2.7V)
16600
15400
8000
1.2
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CE
V
CC
V
CC(min.)
V CC(min.)
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 5 of 11
Switching Characteristics
(Over the Operating Range)
[9]
Parameter
Description
CY62126DV30-55
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[10]
5
ns
t
HZOE
OE HIGH to High Z
[10,11]
20
ns
t
LZCE
CE LOW to Low Z
[10]
10
ns
t
HZCE
CE HIGH to High Z
[10,11]
20
ns
t
PU
CE LOW to Power-up
0
ns
t
PD
CE HIGH to Power-down
55
ns
t
DBE
BLE/BHE LOW to Data Valid
25
ns
t
LZBE
BLE/BHE LOW to Low Z
[10]
5
ns
t
HZBE
BLE/BHE HIGH to High-Z
[10,11]
20
ns
Write Cycle
[12]
t
WC
Write Cycle Time
55
ns
t
SCE
CE LOW to Write End
40
ns
t
AW
Address Set-up to Write End
40
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-up to Write Start
0
ns
t
PWE
WE Pulse Width
40
ns
t
BW
BLE/BHE LOW to Write End
40
ns
t
SD
Data Set-up to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[10,11]
20
ns
t
LZWE
WE HIGH to Low Z
[10]
10
ns
Notes:
9.
Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
OL
.
10. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t.
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signal.
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13,14]
Read Cycle No. 2 (OE Controlled)
[14,15]
Notes:
13. Device is continuously selected. OE, CE = V
IL
, BHE, BLE = V
IL
.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
OE
DATA OUT
SUPPLY
CURRENT
BHE, BLE
I
CC
I
SB
HIGH
IMPEDANCE
ADDRESS
t
LZBE
t
DBE
t
HZBE
CE
V
CC
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 7 of 11
Write Cycle No. 1 (WE Controlled)
[11,12,
16, 17, 18]
Write Cycle No. 2 (CE Controlled)
[11,12,
16, 17, 18]
Notes:
16. Data I/O is high-impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
t
BW
DON'T CARE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
BHE / BLE
t
BW
t
SA
DON'T CARE
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW)
[17, 18]
Write Cycle No. 4 (BHE</>/BLE</> Controlled, OE</> LOW)</>
[17, 18]</>
Switching Waveforms
(continued)
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
t
BW
BHE/BLE
DON'T CARE
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
VALID
t
BW
BHE/BLE
t
SCE
t
PWE
DON'T CARE
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 9 of 11
Truth Table
CE
OE
WE
BLE
BHE
I/O
0
I/O
7
I/O
8
I/O
15
Mode
Power
H
X
X
X
X
High Z
Power Down
Standby (I
SB
)
L
L
H
L
L
Data Out
Read All bits
Active (I
CC
)
L
L
H
L
H
Read Lower bits only
Active (I
CC
)
L
L
H
H
L
Read Upper bits only
Active (I
CC
)
L
X
L
L
L
Write All bits
Active (I
CC
)
L
X
L
L
H
Write Lower bits only
Active (I
CC
)
L
X
L
H
L
Write Upper bits only
Active (I
CC
)
L
H
H
X
X
Selected, Outputs Disabled
Active (I
CC
)
Data Out
High Z
High Z
High Z
Data In
Data In
High Z
High Z
High Z
High Z
Data Out
Data Out
Data In
Data In
L
X
X
H
H
High Z
High Z
Output Disabled
Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
55
CY62126DV30L-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
CY62126DV30LL-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-55ZI
Z44
44-Lead TSOP Type II
CY62126DV30LL-55ZI
Z44
44-Lead TSOP Type II
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
CY62126DV30
MoBL
PRELIMINARY
Document #:
38-05230 Rev. *A
Page 10 of 11
Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
44-pin TSOP II Z44
51-85087-*A
CY62126DV30
MoBL
PRELIMINARY
Document #:38-05230 Rev.*A
Page 11 of 11
Document History Page
Document Title: CY62126DV30 MoBL
1 Mb (64K x 16) Static RAM
Document Number: 38-05230
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
117689
08/27/02
JUI
New Data Sheet
*A
127313
06/13/03
MPR
Changed From Advanced Status to Preliminary.
Changed Isb2 to 5 uA (L), 4 uA (LL)
Changed Iccdr to 4 uA (L), 3 uA (LL)
Changed Cin from 6 pF to 8 pF
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