/home/web/htmldatasheet/RUSSIAN/html/cypress/169343
1M
(
64K
x
16
) Static RAM
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #:
38-05301
Rev.
**
Revised September 30, 2002
Features
Very h
igh speed:
55 ns
Wide v
oltage range:
1.65
V
to
2.2
V
Ultra-low active power
-- Typical active current:
0.5
mA
@ f = 1 MHz
-- Typical active current:
3.75
mA
@ f = f
MAX
Ultra-low standby power
Easy memory expansion with
CE
1
, CE
2
, and OE fea-
tures
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA and a 44-pin TSOP
Type II
Functional Description
[1]
The CY62127DV20 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device f
eatures ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life
(MoBL
) in portable
applications such as cellular telephones. T
he device al
so has
an automatic power-down feature that significantly reduces
power consumption by
99%
when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected
Chip Enable 1
(CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW
or both BHE
and
BLE are HIGH. The input/output pins (
I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected
Chip En-
able 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW, outputs are
disabled (OE HIGH),
both Byte High Enable and Byte Low
Enable are disabled (BHE
, BLE HIGH) or during a write oper-
ation (
Chip Enable 1 (CE
1
) LOW and Chip Enable 2 (CE
2
)
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then da
s
pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the loca-
tion specified on the ad
dress pins (A0 through A15).
Reading from the device is accomplished by taking Chip En-
able 1 (CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable
(BLE) is low, then data from the memory
location specified by the address pins will appear on I/O
0
to
I/O
7
. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O
8
to I/O
15
. See the truth table at the back
of this data sheet for a complete description of re
ad and write
modes.
Note:
1.
For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
64K 16
RAM ARRAY
I/O
0
I/O
7
ROW
DE
C
ODE
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 x 32 x 16
S
E
NS
E AM
P
S
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
I/O
15
WE
BLE
BHE
A
0
A
1
A
9
A
10
Power-down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
Logic Block Diagram
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 2 of 12
Pin Configuration
[2]
Note:
2. DNU pins are to be connected to V
SS
or left open.
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
A
4
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BH E
CE
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
DNU
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
S S
A
9
A
8
OE
V
S S
A
7
I/O
0
B H E
A
2
A
1
B L E
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
DNU
V
CC
1
CE
2
DNU
DNU
DNU
DNU
DNU
2
1
NU
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage to Ground Potential
.........................................................
-
0.2V to V
CCMAX
+
0.2
V
DC Voltage Applied to Outputs
in High-Z State
[
3
]
....................................
-
0.2V to
V
CC
+ 0.2V
DC Input Voltage
[
3
]
................................
-
0.2V to
V
CC
+ 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Product Portfolio
Range
Ambient
Temperature (T
A
)
V
CC
Industrial
-
40
C to +85
o
C
1.65V to 2.2V
Product
V
CC
Range(V)
Speed
(ns)
Power Dissipation
Operating, Icc (mA)
Standby, I
SB2
(
A)
f = 1 MHz
f = f
MAX
Min.
Typ.
[4]
Max.
Typ.
[4]
Max.
Typ.
[4]
Max.
Typ.
[4]
Max.
CY62127DV20L
1.65
1.8
2.2
55
0.5
1
3.75
7.5
0.5
4
CY62127DV20LL
55
3.75
7.5
0.5
2.5
Notes:
3. V
IL(min.)
=
-
2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25C.
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 4 of 12
DC Electrical Characteristics
(Over the Operating
Range)
Capacitance
[5]
Thermal Resistance
Parameter
Description
Test Conditions
CY62127DV20-55
Unit
Min.
Typ.
[4]
Max.
V
OH
Output HIGH Voltage
I
OH
=
-
0.1 mA
V
CC
= 1.65V
1.4
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
V
CC
= 1.65V
0.2
V
V
IH
Input HIGH Voltage
1.4
V
CC
+
0.2
V
V
IL
Input LOW Voltage
0.2
0.4
V
I
IX
Input Leakage Current
GND < V
I
< V
CC
1
+1
A
I
OZ
Output Leakage Current
GND < V
O
< V
CC
, Output Disabled
1
+1
A
I
CC
V
CC
Operating Supply Cur-
rent
f = f
MAX
= 1/t
RC
Vcc = 2.2V, I
OUT
= 0mA, CMOS
level
3.75
7.5
mA
f = 1 MHz
0.5
1
I
SB1
Automatic CE Power-down
Current
-
CMOS Inputs
CE
1
> V
CC
-
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
-
0.2V, V
IN
< 0.2V, f =
f
MAX
(Address and Data Only), f
= 0 (OE, WE, BHE and BLE)
L
0.5
4
A
LL
0.5
2.5
I
SB2
Automatic CE Power-down
Current
-
CMOS Inputs
CE
1
> V
CC
-
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V, f
= 0, V
CC
=2.2V
L
0.5
4
A
LL
0.5
2.5
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
TA = 25C, f = 1 MHz
V
CC
= V
CC(typ)
6
pF
C
OUT
Output Capacitance
8
pF
Parameter
Description
Test Conditions
BGA
Unit
JA
Thermal Resistance (Junction to
Ambient)
[5]
Still Air, soldered on a 3 x 4.5 inch, two-layer
printed circuit board
55
C/W
JC
Thermal Resistance (Junction to
Case)
[5]
16
C/W
Note:
5.
Tested initially and after any design or proces changes that may affect these parameters.
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 5 of 12
AC Test Loads and Waveforms
Data Retention Characteristics
Data Retention Waveform
[7]
Notes:
6. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
s or stable at V
CC(min.)
> 100
s.
7.
BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both.
Parameter
Description
Conditions
Min.
Typ.
[4]
Max.
Unit
V
DR
V
CC
for Data Retention
1
2.2
V
I
CCDR
Data Retention Current
V
CC
= 1V, CE
1
> V
CC
-
0.2V, CE
2
<
0.2V, V
IN
> V
CC
-
0.2V or V
IN
< 0.2V
L
1
A
LL
TBD
t
CDR
[5]
Chip Deselect to Data Reten-
tion Time
0
ns
t
R
[6]
Operation Recovery Time
t
RC
ns
V
CC
Typ
V
CC
UTPUT
R2
C = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
Equivalent to:
THVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
L
Parameters
1.8V
UNIT
R 1
1350 0
R 2
1080 0
R
T H
6000
V
T H
0.80
V
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 1.0V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE .BLE
CE
2
or
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 6 of 12
Switching Characteristics
(Over the Operating Range)
[
8
]
Parameter
Description
CY62127DV20-55
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW or CE
2
HIGH to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[9]
5
ns
t
HZOE
OE HIGH to High Z
[9,11]
20
ns
t
LZCE
CE
1
LOW or CE
2
HIGH to Low Z
[9]
10
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High Z
[9,11]
20
ns
t
PU
CE
1
LOW or CE
2
HIGH to Power-up
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power-down
55
ns
t
DBE
BLE/BHE LOW to Data Valid
55
ns
t
LZBE
[10]
BLE/BHE LOW to Low Z
[9]
5
ns
t
HZBE
BLE/BHE HIGH to High-Z
[9,11]
20
ns
Write Cycle
[12]
t
WC
Write Cycle Time
55
ns
t
SCE
CE
1
LOW or CE
2
HIGH to Write End
45
ns
t
AW
Address Set-up to Write End
45
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-up to Write Start
0
ns
t
PWE
WE Pulse Width
40
ns
t
BW
BLE/BHE LOW to Write End
45
ns
t
SD
Data Set-up to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[9,11]
20
ns
t
LZWE
WE HIGH to Low Z
[9]
10
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[
13
,
14
]
Notes:
8.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ.)/2
, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
9.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
10.
If both byte enables are toggled together, this value is 10 ns.
11.
t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12.
The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
ADDRESS
ATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 7 of 12
Read Cycle No. 2 (OE Controlled)
[
14
,
15
]
Write Cycle No. 1 (WE Controlled)
[
12,
16, 17, 18
]
Notes:
13.
Device is continuously selected. OE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, CE
2<Def>
14.
WE
is HIGH for Read cycle.
15.
Address valid prior to or coincident with CE
1
, BHE, BLE transition LOW and CE
2
transition HIGH.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
t
t
t
t
t
HIGH IMPEDANCE
t
t
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE2
VCC
SUPPLY
CURRENT
t
BHE
/
BLE
t
t
DATA OUT
t
RC
ACE
PD
HZCE
HZBE
HZOE
LZBE
DOE
LZOE
LZCE
DBE
PU
t
t
t
t
t
t
t
t
t
DATA
IN
VALID
CE1
ADDRESS
CE2
WE
ATA I/O
OE
BHE /BLE
t
DON'T CARE
WC
SCE
SA
AW
PWE
HA
BW
HD
SD
HZOE
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 8 of 12
Write Cycle No. 2 (
CE
1
or CE
2
Controlled)
[
12,
16, 17, 18
]
Write Cycle No. 3 (WE Controlled, OE LOW)
[
17, 18
]
Notes:
16. Data I/O is high-impedance if OE
= V
IH
.
17. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
t
t
t
t
t
t
t
t
DATA
IN
VALID
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
BHE /BLE
t
t
DON'T CARE
WC
SCE
HA
AW
SA
PWE
BW
SD
HD
HZOE
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
1
ADDRESS
CE
2
WE
DATA I/O
DON'T CARE
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 9 of 12
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[17]
Switching Waveforms
(continued)
DATA I/O
ADDRESS
t
t
t
t
t
t
CE
1
WE
DATA
IN
VALID
t
BHE /BLE
t
CE
2
t
DON'T CARE
WC
SCE
AW
HA
PWE
SA
HD
SD
BW
Truth Table
CE
1
CE
2
WE
OE
BHE
BLE
Input / Outputs
Mode
Power
H
X
X
X
X
X
High Z
Deselect/Power-down
Standby(I
SB
)
X
L
X
X
X
X
High Z
Deselect/Power-down
Standby(I
SB
)
X
X
X
X
H
H
High Z
Deselect/Power-down
Standby(I
SB
)
L
H
H
L
L
L
Data Out(I/O0 I/O15)
Read
Active(I
CC
)
L
H
H
L
H
L
Data Out(I/O0 I/O7);
High Z
(I/O8 I/O15)
Read
Active(I
CC
)
L
H
H
L
L
H
High Z
(I/O0 I/O7);
Data Out(I/O8 I/O15)
Read
Active(I
CC
)
L
H
H
H
L
H
High Z
Output Disabled
Active(I
CC
)
L
H
H
H
H
L
High Z
Output Disabled
Active(I
CC
)
L
H
H
H
L
L
High Z
Output Disabled
Active(I
CC
)
L
H
L
X
L
L
Data In (I/O0 I/O15)
Write
Active(I
CC
)
L
H
L
X
H
L
Data In (I/O0 I/O7);
High Z
(I/O8 I/O15)
Write
Active(I
CC
)
L
H
L
X
L
H
High Z
(I/O0 I/O7);
Data In (I/O8 I/O15)
Write
Active(I
CC
)
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 10 of 12
Ordering Information
Package Diagrams
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
55
CY62127DV20L-55BVI
BV48A
48-ball Fine Pitch BGA (6mm x 8mm x 1mm)
Industrial
CY62127DV20LL-55BVI
BV48A
48-ball Fine Pitch BGA (6mm x 8mm x 1mm)
CY62127DV20L-55ZI
Z44
44-lead TSOP Type II
CY62127DV20LL-55ZI
Z44
44-lead TSOP Type II
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 11 of 12
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
44-pin TSOP II Z44
51-85087-A
CY62127DV20
MoBL2
ADVANCE
INFORMATION
Document #:
38-05301
Rev.
**
Page 12 of 12
Document History Page
Document Title:
CY62127DV20
MoBL2
1M
(
64K
x
16
) Static RAM
Document Number:
38-05301
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
116568
10/01/02
CDY
New Data Sheet
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