ADVANCE
INFORMATION
512K x 8 MoBL Static RAM
CY62148DV30
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05341 Rev. **
Revised June 11, 2003
Features
Very high speed: 55 ns
-- Wide voltage range: 2.20V 1 3.60V
Pin-compatible with CY62148CV25, CY62148CV30, and
CY62148CV33
Ultra low active power
-- Typical active current:1.5 mA @ f = 1 MHz
-- Typical active current: 8 mA @ f = f
max
(55-ns speed)
Ultra low standby power
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered: 36-ball BGA, 32-pin TSOPII, 32-pin
SOIC, and 32-pin STSOP
Functional Description
[1]
The CY62148DV30 is a high-performance CMOS static RAMs
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery LifeTM (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Note:
1.
For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Logic Block Diagram
A
1
COLUMN
DECODER
ROW DECODE
R
SE
NSE A
M
P
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
13
CE
A
14
A
15
A
16
A
17
A
18
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
ADVANCE
INFORMATION
CY62148DV30
Document #: 38-05341 Rev. **
Page 2 of 11
Pin Configuration
[2,3]
FBGA
32 TSOPII
32 SOIC
32 STSOP
Notes:
2.
NC pins are not connected on the die.
3.
DNU pins have to be left floating or tied to V
SS
to ensure proper application.
A
A
A
15
V
CC
A
13
A
12
A
5
NC
WE
A
7
I/O
4
I/O
5
A
4
I/O
6
I/O
7
V
ss
A
11
A
10
A
1
V
SS
I/O
0
A
2
A
8
A
6
A
3
A
0
V
cc
I/O
1
I/O
2
I/O
3
A
17
A
18
A
16
CE
OE
A
9
A
14
D
E
B
A
C
F
G
H
DNU
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
V
CC
A
3
A
2
A
1
A
17
A
16
OE
A
6
A
14
CE
I/O
2
I/O
0
I/O
1
A
12
A
7
21
22
19
20
I/O
7
27
28
25
26
17
18
23
24
V
SS
A
5
A
4
I/O
6
I/O
5
I/O
4
I/O
3
A
10
A
18
A
11
A
0
A
9
A
8
A
13
A
15
Top View
Top View
Top View
Top View
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
V
CC
A
3
A
2
A
1
A
17
A
16
OE
A
6
A
14
CE
I/O
2
I/O
0
I/O
1
A
12
A
7
21
22
19
20
I/O
7
27
28
25
26
17
18
23
24
V
SS
A
5
A
4
I/O
6
I/O
5
I/O
4
I/O
3
A
10
A
18
A
11
A
0
A
9
A
8
A
13
A
15
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
A
17
A
15
A
18
A
10
I/O
3
A
1
A
0
A
3
A
2
26
25
26
27
ADVANCE
INFORMATION
CY62148DV30
Document #: 38-05341 Rev. **
Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................. 65C to +150C
Ambient Temperature with
Power Applied............................................... 55C to +125C
Supply Voltage to Ground
Potential ........................................ 0.3V to V
CC(MAX)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[4,5]
..................................0.2V to V
CC
+ 0.3V
DC Input Voltage
[4,5]
.............................. 0.2V to V
CC
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Product
Range
Ambient
Temperature
V
CC
[6]
CY62148DV30L
Industrial 40C to +85C 2.2V to 3.6V
CY62148DV30LL
Product Portfolio
Product
V
CC
Range
Speed
Power Dissipation
Operating (I
CC
)
Standby (I
SB2
)
f = 1 MHz
f = f
max
Min.
Typ.
[7]
Max.
Typ.
[7]
Max.
Typ.
[7]
Max.
Typ.
[7]
Max.
CY62148DV30L
2.2V
3.0V
3.6V
55 ns
1.5 mA
3 mA
8 mA
15 mA
2
A
12
A
CY62148DV30LL
2.2V
3.0V
3.6V
55 ns
3 mA
10 mA
8
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
CY62148DV30-55
Unit
Min.
Typ.
[7]
Max.
V
OH
Output HIGH Voltage
I
OH
= 0.1 mA
V
CC
= 2.20V
2.0
V
I
OH
= 1.0 mA
V
CC
= 2.70V
2.4
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
V
CC
= 2.20V
0.4
V
I
OL
= 2.1mA
V
CC
= 2.70V
0.4
V
V
IH
Input HIGH Voltage
V
CC
= 2.2V to 2.7V
1.8
V
CC
+ 0.3V
V
V
CC
= 2.7V to 3.6V
2.2
V
CC
+ 0.3V
V
V
IL
Input LOW
Voltage
V
CC
= 2.2V to 2.7V
0.3
0.6
V
V
CC
= 2.7V to 3.6V
0.3
0.8
V
I
IX
Input Leakage Current
GND < V
I
< V
CC
1
+1
A
I
OZ
Output Leakage Current
GND < V
O
< V
CC
, Output Disabled
1
+1
A
I
CC
V
CC
Operating Supply
Current
f = f
MAX
= 1/t
RC
V
CC
=
V
CCmax
I
OUT
= 0 mA
CMOS levels
L
8
15
mA
LL
10
mA
f = 1 MHz
L
1.5
3
mA
LL
mA
I
SB1
Automatic CE
Power-down
Current -- CMOS Inputs
CE > V
CC
-
0.2V,
V
IN
>V
CC
0.2V, V
IN
<0.2V)
f = f
MAX
(Address and Data Only),
f = 0 (OE, and WE), V
CC
=3.60V
L
2
12
A
LL
8
I
SB2
Automatic CE
Power-down
Current -- CMOS Inputs
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
L
2
12
A
LL
8
Notes:
4.
V
IL(min.)
= 2.0V for pulse durations less than 20 ns
5.
V
IH(max)
=V
CC
+0.75V for pulse durations less than 20 ns.
6.
Full Device AC operation requires linear V
CC
ramp from 0 to V
CC
(min) and V
CC
must be stable at V
CC
(min) for >= 500
s.
7.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25C.
ADVANCE
INFORMATION
CY62148DV30
Document #: 38-05341 Rev. **
Page 4 of 11
Capacitance
for all packages
[8]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= V
CC(typ.)
6
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Parameter
Description
Test Conditions
BGA
TSOP II
SOIC
STSOP
Unit
JA
Thermal Resistance
[8]
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
85
76
55
105
C/W
JC
Thermal Resistance
[8]
(Junction to Case)
10
13
22
13
C/W
AC Test Loads and Waveforms
Parameters
2.50V
3.0V
Unit
R1
16667
1103
R2
15385
1554
R
TH
8000
645
V
TH
1.20
1.75
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min. Typ.
[7]
Max. Unit
V
DR
V
CC
for Data Retention
1.5
2.2V
V
I
CCDR
Data Retention Current
V
CC
= 1.5V, CE > V
CC
-
0.2V,
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V
L
9
A
LL
6
A
t
CDR
[8]
Chip Deselect to Data Retention Time
0
ns
t
R
[9]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
Notes:
8.
Tested initially and after any design or process changes that may affect these parameters.
9.
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
s or stable at V
CC(min.)
>
100
s.
V
CC
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Fall time: 1 V/ns
Rise Time: 1 V/ns
1.5V
1.5V
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
V
CC
ADVANCE
INFORMATION
CY62148DV30
Document #: 38-05341 Rev. **
Page 5 of 11
Switching Characteristics
(Over the Operating Range)
[10]
Parameter
Description
55 ns
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[11]
5
ns
t
HZOE
OE HIGH to High Z
[11,12]
20
ns
t
LZCE
CE LOW to Low Z
[11]
10
ns
t
HZCE
CE HIGH to High Z
[11, 12]
20
ns
t
PU
CE LOW to Power-Up
0
ns
t
PD
CE HIGH to Power-up
55
ns
Write Cycle
[13]
t
WC
Write Cycle Time
55
ns
t
SCE
CE LOW to Write End
40
ns
t
AW
Address Set-up to Write End
40
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-up to Write Start
0
ns
t
PWE
WE Pulse Width
40
ns
t
SD
Data Set-up to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[11, 12]
20
ns
t
LZWE
WE HIGH to Low Z
[11]
10
ns
Switching Waveforms
Notes:
10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the "AC Test Loads and Waveforms" section.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
12. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
14. Device is continuously selected. OE, CE = V
IL
.
15. WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
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